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Table 15-10. Interrupt Mode ................................................................................................. 1056

Table 15-11. DMA Mode ...................................................................................................... 1057

Table 15-12. SHA/MD5 Register Map ................................................................................... 1058

Table 15-13. SHA/MD5 Inner/Outer Digest/HMAC Key Register Mapping ............................... 1060

Table 16-1. Available CCP Pins .......................................................................................... 1080

Table 16-2. General-Purpose Timers Signals (128TQFP) ..................................................... 1081

Table 16-3. General-Purpose Timer Capabilities .................................................................. 1082

Table 16-4. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes ........ 1084

Table 16-5. 16-Bit Timer With Prescaler Configurations ........................................................ 1085

Table 16-6. Counter Values When the Timer is Enabled in RTC Mode .................................. 1086

Table 16-7. Counter Values When the Timer is Enabled in Input Edge-Count Mode ............... 1087

Table 16-8. Counter Values When the Timer is Enabled in Input Event-Count Mode .............. 1088

Table 16-9. Counter Values When the Timer is Enabled in PWM Mode ................................. 1090

Table 16-10. Timeout Actions for GPTM Modes ..................................................................... 1093

Table 16-11. Timers Register Map ........................................................................................ 1098

Table 17-1. Watchdog Timers Register Map ........................................................................ 1155

Table 18-1. ADC Signals (128TQFP) .................................................................................. 1179

Table 18-2. Samples and FIFO Depth of Sequencers .......................................................... 1180

Table 18-3. Sample and Hold Width in ADC Clocks ............................................................. 1182

Table 18-4. R

and F

CONV

Values with Varying N

Values and F

ADC

= 16 MHz ..................... 1183

Table 18-5. R

and F

CONV

Values with Varying N

Values and F

ADC

= 32 MHz ..................... 1183

Table 18-6. Differential Sampling Pairs ............................................................................... 1190

Table 18-7. ADC Register Map ........................................................................................... 1197

Table 18-8. Sample and Hold Width in ADC Clocks ............................................................. 1251

Table 18-9. Sample and Hold Width in ADC Clocks ............................................................. 1263

Table 18-10. Sample and Hold Width in ADC Clocks ............................................................. 1271

Table 19-1. UART Signals (128TQFP) ................................................................................ 1287

Table 19-2. Flow Control Mode ........................................................................................... 1293

Table 19-3. UART Register Map ......................................................................................... 1297

Table 20-1. SSI Signals (128TQFP) .................................................................................... 1352

Table 20-2. QSSI Transaction Encodings ............................................................................ 1355

Table 20-3. SSInFss Functionality ...................................................................................... 1355

Table 20-4. Legacy Mode TI, Freescale SPI Frame Format Features .................................... 1357

Table 20-5. SSI Register Map ............................................................................................. 1367

Table 21-1. I2C Signals (128TQFP) .................................................................................... 1401

Table 21-2. Examples of I

C Master Timer Period Versus Speed Mode ................................. 1408

Table 21-3. Examples of I

C Master Timer Period in High-Speed Mode ................................ 1409

Table 21-4. Inter-Integrated Circuit (I

C) Interface Register Map ........................................... 1424

Table 21-5. Write Field Decoding for I2CMCS[6:0] ............................................................... 1432

Table 22-1. Controller Area Network Signals (128TQFP) ...................................................... 1481

Table 22-2. Message Object Configurations ........................................................................ 1487

Table 22-3. CAN Protocol Ranges ...................................................................................... 1495

Table 22-4. CANBIT Register Values .................................................................................. 1495

Table 22-5. CAN Register Map ........................................................................................... 1499

Table 23-1. Ethernet Signals (128TQFP) ............................................................................. 1533

Table 23-2. Enhanced Transmit Descriptor 0 (TDES0) ......................................................... 1538

Table 23-3. Enhanced Transmit Descriptor 1 (TDES1) ......................................................... 1541

Table 23-4. Enhanced Transmit Descriptor 2 (TDES2) ......................................................... 1542

21June 18, 2014

Texas Instruments-Production Data

Tiva

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TM4C129ENCPDT Microcontroller