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Table 10-8. GPIO Pins With Special Considerations .............................................................. 778

Table 10-9. GPIO Pins With Special Considerations .............................................................. 784

Table 10-10. GPIO Pins With Special Considerations .............................................................. 786

Table 10-11. GPIO Pins With Special Considerations .............................................................. 789

Table 10-12. GPIO Pins With Special Considerations .............................................................. 795

Table 10-13. GPIO Drive Strength Options .............................................................................. 808

Table 11-1. External Peripheral Interface Signals (128TQFP) ................................................. 825

Table 11-2. EPI Interface Options ......................................................................................... 830

Table 11-3. EPI SDRAM x16 Signal Connections .................................................................. 831

Table 11-4. CSCFGEXT + CSCFG Encodings ...................................................................... 835

Table 11-5. Dual- and Quad- Chip Select Address Mappings ................................................. 836

Table 11-6. Chip Select Configuration Register Assignment ................................................... 837

Table 11-7. Capabilities of Host Bus 8 and Host Bus 16 Modes .............................................. 837

Table 11-8. EPI Host-Bus 8 Signal Connections .................................................................... 839

Table 11-9. EPI Host-Bus 16 Signal Connections .................................................................. 841

Table 11-10. PSRAM Fixed Latency Wait State Configuration .................................................. 846

Table 11-11. Data Phase Wait State Programming .................................................................. 851

Table 11-12. EPI General-Purpose Signal Connections ........................................................... 857

Table 11-13. External Peripheral Interface (EPI) Register Map ................................................. 862

Table 11-14. CSCFGEXT + CSCFG Encodings ...................................................................... 888

Table 11-15. CSCFGEXT + CSCFG Encodings ...................................................................... 894

Table 12-1. Endian Configuration ......................................................................................... 955

Table 12-2. Endian Configuration with Bit Reversal ................................................................ 955

Table 12-3. CCM Register Map ............................................................................................ 957

Table 13-1. Key-Block-Round Combinations ......................................................................... 967

Table 13-2. Interrupts and Events ......................................................................................... 976

Table 13-3. AES Module Performance (Input/Output Block Size = 128) ................................... 977

Table 13-4. AES Module Packet Mode Switch Overhead ....................................................... 978

Table 13-5. AES Register Map ............................................................................................. 984

Table 13-6. AES Key Register Descriptions ........................................................................... 987

Table 14-1. Key Repartition ................................................................................................ 1016

Table 14-2. DES Reset Description ..................................................................................... 1018

Table 14-3. DES Global Initialization ................................................................................... 1020

Table 14-4. DES Algorithm Type Configuration .................................................................... 1021

Table 14-5. 3DES Algorithm Type Configuration .................................................................. 1021

Table 14-6. DES Interrupt Mode ......................................................................................... 1022

Table 14-7. DES DMA Mode .............................................................................................. 1022

Table 14-8. DES Register Map ........................................................................................... 1024

Table 14-9. DES Key Register Mapping .............................................................................. 1026

Table 15-1. Interrupts and Events ....................................................................................... 1047

Table 15-2. SHA/MD5 Module Algorithm Selection .............................................................. 1047

Table 15-3. Outer Digest Registers ..................................................................................... 1048

Table 15-4. Inner Digest Registers ...................................................................................... 1049

Table 15-5. SHA Digest Processed in Three Passes ............................................................ 1051

Table 15-6. SHA Digest Processed in One Pass .................................................................. 1051

Table 15-7. SHA/MD5 Performance .................................................................................... 1053

Table 15-8. Continuing a Prior HMAC ................................................................................. 1055

Table 15-9. SHA-1 Apply on the Key ................................................................................... 1056

June 18, 201420

Texas Instruments-Production Data

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