Datasheet

30.18 Inter-Integrated Circuit (I
2
C) Interface
Table 30-48. I
2
C Characteristics
UnitMaxNomMinParameter NameParameterParameter
No.
system clocks--36Start condition hold timeT
SCH
I1
a
system clocks--36Clock Low periodT
LP
I2
a
ns(see note
b)
--I2CSCL/I2CSDA rise time (V
IL
=0.5 V
to V
IH
=2.4 V)
T
SRT
I3
b
system clocks-2-Data hold time (slave)
T
DH
I4
system clocks-7-Data hold time (master)
ns109-I2CSCL/I2CSDA fall time (V
IH
=2.4 V
to V
IL
=0.5 V)
T
SFT
I5
c
system clocks--24Clock High timeT
HT
I6
a
system clocks--18Data setup timeT
DS
I7
system clocks--36Start condition setup time (for
repeated start condition only)
T
SCSR
I8
a
system clocks--24Stop condition setup timeT
SCS
I9
a
system clocks-2-Data Valid (slave)
T
DV
I10
system clocks-(6 * (1 +
TPR)) + 1
-Data Valid (master)
a. Values depend on the value programmed into the TPR bit in the I
2
C Master Timer Period (I2CMTPR) register; a TPR
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I
2
C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
b. Because I2CSCL and I2CSDA operate as open-drain-type signals, which the controller can only actively drive low, the
time I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
c. Specified at a nominal 50 pF load.
Figure 30-33. I
2
C Timing
I2CSCL
I2CSDA
I1
I2
I6
I7 I8
I5
I3 I9
I4
I10
June 18, 20141994
Texas Instruments-Production Data
Electrical Characteristics