Datasheet

30.14.1 Types of I/O Pins and ESD Protection
Caution – All device I/Os pins, except for PB1, are NOT 5V tolerant; voltages in excess of the limits
shown in Table 30-6 on page 1944 can permanently damage the device. PB1 is used for the USB's
USB0VBUS signal, which requires a 5-V input.
30.14.1.1 Hibernate WAKE pin
The Hibernate WAKE pin uses ESD protection, similar to the one shown in Figure 30-16 on page 1975.
This ESD protection prevents a direct path between this pad and any power supply rails in the
device. The WAKE pad input voltage should be kept inside the maximum ratings specified in Table
30-1 on page 1942 to ensure current leakage and current injections are within acceptable range.
Current leakages and current injection for these pins are specified in Table 30-36 on page 1975.
Figure 30-16. ESD Protection
Table 30-36. Pad Voltage/Current Characteristics for Hibernate WAKE Pin
ab
UnitMaxNomMinParameter NameParameter
nA300--Positive IO leakage for V
DD
≤ V
IN
≤V
BAT
+ 0.3VI
LKG+
µA43.3--Negative IO leakage for-0.3V ≤ V
IN
≤0V
c
I
LKG-
mA2--Max positive injection if not voltage protected
d
I
INJ+
mA-0.5--Max negative injection if not voltage protected
d
I
INJ-
a. V
IN
must be within the range specified in Table 30-1 on page 1942. Leakage current outside of this maximum voltage is not
guaranteed and can result in permanent damage of the device.
b. VDD must be within the range specified in Table 30-6 on page 1944.
c. Leakage outside the minimum range (-0.3V) is unbounded and must be limited to I
INJ-
using an external resistor.
d. If the I/O pad is not voltage limited, it should be current limited (to I
INJ
+ and I
INJ-
) if there is any possibility of the pad voltage
exceeding the V
IO
limits (including transient behavior during supply ramp up, or at any time when the part is unpowered).
30.14.1.2 Non-Power I/O Pins
Most non-power I/Os (with the exception of the I/O pad for Hibernate WAKE input) have ESD protection
as shown in Figure 30-17 on page 1976.
These I/Os have an ESD clamp to ground and a diode connection to the corresponding power
supply rail. The voltage and current of these I/Os should follow the specifications in Table
30-37 on page 1976 to prevent potential damage to the device. In addition, it is recommended that
the ADC external reference specifications in Table 30-44 on page 1985 be adhered to prevent any
gain error.
1975June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C129ENCPDT Microcontroller