Datasheet

in operational ranges. The BOR monitor is used to generate a reset to the device or assert an
interrupt if the V
DD
supply drops below its operational range.
Note: V
DDA
BOR and V
DD
BOR events are a combined BOR to the system logic, such that if either
BOR event occurs, the following bits are affected:
■ BORRIS bit in the Raw Interrupt Status (RIS) register, System Control offset 0x050.
See page 268.
■ BORMIS bit in the Masked Interrupt Status and Clear (MISC) register, System Control
offset 0x058. This bit is set only if the BORIM bit in the Interrupt Mask Control (IMC)
register has been set. See page 270 and page 272.
■ BOR bit in the Reset Cause (RESC) register, System Control offset 0x05C. This bit is
set only if either of the BOR events have been configured to initiate a reset. See page 274.
In addition, the following bits control both BOR events:
■ BORIM bit in the Interrupt Mask Control (IMC) register, System Control offset 0x054.
■ VDDA_UBOR0 and VDD_UBOR0 bits in the Power-Temperature Cause (PWRTC) register.
Please refer to “System Control” on page 227 for more information on how to configure these
registers.
Figure 30-5 on page 1952 shows the relationship between V
DD
, POK, POR and a BOR event.
Figure 30-5. Power and Brown-Out Assertions vs V
DD
Levels
P2
VDD
P7
RISE
P8
POK
VDD
MIN
1
0
P7
FALL
BOR
1
0
30.6.3 V
DDC
Levels
The V
DDC
supply has one monitor, the Power-OK (POK). The POK monitor is used to keep the
digital circuitry in reset until the V
DDC
power supply is at an acceptable operational level. The digital
reset is only released when the Power-On Reset has deasserted and all of the Power-OK monitors
for each of the supplies indicate that power levels are in operational ranges. Figure 30-6 on page 1953
shows the relationship between POK and V
DDC
.
June 18, 20141952
Texas Instruments-Production Data
Electrical Characteristics