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Table 5-18. Module Power Control ........................................................................................ 463

Table 5-19. Module Power Control ........................................................................................ 468

Table 5-20. Module Power Control ........................................................................................ 470

Table 5-21. Module Power Control ........................................................................................ 472

Table 5-22. Module Power Control ........................................................................................ 474

Table 5-23. Module Power Control ........................................................................................ 477

Table 5-24. Module Power Control ........................................................................................ 479

Table 5-25. Module Power Control ........................................................................................ 483

Table 5-26. Module Power Control ........................................................................................ 485

Table 5-27. Module Power Control ........................................................................................ 487

Table 5-28. Module Power Control ........................................................................................ 489

Table 5-29. Module Power Control ........................................................................................ 491

Table 5-30. Module Power Control ........................................................................................ 493

Table 5-31. Module Power Control ........................................................................................ 495

Table 5-32. Module Power Control ........................................................................................ 497

Table 5-33. Module Power Control ........................................................................................ 499

Table 5-34. Module Power Control ........................................................................................ 501

Table 6-1. System Exception Register Map ......................................................................... 531

Table 7-1. Hibernate Signals (128TQFP) ............................................................................. 542

Table 7-2. HIB Clock Source Configurations ........................................................................ 543

Table 7-3. Hibernation Module Register Map ....................................................................... 560

Table 8-1. MEMTIM0 Register Configuration versus Frequency ............................................ 613

Table 8-2. Flash Memory Protection Policy Combinations .................................................... 618

Table 8-3. User-Programmable Flash Memory Resident Registers ....................................... 622

Table 8-4. MEMTIM0 Register Configuration versus Frequency ............................................ 625

Table 8-5. Master Memory Access Availability ..................................................................... 629

Table 8-6. Flash Register Map ............................................................................................ 630

Table 9-1. μDMA Channel Assignments .............................................................................. 688

Table 9-2. Request Type Support ....................................................................................... 690

Table 9-3. Control Structure Memory Map ........................................................................... 692

Table 9-4. Channel Control Structure .................................................................................. 692

Table 9-5. μDMA Read Example: 8-Bit Peripheral ................................................................ 701

Table 9-6. μDMA Interrupt Assignments .............................................................................. 702

Table 9-7. Channel Control Structure Offsets for Channel 30 ................................................ 703

Table 9-8. Channel Control Word Configuration for Memory Transfer Example ...................... 704

Table 9-9. Channel Control Structure Offsets for Channel 7 .................................................. 705

Table 9-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 705

Table 9-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 707

Table 9-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive

Example ............................................................................................................ 707

Table 9-13. μDMA Register Map .......................................................................................... 709

Table 10-1. GPIO Pins With Special Considerations .............................................................. 751

Table 10-2. GPIO Pins and Alternate Functions (128TQFP) ................................................... 751

Table 10-3. GPIO Drive Strength Options .............................................................................. 761

Table 10-4. GPIO Pad Configuration Examples ..................................................................... 762

Table 10-5. GPIO Interrupt Configuration Example ................................................................ 763

Table 10-6. GPIO Pins With Special Considerations .............................................................. 764

Table 10-7. GPIO Register Map ........................................................................................... 765

19June 18, 2014

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TM4C129ENCPDT Microcontroller