Datasheet

Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020
This register contains enables for each of the QEI module interrupts. An interrupt is asserted to the
interrupt controller if the corresponding bit in this register is set.
QEI Interrupt Enable (QEIINTEN)
QEI0 base: 0x4002.C000
Offset 0x020
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INTINDEXINTTIMER
INTDIR
INTERROR
reserved
RWRWRWRWROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:4
Phase Error Interrupt Enable
Note: The INTERROR bit is only applicable when the QEI is operating
in quadrature phase mode (SIGMODE=0) and should be
masked when SIGMODE =1.
DescriptionValue
The INTERROR interrupt is suppressed and not sent to the
interrupt controller.
0
An interrupt is sent to the interrupt controller when the
INTERROR bit in the QEIRIS register is set.
1
0RWINTERROR3
Direction Change Interrupt Enable
DescriptionValue
The INTDIR interrupt is suppressed and not sent to the interrupt
controller.
0
An interrupt is sent to the interrupt controller when the INTDIR
bit in the QEIRIS register is set.
1
0RWINTDIR2
Timer Expires Interrupt Enable
DescriptionValue
The INTTIMER interrupt is suppressed and not sent to the
interrupt controller.
0
An interrupt is sent to the interrupt controller when the
INTTIMER bit in the QEIRIS register is set.
1
0RWINTTIMER1
1889June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C129ENCPDT Microcontroller