Datasheet

List of Tables
Table 1. Revision History .................................................................................................. 49
Table 2. Documentation Conventions ................................................................................ 53
Table 1-1. TM4C129ENCPDT Microcontroller Features ......................................................... 56
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 91
Table 2-2. Processor Register Map ....................................................................................... 92
Table 2-3. PSR Register Combinations ................................................................................. 98
Table 2-4. Memory Map ..................................................................................................... 109
Table 2-5. Memory Access Behavior ................................................................................... 113
Table 2-6. SRAM Memory Bit-Banding Regions ................................................................... 115
Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................. 115
Table 2-8. Exception Types ................................................................................................ 121
Table 2-9. Interrupts .......................................................................................................... 122
Table 2-10. Exception Return Behavior ................................................................................. 130
Table 2-11. Faults ............................................................................................................... 131
Table 2-12. Fault Status and Fault Address Registers ............................................................ 132
Table 2-13. Cortex-M4F Instruction Summary ....................................................................... 134
Table 3-1. Core Peripheral Register Regions ....................................................................... 141
Table 3-2. Memory Attributes Summary .............................................................................. 145
Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 147
Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 148
Table 3-5. AP Bit Field Encoding ........................................................................................ 148
Table 3-6. Memory Region Attributes for Tiva™ C Series Microcontrollers ............................. 149
Table 3-7. QNaN and SNaN Handling ................................................................................. 152
Table 3-8. Peripherals Register Map ................................................................................... 153
Table 3-9. Interrupt Priority Levels ...................................................................................... 178
Table 3-10. Example SIZE Field Values ................................................................................ 206
Table 4-1. JTAG_SWD_SWO Signals (128TQFP) ............................................................... 215
Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 217
Table 4-3. JTAG Instruction Register Commands ................................................................. 223
Table 5-1. System Control & Clocks Signals (128TQFP) ...................................................... 227
Table 5-2. Reset Sources ................................................................................................... 228
Table 5-3. Clock Source Options ........................................................................................ 238
Table 5-4. Clock Source State Following POR ..................................................................... 238
Table 5-5. System Clock Frequency ................................................................................... 242
Table 5-6. System Divisor Factors for f
vco
=480 MHz ............................................................ 244
Table 5-7. Actual PLL Frequency ........................................................................................ 245
Table 5-8. Peripheral Memory Power Control ...................................................................... 250
Table 5-9. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 251
Table 5-10. MOSC Configurations ........................................................................................ 254
Table 5-11. System Control Register Map ............................................................................. 254
Table 5-12. MEMTIM0 Register Configuration versus Frequency ............................................ 284
Table 5-13. MOSC Configurations ........................................................................................ 288
Table 5-14. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 307
Table 5-15. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 310
Table 5-16. Module Power Control ........................................................................................ 458
Table 5-17. Module Power Control ........................................................................................ 460
June 18, 201418
Texas Instruments-Production Data
Table of Contents