Datasheet

Register 81: Ethernet PHY Configuration 1 - MR9 (EPHYCFG1), address 0x009
This register configuration for the Ethernet PHY. These configuration values are programmed by
the system processor after a POR. The DONE bit in the EPHYCFG1 register is set when configuration
is complete. This register is used when the user requires a configuration different from what is
provided in the EMACPC register.
Ethernet PHY Configuration 1 - MR9 (EPHYCFG1)
Base n/a
Address 0x009
Type RW, reset 0x0000
0123456789101112131415
reserved
FRXDVDET
FANSEL
FASTANEN
RAMDIXFAMDIXLLRTDRARreservedDONE
RORWRWRWRWRWRWRWRWROROROROROROWOType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Configuration Done
This bit reads as a zero. The application must write a one to this bit to
terminate the PHYHOLD mode set in the EMACPC register and wake
up the EPHY.
DescriptionValue
Configuration process is not complete.0
Configuration process is complete, and the PHY can continue
and complete its internal reset sequence.
1
0WODONE15
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved14:9
TDR Auto-Run at Link Down
DescriptionValue
Disable automatic execution of TDR.0
Enable execution of TDR procedure after link down event.1
0RWTDRAR8
Link Loss Recovery
DescriptionValue
Normal Link Loss operation
Link status goes down approximately 250 µs from signal loss.
0
Enable Link Loss Recovery mechanism
This mode allows recovery from short interference and continues
to hold the link up for a period of an additional few µs until the
short interference is gone and the signal is OK.
1
0RWLLR7
June 18, 20141730
Texas Instruments-Production Data
Ethernet Controller