Datasheet

DescriptionResetTypeNameBit/Field
Start or Stop Transmission Command
When this bit is set, transmission is placed in the running state. The
DMA attempts to acquire the descriptor from the Transmit Descriptor
List. Descriptor acquisition is attempted from the current position in the
list, which is the Transmit List Base Address set by Transmit Descriptor
List Address (EMACTXDLADDR) register, or from the position retained
when transmission was stopped previously.
If the DMA does not own the current descriptor, transmission enters the
suspended state and bit[2] (Transmit Buffer Unavailable, TU) of the MAC
DMA Raw Interrupt Status Register (EMACDMARIS) is set. The Start
Transmission command is effective only when transmission is stopped.
If the command is issued before setting EMACTXDLADDR, then the
DMA behavior is unpredictable.
When this bit is cleared, the transmission process is placed in the
Stopped state after completing the transmission of the current frame.
The Next Descriptor position in the Transmit List is saved, and it
becomes the current position when transmission is restarted. To change
the list address, you need to program EMACTXDLADDR with a new
value when this bit is reset. The new value is considered when this bit
is set again. The stop transmission command is effective only when the
transmission of the current frame is complete or the transmission is in
the Suspended state.
DescriptionValue
Transmission process is placed in the stopped state after
completing the transmission of the current frame. The Next
Descriptor position in the Transmit List is saved, and it becomes
the current position when transmission is restarted.
0
Transmission is placed in the running state, and the DMA checks
the transmit list at the current position for a frame to be
transmitted.
1
0x0RWST13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved12:8
Forward Error Frames
When this bit is reset, the RX FIFO drops frames with error status (CRC
error, collision error, MII_ER, giant frame, watchdog timeout, or overflow).
However, if the start byte (write) pointer of a frame is already transferred
to the RX controller side (in Threshold mode), then the frame is not
dropped.
When the FEF bit is set, all frames except runt error frames are
forwarded to the DMA. If Bit 25, Receive Store and Forward (RSF), is
set and the RX FIFO overflows when a partial frame is written, then the
frame is dropped irrespective of the FEF bit setting. However, if the RSF
is reset and the RX FIFO overflows when a partial frame is written, then
a partial frame may be forwarded to the DMA.
DescriptionValue
The Receive FIFO drops frames with error status0
All frames except runt error frames are forwarded to the DMA.1
0x0RWFEF7
1693June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C129ENCPDT Microcontroller