Datasheet

Register 22: Ethernet MAC Watchdog Timeout (EMACWDOGTO), offset 0x0DC
This register controls the watchdog counter for received frames.
Ethernet MAC Watchdog Timeout (EMACWDOGTO)
Base 0x400E.C000
Offset 0x0DC
Type RW, reset 0x0000.0000
16171819202122232425262728293031
PWEreserved
RWROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
WTOreserved
RWRWRWRWRWRWRWRWRWRWRWRWRWRWROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:17
Programmable Watchdog Enable
DescriptionValue
The watchdog timeout for a received frame is controlled by
setting the WD and JE bits in the EMACCFG register.
0
When the WD bit of the EMACCFG register is clear, the WTO
field is used as a watchdog timeout for a received frame.
1
0RWPWE16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:14
Watchdog Timeout
When the PWE bit in the EMACWDOGTO register is set and the WD bit
of the EMACCFG register is clear, this field is used as a watchdog
timeout value for a received frame. If the length of a received frame
exceeds the value of this field, such frame is terminated and declared
an error frame.
Note: When the PWE bit is set the value in this field should be more
than 1,522 (0x05F2). Otherwise, valid, tagged IEEE 802.3-
frames are declared as error frames and are dropped.
0RWWTO13:0
1635June 18, 2014
Texas Instruments-Production Data
Tiva
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TM4C129ENCPDT Microcontroller