Datasheet

Register 9: Ethernet MAC Status (EMACSTATUS), offset 0x024
The Ethernet MAC Status (EMACSTATUS) register gives the status of all main modules of the
transmit and receive data-paths and the FIFOs. An all-zero status indicates that the MAC is in idle
state (and FIFOs are empty) and no activity is going on in the data-paths.
Ethernet MAC Status (EMACSTATUS)
Base 0x400E.C000
Offset 0x024
Type RO, reset 0x0000.0000
16171819202122232425262728293031
TPETFC
TXPAUSED
TRCTWCreservedTXFETXFFreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RPERFCFCreservedRWCRRCreservedRXFreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:26
TX/RX Controller TX FIFO Full Status
DescriptionValue
The TX/RX Controller TX FIFO is not full.0
The TX/RX Controller TX FIFO is full. Therefore, the TX/RX
Controller cannot accept any more frames for transmission.
1
0ROTXFF25
TX/RX Controller TX FIFO Not Empty Status
DescriptionValue
TX/RX Controller TX FIFO is empty.0
TX/RX Controller TX FIFO is not empty and some data is left
for transmission.
1
0ROTXFE24
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved23
TX/RX Controller TX FIFO Write Controller Active Status
DescriptionValue
TX/RX Controller's TX FIFO write controller is inactive.0
TX/RX Controller's TX FIFO write controller is active and
transferring data to the TX FIFO.
1
0ROTWC22
1615June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C129ENCPDT Microcontroller