Datasheet

Figure 21-7. High-Speed Data Format .................................................................................. 1410
Figure 21-8. Master Single TRANSMIT ................................................................................ 1414
Figure 21-9. Master Single RECEIVE ................................................................................... 1415
Figure 21-10. Master TRANSMIT of Multiple Data Bytes ......................................................... 1416
Figure 21-11. Master RECEIVE of Multiple Data Bytes ............................................................ 1417
Figure 21-12. Master RECEIVE with Repeated START after Master TRANSMIT ....................... 1418
Figure 21-13. Master TRANSMIT with Repeated START after Master RECEIVE ....................... 1419
Figure 21-14. Standard High Speed Mode Master Transmit ..................................................... 1420
Figure 21-15. Slave Command Sequence .............................................................................. 1421
Figure 22-1. CAN Controller Block Diagram .......................................................................... 1481
Figure 22-2. CAN Data/Remote Frame ................................................................................. 1482
Figure 22-3. Message Objects in a FIFO Buffer .................................................................... 1491
Figure 22-4. CAN Bit Time ................................................................................................... 1495
Figure 23-1. Ethernet MAC with Integrated PHY Interface ..................................................... 1532
Figure 23-2. Ethernet MAC and PHY Clock Structure ............................................................ 1534
Figure 23-3. Enhanced Transmit Descriptor Structure ........................................................... 1538
Figure 23-4. Enhanced Receive Descriptor Structure ............................................................ 1543
Figure 23-5. TX DMA Default Operation Using Descriptors .................................................... 1550
Figure 23-6. TX DMA OSF Mode Operation Using Descriptors .............................................. 1552
Figure 23-7. RX DMA Operation Flow .................................................................................. 1555
Figure 23-8. Networked Time Synchronization ...................................................................... 1565
Figure 23-9. System Time Update Using Fine Correction Method .......................................... 1567
Figure 23-10. Propagation Delay Calculation in Clocks Supporting Peer-to-Peer Path
Correction ....................................................................................................... 1570
Figure 23-11. Wake-Up Frame Filter Register Bank ................................................................ 1578
Figure 23-12. Integrated PHY Diagram .................................................................................. 1582
Figure 23-13. Interface to Ethernet Jack ................................................................................. 1588
Figure 24-1. USB Module Block Diagram ............................................................................. 1769
Figure 25-1. Analog Comparator Module Block Diagram ....................................................... 1778
Figure 25-2. Structure of Comparator Unit ............................................................................ 1779
Figure 25-3. Comparator Internal Reference Structure .......................................................... 1780
Figure 26-1. PWM Module Diagram ..................................................................................... 1795
Figure 26-2. PWM Generator Block Diagram ........................................................................ 1795
Figure 26-3. PWM Count-Down Mode .................................................................................. 1798
Figure 26-4. PWM Count-Up/Down Mode ............................................................................. 1798
Figure 26-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1799
Figure 26-6. PWM Dead-Band Generator ............................................................................. 1799
Figure 27-1. QEI Block Diagram .......................................................................................... 1873
Figure 27-2. QEI Input Signal Logic ...................................................................................... 1874
Figure 27-3. Quadrature Encoder and Velocity Predivider Operation ...................................... 1876
Figure 28-1. 128-Pin TQFP Package Pin Diagram ................................................................ 1895
Figure 30-1. Load Conditions ............................................................................................... 1947
Figure 30-2. JTAG Test Clock Input Timing ........................................................................... 1949
Figure 30-3. JTAG Test Access Port (TAP) Timing ................................................................ 1949
Figure 30-4. Power and Brown-Out Assertions vs V
DDA
Levels .............................................. 1951
Figure 30-5. Power and Brown-Out Assertions vs V
DD
Levels ................................................ 1952
Figure 30-6. POK Assertion vs V
DDC
................................................................................... 1953
Figure 30-7. POR-BOR V
DD
Glitch Response ....................................................................... 1953
June 18, 201416
Texas Instruments-Production Data
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