Datasheet

23.3.2.4 DMA Arbiter
The arbiter inside the DMA module performs the arbitration between the Transmit and Receive
channel accesses. The DMA can be configured to arbitrate in a round-robin or fixed-priority
configuration. When the DA bit of the EMACDMABUSMOD register is clear, the DMA arbiter allocates
the data bus in the ratio set by the PR bit field of the EMACDMABUSMOD register when both the
TX and RX DMA request access at the same time. When the DA bit is set, the RX DMA always has
priority over the TX DMA for data access by default. However if the TXPR bit of the
EMACDMABUSMOD register is also set, then the TX DMA always gets priority over the RX DMA.
23.3.2.5 Enhanced and Alternate Descriptors
Enhanced Descriptors can contain up to eight words (32 bytes) and buffers of up to 8 KB (useful
for Jumbo frames). Enhanced Descriptors support IEEE 1588-2008 Advanced Timestamp and IPC
Full Checksum (Type 2) Offload. These enhanced features are enabled with the TSEN bit of the
EMACTIMSTCTRL register and the IPC bit of the EMACCFG register, respectively.
When using Enhanced Descriptors, set the descriptor size to eight words with the Alternate Descriptor
Size (ATDS) bit in the Ethernet MAC DMA Bus Mode (EMACDMABUSMOD) register. If these
enhanced features are not enabled, the extended descriptors (DES4 to DES7) are not required.
Therefore, the software can use Alternate Descriptors with a default size of 16 bytes (4 words). For
alternate descriptors, the software should clear the Alternate Descriptor Size (ATDS) bit in the
Ethernet MAC DMA Bus Mode (EMACDMABUSMOD) register.
See the section called “Enhanced Transmit Descriptor” on page 1537 and the section called “Enhanced
Receive Descriptor” on page 1542 for more details on the descriptor structure.
Enhanced Transmit Descriptor
The MAC requires at least one descriptor for a transmit frame. In addition to two buffers, two
byte-count buffers, and two address pointers, the transmit descriptor has control fields which can
be used to control the MAC operation on per-transmit frame basis. Figure 23-3 on page 1538 shows
the enhanced transmit descriptor. Software must program the control bits TDES0[31:18] during
descriptor initialization. When the DMA updates the descriptor, it writes back all the control bits to
their initialized value, clears the OWN bit and updates the status bits.
With advanced timestamp support, the snapshot of the timestamp to be taken can be enabled for
a given frame by setting Bit 25 (TTSE) of TDES0. When the descriptor is closed (that is, when the
OWN bit is cleared), the timestamp is written into TDES6 and TDES7.
Note: When the Advanced Timestamp feature is enabled, software should set the ATDS bit of the
Ethernet MAC DMA Bus Mode (EMACDMABUSMOD) register, offset 0xC00, so that the
DMA operates with extended descriptor size. When this control bit is reset to the default
(0), the TDES4-TDES7 descriptor space is not valid and only Alternate Descriptors are
available, with a default size of 16 bytes (4 words).
1537June 18, 2014
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