Datasheet

Table 23-1. Ethernet Signals (128TQFP)
DescriptionBuffer TypePin TypePin Mux / Pin
Assignment
Pin NumberPin Name
Ethernet 0 LED 0.TTLOPF0 (5)
PK4 (5)
42
63
EN0LED0
Ethernet 0 LED 1.TTLOPF4 (5)
PK6 (5)
46
61
EN0LED1
Ethernet 0 LED 2.TTLOPF1 (5)
PK5 (5)
43
62
EN0LED2
Ethernet 0 Pulse-Per-Second (PPS) Output.TTLOPG0 (5)
PJ0 (5)
49
116
EN0PPS
Ethernet PHY negative receive differential input.TTLI/Ofixed53EN0RXIN
Ethernet PHY positive receive differential input.TTLI/Ofixed54EN0RXIP
Ethernet PHY negative transmit differential output.TTLI/Ofixed56EN0TXON
Ethernet PHY positive transmit differential output.TTLI/Ofixed57EN0TXOP
4.87-kΩ resistor (1% precision) for Ethernet PHY.AnalogOfixed59RBIAS
23.3 Functional Description
The Ethernet Controller is made up of the following sub-modules:
■ Clock Control
■ DMA Controller
■ Transmit/Receive Controller (TX/RX Controller)
■ Media Access Controller (MAC)
■ AHB Bus Interface
■ PHY Interface
The following sections describe the features and functions of each sub-module.
23.3.1 Ethernet Clock Control
23.3.1.1 PHY Interface
The Ethernet Controller Module and Integrated PHY receive two clock inputs:
■ A gated system clock acts as the clock source to the Control and Status registers (CSR) of the
Ethernet MAC. The SYSCLK frequency for Run, Sleep and Deep Sleep mode is programmed
in the System Control module. Refer to “System Control” on page 227 for more information on
programming SYSCLK and enabling the Ethernet MAC.
■ The PHY receives the main oscillator (MOSC) which must be 25 MHz ± 50 ppm for proper
operation. The MOSC source can be a single-ended source or a crystal. Figure 23-2 on page 1534
shows the clock inputs to the Ethernet Controller Module.
1533June 18, 2014
Texas Instruments-Production Data
Tiva
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TM4C129ENCPDT Microcontroller