Datasheet

Figure 14-4. DES3DES-CFB Feedback Mode ....................................................................... 1020
Figure 14-5. DES Polling Mode ............................................................................................ 1022
Figure 14-6. DES Interrupt Service ...................................................................................... 1023
Figure 14-7. DES Context Input Event Service ...................................................................... 1024
Figure 15-1. SHA/MD5 Module Block Diagram ..................................................................... 1045
Figure 15-2. SHA/MD5 Polling Mode .................................................................................... 1056
Figure 15-3. SHA/MD5 Interrupt Subroutine ......................................................................... 1058
Figure 16-1. GPTM Module Block Diagram ........................................................................... 1080
Figure 16-2. Input Edge-Count Mode Example, Counting Down ............................................. 1088
Figure 16-3. 16-Bit Input Edge-Time Mode Example ............................................................. 1089
Figure 16-4. 16-Bit PWM Mode Example .............................................................................. 1091
Figure 16-5. CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................. 1091
Figure 16-6. CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................. 1092
Figure 16-7. CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................. 1092
Figure 16-8. Timer Daisy Chain ........................................................................................... 1093
Figure 17-1. WDT Module Block Diagram ............................................................................. 1153
Figure 18-1. Implementation of Two ADC Blocks .................................................................. 1178
Figure 18-2. ADC Module Block Diagram ............................................................................. 1179
Figure 18-3. ADC Sample Phases ....................................................................................... 1184
Figure 18-4. Doubling the ADC Sample Rate ........................................................................ 1184
Figure 18-5. Skewed Sampling ............................................................................................ 1185
Figure 18-6. Sample Averaging Example .............................................................................. 1187
Figure 18-7. ADC Input Equivalency .................................................................................... 1188
Figure 18-8. ADC Voltage Reference ................................................................................... 1188
Figure 18-9. ADC Conversion Result ................................................................................... 1189
Figure 18-10. Differential Voltage Representation ................................................................... 1191
Figure 18-11. Internal Temperature Sensor Characteristic ....................................................... 1192
Figure 18-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0) .............................................. 1194
Figure 18-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ............................................... 1195
Figure 18-14. High-Band Operation (CIC=0x3 and/or CTC=0x3) .............................................. 1196
Figure 19-1. UART Module Block Diagram ........................................................................... 1286
Figure 19-2. UART Character Frame .................................................................................... 1289
Figure 19-3. IrDA Data Modulation ....................................................................................... 1291
Figure 20-1. QSSI Module with Advanced, Bi-SSI and Quad-SSI Support .............................. 1351
Figure 20-2. TI Synchronous Serial Frame Format (Single Transfer) ...................................... 1358
Figure 20-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................... 1359
Figure 20-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ........................ 1360
Figure 20-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 ................ 1360
Figure 20-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ....................................... 1361
Figure 20-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............. 1362
Figure 20-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ...... 1362
Figure 20-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ....................................... 1363
Figure 21-1. I
2
C Block Diagram ........................................................................................... 1400
Figure 21-2. I
2
C Bus Configuration ....................................................................................... 1402
Figure 21-3. START and STOP Conditions ........................................................................... 1403
Figure 21-4. Complete Data Transfer with a 7-Bit Address ..................................................... 1403
Figure 21-5. R/S Bit in First Byte .......................................................................................... 1404
Figure 21-6. Data Validity During Bit Transfer on the I
2
C Bus ................................................. 1404
15June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C129ENCPDT Microcontroller