Datasheet

Register 7: I
2
C Master Masked Interrupt Status (I2CMMIS), offset 0x018
This register specifies whether an interrupt was signaled.
I2C Master Masked Interrupt Status (I2CMMIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
I2C 6 base: 0x400C.2000
I2C 7 base: 0x400C.3000
I2C 8 base: 0x400B.8000
I2C 9 base: 0x400B.9000
Offset 0x018
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MISCLKMIS
DMARXMISDMATXMIS
NACKMIS
STARTMIS
STOPMIS
ARBLOSTMIS
TXMISRXMISTXFEMISRXFFMISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:12
Receive FIFO Full Interrupt Mask
DescriptionValue
No interrupt.0
An unmasked Receive FIFO Full interrupt was signaled and is
pending.
1
This bit is cleared by writing a 1 to the RXFFIC bit in the I2CMICR
register.
0RORXFFMIS11
Transmit FIFO Empty Interrupt Mask
DescriptionValue
No interrupt.0
An unmasked Transmit FIFO Empty interrupt was signaled and
is pending.
1
This bit is cleared by writing a 1 to the TXFEIC bit in the I2CMICR
register.
0ROTXFEMIS10
1445June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C129ENCPDT Microcontroller