Datasheet

DescriptionResetTypeNameBit/Field
Receive FIFO Request Raw Interrupt Status
DescriptionValue
No interrupt0
The trigger level for the RX FIFO has been reached or there is
data in the FIFO and the burst count is zero. Thus, a RX FIFO
request interrupt is pending.
1
This bit is cleared by writing a 1 to the RXIC bit in the I2CMICR register.
0RORXRIS9
Transmit Request Raw Interrupt Status
DescriptionValue
No interrupt0
The trigger level for the TX FIFO has been reached and more
data is needed to complete the burst. Thus, a TX FIFO request
interrupt is pending.
1
This bit is cleared by writing a 1 to the TXIC bit in the I2CMICR register.
0ROTXRIS8
Arbitration Lost Raw Interrupt Status
DescriptionValue
No interrupt0
The Arbitration Lost interrupt is pending.1
This bit is cleared by writing a 1 to the ARBLOSTIC bit in the I2CMICR
register.
0ROARBLOSTRIS7
STOP Detection Raw Interrupt Status
DescriptionValue
No interrupt0
The STOP Detection interrupt is pending.1
This bit is cleared by writing a 1 to the STOPIC bit in the I2CMICR
register.
0ROSTOPRIS6
START Detection Raw Interrupt Status
DescriptionValue
No interrupt0
The START Detection interrupt is pending.1
This bit is cleared by writing a 1 to the STARTIC bit in the I2CMICR
register.
0ROSTARTRIS5
Address/Data NACK Raw Interrupt Status
DescriptionValue
No interrupt0
The address/data NACK interrupt is pending.1
This bit is cleared by writing a 1 to the NACKIC bit in the I2CMICR
register.
0RONACKRIS4
1443June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C129ENCPDT Microcontroller