Datasheet

DescriptionResetTypeNameBit/Field
Error
DescriptionValue
No error was detected on the last operation.0
An error occurred on the last operation.1
The error can be from the slave address not being acknowledged or the
transmit data not being acknowledged.
0ROERROR1
I
2
C Busy
DescriptionValue
The controller is idle.0
The controller is busy.1
When the BUSY bit is set, the other status bits are not valid.
0ROBUSY0
Write-Only Control Register
I2C Master Control/Status (I2CMCS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
I2C 6 base: 0x400C.2000
I2C 7 base: 0x400C.3000
I2C 8 base: 0x400B.8000
I2C 9 base: 0x400B.9000
Offset 0x004
Type WO, reset 0x0000.0020
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RUNSTARTSTOPACKHSQCMDBURSTreserved
WOWOWOWOWOWOWOROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:7
Burst Enable
DescriptionValue
Burst operation is disabled.0
The master is enabled to burst using the receive and transmit
FIFOs. See field decoding in Table 21-5 on page 1432.
1
Note that the BURST and RUN bits are mutually exclusive.
0WOBURST6
1429June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C129ENCPDT Microcontroller