Datasheet

Figure 10-4. GPIODATA Read Example ................................................................................. 757
Figure 11-1. EPI Block Diagram ............................................................................................. 825
Figure 11-2. SDRAM Non-Blocking Read Cycle ...................................................................... 832
Figure 11-3. SDRAM Normal Read Cycle ............................................................................... 833
Figure 11-4. SDRAM Write Cycle ........................................................................................... 834
Figure 11-5. iRDY Access Stalls, IRDYDLY==01, 10, 11 .......................................................... 844
Figure 11-6. iRDY Signal Connection ..................................................................................... 844
Figure 11-7. PSRAM Burst Read ........................................................................................... 847
Figure 11-8. PSRAM Burst Write ........................................................................................... 847
Figure 11-9. Read Delay During Refresh Event ...................................................................... 848
Figure 11-10. Write Delay During Refresh Event ....................................................................... 849
Figure 11-11. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 850
Figure 11-12. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 853
Figure 11-13. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 853
Figure 11-14. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH
= 0, RDHIGH = 0 ............................................................................................... 854
Figure 11-15. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual or
Quad CSn ......................................................................................................... 854
Figure 11-16. Continuous Read Mode Accesses ...................................................................... 854
Figure 11-17. Write Followed by Read to External FIFO ............................................................ 855
Figure 11-18. Two-Entry FIFO ................................................................................................. 855
Figure 11-19. Single-Cycle Single Write Access, FRM50=0, FRMCNT=0, WR2CYC=0 ............... 858
Figure 11-20. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, WR2CYC=1 ............... 859
Figure 11-21. Read Accesses, FRM50=0, FRMCNT=0 ............................................................. 859
Figure 11-22. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 860
Figure 11-23. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 860
Figure 11-24. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 860
Figure 11-25. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 860
Figure 11-26. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 861
Figure 11-27. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 861
Figure 11-28. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 861
Figure 11-29. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 862
Figure 13-1. AES Block Diagram ........................................................................................... 964
Figure 13-2. AES - ECB Feedback Mode ............................................................................... 968
Figure 13-3. AES - CBC Feedback Mode ............................................................................... 969
Figure 13-4. AES Encryption With CTR/ICM Mode .................................................................. 969
Figure 13-5. AES - CFB Feedback Mode ............................................................................... 970
Figure 13-6. AES - F8 Mode .................................................................................................. 971
Figure 13-7. AES - XTS Operation ......................................................................................... 971
Figure 13-8. AES - F9 Operation ........................................................................................... 972
Figure 13-9. AES - CBC-MAC Authentication Mode ................................................................ 973
Figure 13-10. AES - GCM Operation ........................................................................................ 974
Figure 13-11. AES - CCM Operation ........................................................................................ 975
Figure 13-12. AES Polling Mode .............................................................................................. 982
Figure 13-13. AES Interrupt Service ........................................................................................ 984
Figure 14-1. DES Block Diagram ......................................................................................... 1016
Figure 14-2. DES - ECB Feedback Mode ............................................................................. 1019
Figure 14-3. DES3DES - CBC Feedback Mode .................................................................... 1019
June 18, 201414
Texas Instruments-Production Data
Table of Contents