Datasheet
1. Enable the QSSI module using the RCGCSSI register (see page 397).
2. Enable the clock to the appropriate GPIO module via the RCGCGPIO register (see page 389).
To find out which GPIO port to enable, refer to Table 29-5 on page 1932.
3. Set the GPIO AFSEL bits for the appropriate pins (see page 778). To determine which GPIOs to
configure, see Table 29-4 on page 1921.
4. Configure the PMCn fields in the GPIOPCTL register to assign the QSSI signals to the appropriate
pins. See page 795 and Table 29-5 on page 1932.
5. Program the GPIODEN register to enable the pin's digital function. In addition, the drive strength,
drain select and pull-up/pull-down functions must be configured. Refer to “General-Purpose
Input/Outputs (GPIOs)” on page 750 for more information.
Note: Pull-ups can be used to avoid unnecessary toggles on the QSSI pins, which can take
the slave to a wrong state. In addition, if the SSIClk signal is programmed to steady
state High through the SPO bit in the SSICR0 register, then software must also configure
the GPIO port pin corresponding to the SSInClk signal as a pull-up in the GPIO Pull-Up
Select (GPIOPUR) register.
For each of the frame formats, the QSSI is configured using the following steps:
1. If initializing out of reset, ensure that the SSE bit in the SSICR1 register is clear before making
any configuration changes. Otherwise, configuration changes for Advanced SSI can be made
while the SSE bit is set.
2. Select whether the QSSI is a master or slave:
a. For master operations, set the SSICR1 register to 0x0000.0000.
b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.
c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.
3. Configure the QSSI clock source by writing to the SSICC register.
4. Configure the clock prescale divisor by writing the SSICPSR register.
5. Write the SSICR0 register with the following configuration:
■ Serial clock rate (SCR)
■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
■ The protocol mode: Freescale SPI or TI SSF
■ The data size (DSS)
6. Optionally, configure the SSI module for μDMA use with the following steps:
a. Configure a μDMA for SSI use. See “Micro Direct Memory Access (μDMA)” on page 686 for
more information.
b. Enable the SSI Module's TX FIFO or RX FIFO by setting the TXDMAE or RXDMAE bit in the
SSIDMACTL register.
1365June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C129ENCPDT Microcontroller