Datasheet

DescriptionResetTypeNameBit/Field
UART Break Error
DescriptionValue
No break condition has occurred0
A break condition has been detected, indicating that the receive
data input was held Low for longer than a full-word transmission
time (defined as start, data, parity, and stop bits).
1
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive data input
goes to a 1 (marking state) and the next valid start bit is received.
0ROBE2
UART Parity Error
DescriptionValue
No parity error has occurred0
The parity of the received data character does not match the
parity defined by bits 2 and 7 of the UARTLCRH register.
1
This bit is cleared to 0 by a write to UARTECR.
0ROPE1
UART Framing Error
DescriptionValue
No framing error has occurred0
The received character does not have a valid stop bit (a valid
stop bit is 1).
1
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
0ROFE0
Write-Only Error Clear Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x004
Type WO, reset 0x0000.0000
16171819202122232425262728293031
reserved
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
0000000000000000Reset
0123456789101112131415
DATAreserved
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
0000000000000000Reset
June 18, 20141302
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)