Datasheet

List of Figures
Figure 1-1. Tiva
™
TM4C129ENCPDT Microcontroller High-Level Block Diagram ...................... 58
Figure 2-1. CPU Block Diagram ............................................................................................. 88
Figure 2-2. TPIU Block Diagram ............................................................................................ 89
Figure 2-3. Cortex-M4F Register Set ...................................................................................... 92
Figure 2-4. Bit-Band Mapping .............................................................................................. 117
Figure 2-5. Data Storage ..................................................................................................... 118
Figure 2-6. Vector Table ...................................................................................................... 126
Figure 2-7. Exception Stack Frame ...................................................................................... 129
Figure 3-1. SRD Use Example ............................................................................................. 147
Figure 3-2. FPU Register Bank ............................................................................................ 150
Figure 4-1. JTAG Module Block Diagram .............................................................................. 215
Figure 4-2. Test Access Port State Machine ......................................................................... 219
Figure 4-3. IDCODE Register Format ................................................................................... 225
Figure 4-4. BYPASS Register Format ................................................................................... 225
Figure 4-5. Boundary Scan Register Format ......................................................................... 225
Figure 5-1. Basic RST Configuration .................................................................................... 231
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 231
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 231
Figure 5-4. Power Architecture ............................................................................................ 236
Figure 5-5. Main Clock Tree ................................................................................................ 240
Figure 5-6. Module Clock Selection ...................................................................................... 249
Figure 7-1. Hibernation Module Block Diagram ..................................................................... 541
Figure 7-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 545
Figure 7-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 545
Figure 7-4. Using a Regulator for Both V
DD
and V
BAT
............................................................ 546
Figure 7-5. Counter Behavior with a TRIM Value of 0x8002 ................................................... 550
Figure 7-6. Counter Behavior with a TRIM Value of 0x7FFC .................................................. 550
Figure 7-7. Tamper Block Diagram ....................................................................................... 550
Figure 7-8. Tamper Pad with Glitch Filtering ......................................................................... 551
Figure 8-1. Internal Memory Block Diagram .......................................................................... 609
Figure 8-2. Flash Memory Configuration ............................................................................... 613
Figure 8-3. Single 256-Bit Prefetch Buffer Set ....................................................................... 614
Figure 8-4. Four 256-Bit Prefetch Buffer Configuration .......................................................... 614
Figure 8-5. Single Cycle Access, 0 Wait States ..................................................................... 615
Figure 8-6. Prefetch Fills from Flash ..................................................................................... 616
Figure 8-7. Mirror Mode Function ......................................................................................... 617
Figure 9-1. μDMA Block Diagram ......................................................................................... 687
Figure 9-2. Example of Ping-Pong μDMA Transaction ........................................................... 694
Figure 9-3. Memory Scatter-Gather, Setup and Configuration ................................................ 696
Figure 9-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 697
Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 699
Figure 9-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 700
Figure 10-1. Digital I/O Pads ................................................................................................. 755
Figure 10-2. Analog/Digital I/O Pads ...................................................................................... 756
Figure 10-3. GPIODATA Write Example ................................................................................. 757
13June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C129ENCPDT Microcontroller