Datasheet

Table 2-9. Interrupts (continued)
DescriptionVector Address or
Offset
Interrupt Number (Bit
in Interrupt Registers)
Vector Number
I
2
C 90x0000.01F8110126
Reserved-111-113127-129
2.5.3 Exception Handlers
The processor handles exceptions using:
■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs.
■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault
exceptions handled by the fault handlers.
■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system
exceptions that are handled by system handlers.
2.5.4 Vector Table
The vector table contains the reset value of the stack pointer and the start addresses, also called
exception vectors, for all exception handlers. The vector table is constructed using the vector address
or offset shown in Table 2-8 on page 121. Figure 2-6 on page 126 shows the order of the exception
vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the
exception handler is Thumb code
125June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C129ENCPDT Microcontroller