Datasheet

ADC Sample Phase Control (ADCSPC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x024
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PHASEreserved
RWRWRWRWROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:4
Phase Lag
This field selects the sample phase lag from the standard sample time.
DescriptionValue
The ADC samples are concurrent.0x0
The ADC sample lags by 1 ADC clock0x1
The ADC sample lags by 2 ADC clocks0x2
The ADC sample lags by 3 ADC clocks0x3
The ADC sample lags by 4 clocks0x4
The ADC sample lags by 5 clocks0x5
The ADC sample lags by 6 clocks0x6
The ADC sample lags by 7 clocks0x7
The ADC sample lags by 8 clocks0x8
The ADC sample lags by 9 clocks0x9
The ADC sample lags by 10 clocks0xA
The ADC sample lags by 11 clocks0xB
The ADC sample lags by 12 clocks0xC
The ADC sample lags by 13 clocks0xD
The ADC sample lags by 14 clocks0xE
The ADC sample lags by 15 clocks0xF
0x0RWPHASE3:0
June 18, 20141226
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)