Datasheet

DescriptionResetTypeNameBit/Field
GPTM Timer A Match Interrupt Enable
DescriptionValue
The match interrupt is disabled for match events.0
Note: Clearing the TAMIE bit in the GPTMTAMR register
prevents assertion of µDMA or ADC requests
generated on a match event. Even if the TATODMAEN
bit is set in the GPTMDMAEV register or the
TATOADCEN bit is set in the GPTMADCEV register,
a µDMA or ADC match trigger is not sent to the µDMA
or ADC, respectively, when the TAMIE bit is clear.
An interrupt is generated when the match value in the
GPTMTAMATCHR register is reached in the one-shot and
periodic modes.
1
0RWTAMIE5
GPTM Timer A Count Direction
DescriptionValue
The timer counts down.0
The timer counts up. When counting up, the timer starts from a
value of 0x0.
1
When in PWM or RTC mode, the status of this bit is ignored. PWM mode
always counts down and RTC mode always counts up.
0RWTACDIR4
GPTM Timer A Alternate Mode Select
The TAAMS values are defined as follows:
DescriptionValue
Capture or compare mode is enabled.0
PWM mode is enabled.1
Note: To enable PWM mode, you must also clear the TACMR
bit and configure the TAMR field to 0x1 or 0x2.
0RWTAAMS3
GPTM Timer A Capture Mode
The TACMR values are defined as follows:
DescriptionValue
Edge-Count mode0
Edge-Time mode1
0RWTACMR2
June 18, 20141104
Texas Instruments-Production Data
General-Purpose Timers