Datasheet

Register 41: SHA DMA Interrupt Mask (SHA_DMAIM), offset 0x010
The SHA DMA Interrupt Mask (SHA_DMA_IM) register controls interrupt behavior and are used
to program which interrupts are suppressed.
SHA DMA Interrupt Mask (SHA_DMAIM)
Base
Offset 0x010
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CINDINCOUTreserved
RWRWRWROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:3
Context Out DMA Done Interrupt Mask
If this bit is unmasked, an interrupt is generated when the µDMA
completes the output context read from the internal register.
DescriptionValue
The COUT interrupt is suppressed and not sent to the interrupt
controller.
0
The COUT interrupt is sent to the interrupt controller.1
0RWCOUT2
Data In DMA Done Interrupt Mask
If this bit is unmasked, an interrupt is generated when the µDMA writes
the last word of input data to the internal FIFO of the engine.
DescriptionValue
The DIN interrupt is suppressed and not sent to the interrupt
controller.
0
The DIN interrupt is sent to the interrupt controller.1
0RWDIN1
Context In DMA Done Interrupt Mask
If this bit is unmasked, an interrupt is generated when the µDMA
completes a context write to the internal register.
DescriptionValue
The CIN interrupt is suppressed and not sent to the interrupt
controller.
0
The CIN interrupt is sent to the interrupt controller.1
0RWCIN0
1075June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C129ENCPDT Microcontroller