Datasheet

15.4 SHA/MD5 µDMA Control Register Descriptions (Encryption Control
Offset)
This section lists and describes the SHA/MD5 µDMA registers, in numerical order by address offset.
Registers in this section are relative to the Encryption Control base address of 0x4403.0000.
Note: The SHA module can only be accessed through privileged mode. If the µDMA is used for
SHA transfers, then the µDMA's DMA Channel Control (DMACHCTL) register also needs
to be programmed to allow for privileged accesses.
Note: If the application uses SHA µDMA interrupt triggers, the bits in the SHA_IRQENABLE
register should be cleared.
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SHA/MD5 Accelerator