Datasheet

Register 22: Floating-Point Status Control (FPSC)
The FPSC register provides all necessary user-level control of the floating-point system.
Floating-Point Status Control (FPSC)
Type RW, reset -
16171819202122232425262728293031
reservedRMODEFZDNAHPreservedVCZN
RORORORORORORWRWRWRWRWRORWRWRWRWType
000000-----0----Reset
0123456789101112131415
IOCDZCOFCUFCIXCreservedIDCreserved
RWRWRWRWRWRORORWROROROROROROROROType
-----00-00000000Reset
DescriptionResetTypeNameBit/Field
Negative Condition Code Flag
Floating-point comparison operations update this condition code flag.
-RWN31
Zero Condition Code Flag
Floating-point comparison operations update this condition code flag.
-RWZ30
Carry Condition Code Flag
Floating-point comparison operations update this condition code flag.
-RWC29
Overflow Condition Code Flag
Floating-point comparison operations update this condition code flag.
-RWV28
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved27
Alternative Half-Precision
When set, alternative half-precision format is selected. When clear,
IEEE half-precision format is selected.
The AHP bit in the FPDSC register holds the default value for this bit.
-RWAHP26
Default NaN Mode
When set, any operation involving one or more NaNs returns the Default
NaN. When clear, NaN operands propagate through to the output of a
floating-point operation.
The DN bit in the FPDSC register holds the default value for this bit.
-RWDN25
Flush-to-Zero Mode
When set, Flush-to-Zero mode is enabled. When clear, Flush-to-Zero
mode is disabled and the behavior of the floating-point system is fully
compliant with the IEEE 754 standard.
The FZ bit in the FPDSC register holds the default value for this bit.
-RWFZ24
107June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C129ENCPDT Microcontroller