Datasheet

Register 18: SHA Mode (SHA_MODE), offset 0x044
This register is written to configure the hash algorithm to be used in the hash operation.
SHA Mode (SHA_MODE)
Base 0x4403.4000
Offset 0x044
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ALGO
ALGO_CONSTANT
CLOSE_HASH
HMAC_KEY_PROC
reserved
HMAC_OUTER_HASH
reserved
RWRWRWRWRWRWRRWROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:8
HMAC Outer Hash Processing Enable
This bit is written to indicate that the outer hash should be performed
on the hash digest when the inner hash has finished. The inner hash
finishes when the length of hash has been processed the final inner
hash is performed (if CLOSE_HASH was set to 1).
This bit should normally be set together with CLOSE_HASH to finish the
inner hash first, or immediately when block length is zero (HMAC
continue with the just outer hash to be done). This bit is auto-cleared
when outer hash is finished.
DescriptionValue
No operation0
Enable HMAC processing of outer hash.
This bit self-clears when outer hash is finished.
1
0RWHMAC_OUTER_HASH7
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0Rreserved6
June 18, 20141064
Texas Instruments-Production Data
SHA/MD5 Accelerator