Datasheet

data to process. Data must be written to the 16 x 32-bit SHA_DATA_n_IN registers that provide
storage for one 64-byte block of data. Unless the CLOSE_HASH bit is set, all of the SHA_DATA_n_IN
input buffers must be filled. Data can be written by single write accesses to the 16 registers from a
processor or by a DMA transfer.
For µDMA transfers, the DMA_EN bit must be set in the SHA_SYSCONFIG register and the
appropriate mask bits must be set in the SHA_DMAIM register before starting the new hash. Note
that if the µDMA is used for transfers, the SHA_IRQENABLE register should be clear so all interrupts
are generated through the µDMA interrupt registers.
The µDMA must be configured to transfer 16 data words of 32 bits each time it is triggered by a
µDMA request from the SHA/MD5 Module. The 16 data words written are sent to the 16
SHA_DATA_n_IN registers.
The module detects that a 64-byte block is available, and then moves the data to a working register
space for processing and asserts the INPUT_READY bit in the SHA_IRQSTATUS register to 1. If
the DMA_EN bit in the SHA_SYSCONFIG register has been set to 1, a new µDMA request triggers
a new block transfer; otherwise, the processor polls the INPUT_READY bit and writes the 16 data
words of 32 bits when it equals 1.
This operation is repeated until the length of the message to hash is reached. The OUPUT_READY
bit in the SHA_IRQSTATUS register then indicates that the hash operation is complete. If the IT_EN
bit in the SHA_SYSCONFIG register is set, an interrupt (active low) is also generated to indicate
the hash completion.
The processor can then read the eight digest registers A through H that contain the hash and/or
HMAC result. If the hash is an intermediate result of a larger hash, the digest count register must
also be read and saved.
Note: The number of digest registers used depends on the algorithm selected for the SHA/MD5
Module (MD5, SHA-1, SHA-224, or SHA-256), as shown in Table 15-3 on page 1048 and
Table 15-4 on page 1049
Table 15-3. Outer Digest Registers
HMAC Key
Processing (write)
SHA-2 (Read/Write)SHA-1
(Read/Write)
MD5
(Read/Write)
AddressRegister
HMAC Key [31:0]Outer digest [255:224]Outer digest
[159:128]
Outer digest
[127:96]
0x000SHA_ODIGEST_A
HMAC key [63:32]Outer digest [223:192]Outer digest
[127:96]
Outer digest
[95:64]
0x004SHA_ODIGEST_B
HMAC key [95:64]Outer digest [191:160]Outer digest
[95:64]
Outer digest
[63:32]
0x008SHA_ODIGEST_C
HMAC key [127:96]Outer digest [159:128]Outer digest
[63:32]
Outer digest
[31:0]
0x00CSHA_ODIGEST_D
HMAC key [159:128]Outer digest [127:96]Outer digest [31:0]0x010SHA_ODIGEST_E
HMAC key [191:160]Outer digest [95:64]0x014SHA_ODIGEST_F
HMAC key [223:192]Outer digest [63:32]0x018SHA_ODIGEST_G
HMAC key [255:224]Outer digest [31:0]0x01CSHA_ODIGEST_H
June 18, 20141048
Texas Instruments-Production Data
SHA/MD5 Accelerator