Datasheet
when context out, context in, data in or data out is ready. The SHA Interrupt Status
(SHA_IRQSTATUS), offset 0x118, indicates when an interrupt is triggered.
Note: If the application uses Interrupt Mode, an interrupt is generated for each block of processed
data. To support larger data flow, SHA µDMA Mode should be used and the bits in the
SHA_IRQENABLE register should be cleared.
Table 15-1. Interrupts and Events
DescriptionEvent
Context output interruptSHA_IRQSTATUS[3]: CONTEXT_OUT
Data input interruptSHA_IRQSTATUS[1]: DATA_IN
Context input interruptSHA_IRQSTATUS[0]: CONTEXT_IN
15.1.5 Operation Description
The SHA/MD5 Module can run the SHA-1, SHA-224, SHA-256, and MD5 algorithms, depending
on the value of the ALGO bit field in the SHA Mode (SHA_MODE) register, offset 0x044, as listed
in Table 15-2 on page 1047.
Table 15-2. SHA/MD5 Module Algorithm Selection
DescriptionALGO Field Value in SHA_MODE Register
MD5 algorithm selected0x0
SHA-1 algorithm selected0x1
SHA-224 algorithm selected0x2
SHA-256 algorithm selected0x3
15.1.5.1 SHA Mode
Starting a New Hash
To start a new hash, follow these steps:
1. Set the ALGO bitfield in the SHA_MODE register, at offset 0x044, to 0x1, 0x2, or 0x3 to select
SHA-1, SHA-224, or SHA-256, respectively.
2. Set the ALGO_CONSTANT bit in the SHA_MODE register to 1 to initialize all SHA Inner/Outer
Digest n registers from SHA_ODIGEST_A/SHA_IDIGEST_A to
SHA_ODIGEST_H/SHA_IDIGEST_H with their default values specified by the algorithm, and
set the SHA_DIGESTCOUNT register to 0.
3. Set the CLOSE_HASH bit of the SHA Mode (SHA_MODE) register to let the SHA engine do the
padding. If the Hash is computed in one shot, the length of the message can be any value up
to 128 MB. To process an intermediate Hash digest, the CLOSE_HASH bit is set to 0, in which
case the packets hashed must be 64 bytes; the last packet must be hashed with the CLOSE_HASH
bit set to 1.
4. Specify the LENGTH field in the SHA Length (SHA_LENGTH) register of the hash data to
process in bytes.
After the configuration is complete, the INPUT_READY status bit equals 1 in the SHA Interrupt
Status (SHA_IRQSTATUS) register (regardless of whether or not the M_INPUT_READY bit in the
SHA_IRQENABLE register is set. When this bit is set, it indicates the SHA engine can receive the
1047June 18, 2014
Texas Instruments-Production Data
Tiva
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TM4C129ENCPDT Microcontroller