Datasheet

Register 17: DES Interrupt Enable (DES_IRQENABLE), offset 0x040
This register contains an enable bit for each unique interrupt generated by the module. It matches
the layout of DES_IRQSTATUS register. An interrupt is enabled when the bit in this register is set
to 1.
DES Interrupt Enable (DES_IRQENABLE)
Base 0x4403.8000
Offset 0x040
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
M_CONTEX_IN
M_DATA_INM_DATA_OUT
reserved
RWRWRWROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.0000ROreserved31:3
If this bit is set to 1 the data output interrupt is enabled.0RWM_DATA_OUT2
If this bit is set to 1 the data input interrupt is enabled.0RWM_DATA_IN1
If this bit is set to 1 the context interrupt is enabled.0RWM_CONTEX_IN0
June 18, 20141038
Texas Instruments-Production Data
Data Encryption Standard Accelerator (DES)