Datasheet

This register indicates the interrupt status. If one of the interrupt bits is set the interrupt output will

be asserted.

DES Interrupt Status (DES_IRQSTATUS)

Base 0x4403.8000

Offset 0x03C

Type RO, reset 0x0000.0000

16171819202122232425262728293031

reserved

ROROROROROROROROROROROROROROROROType

0000000000000000Reset

0123456789101112131415

CONTEX_IN

DATA_IN

DATA_OUT

reserved

ROROROROROROROROROROROROROROROROType

0000000000000000Reset

DescriptionResetTypeNameBit/Field

Software should not rely on the value of a reserved bit. To provide

compatibility with future products, the value of a reserved bit should be

preserved across a read-modify-write operation.

0x0000.0000ROreserved31:3

This bit indicates data output interrupt is active and triggers the interrupt

output.

0RODATA_OUT2

This bit indicates data input interrupt is active and triggers the interrupt

output.

0RODATA_IN1

This bit indicates context interrupt is active and triggers the interrupt

output.

0ROCONTEX_IN0

1037June 18, 2014

Texas Instruments-Production Data

Tiva

™

TM4C129ENCPDT Microcontroller