Datasheet

of a 3x reduction in throughput. The DES buffered engine implements a 3DES logic wrapper around
the 2-round DES core, enabling seamless 3DES encryption.
14.2.4.3 DES Cipher Core
The DES cipher core implements the DES algorithm as specified in the FIPS 46-3. The core operates
on the input block and performs the required substitution, shift, and mix operations. The core also
applies the correct key-scheduling.
Inherently, considerable parallelism is possible with the DES algorithm. This is exploited in two
ways. For high performance, the 64 bits composing the data block are processed concurrently
(4-round implementation). For low gate-count, resources are shared on both the main data and key
paths (1-round implementation).
A fundamental component of the DES algorithm is the substitution box (S-Box). The S-Box provides
a unique 4-bit output for each 6-bit input. The S-Box design is a primary factor for both performance
and gate count. The DES Cipher Core has a standard lookup table S-Box that allows room for the
synthesizer to optimize on timing or gate count.
14.3 Software Reset
Table 14-2 on page 1018 lists the resets used in the DES module.
Table 14-2. DES Reset Description
DescriptionSourceNameType
Global resetPRCMDES_RSTHardware
Starts the soft reset sequence. When the
DES_SYSSTATUS/DES_P_SYSSTATUS[0]
RESETDONE bit goes to 1, the soft reset sequence
is finished.
InternalDES_SYSCONFIG [1]
SOFTRESET
Software
14.4 DES Supported Modes of Operation
14.4.1 ECB Feedback Mode
Figure 14-2 on page 1019 shows the basic ECB feedback mode of operation, where the input data is
passed directly to the basic cryptographic core and the output of the cryptographic core is passed
directly to the output buffer. For decryption the DES core operates in reverse, this means the decrypt
key sequence is used for the data processing, where encryption uses the encrypt key sequence.
June 18, 20141018
Texas Instruments-Production Data
Data Encryption Standard Accelerator (DES)