Datasheet

Register 42: AES DMA Interrupt Clear (AES_DMAIC), offset 0x02C
The AES DMA Interrupt Clear (AES_DMAIC) register is used to clear the AES_DMARIS and
AES_DMAMIS registers by writing a 1 to each register bit.
Note: This registers always reads as zero.
AES DMA Interrupt Clear (AES_DMAIC)
Base 0x4403.0000
Offset 0x02C
Type W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CINCOUTDINDOUTreserved
W1CW1CW1CW1CROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:4
Data Out DMA Done Interrupt Clear
Writing a 1 to this bit clears the DOUT bit in the AES_DMARIS and
AES_DMAMIS register.
0W1CDOUT3
Data In DMA Done Interrupt Clear
Writing a 1 to this bit clears the DIN bit in the AES_DMARIS and
AES_DMAMIS register.
0W1CDIN2
Context Out DMA Done Masked Interrupt Status
Writing a 1 to this bit clears the COUT bit in the AES_DMARIS and
AES_DMAMIS register.
0W1CCOUT1
Context In DMA Done Raw Interrupt Status
Writing a 1 to this bit clears the CIN bit in the AES_DMARIS and
AES_DMAMIS register.
0W1CCIN0
June 18, 20141014
Texas Instruments-Production Data
Advance Encryption Standard Accelerator (AES)