Datasheet

Register 41: AES DMA Masked Interrupt Status (AES_DMAMIS), offset 0x028
The AES DMA Masked Interrupt Status (AES_DMAMIS) register displays the raw interrupts that
are unmasked in the AES DMA Raw Interrupt Status (AES_DMARIS) register.
AES DMA Masked Interrupt Status (AES_DMAMIS)
Base 0x4403.0000
Offset 0x028
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CINCOUTDINDOUTreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:4
Data Out DMA Done Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
A DOUT interrupt has occurred.1
0RODOUT3
Data In DMA Done Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
A DIN interrupt has occurred.1
0RODIN2
Context Out DMA Done Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
A COUT interrupt has occurred.1
0ROCOUT1
Context In DMA Done Raw Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
A CIN interrupt has occurred.1
0ROCIN0
1013June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C129ENCPDT Microcontroller