Datasheet

21.4 Initialization and Configuration .................................................................................... 1421
21.4.1 Configure the I
2
C Module to Transmit a Single Byte as a Master .................................. 1421
21.4.2 Configure the I
2
C Master to High Speed Mode ............................................................ 1422
21.5 Register Map ............................................................................................................ 1423
21.6 Register Descriptions (I
2
C Master) .............................................................................. 1425
21.7 Register Descriptions (I
2
C Slave) ............................................................................... 1454
21.8 Register Descriptions (I
2
C Status and Control) ............................................................ 1471
22 Controller Area Network (CAN) Module ........................................................... 1480
22.1 Block Diagram ........................................................................................................... 1481
22.2 Signal Description ..................................................................................................... 1481
22.3 Functional Description ............................................................................................... 1482
22.3.1 Initialization ............................................................................................................... 1483
22.3.2 Operation .................................................................................................................. 1483
22.3.3 Transmitting Message Objects ................................................................................... 1484
22.3.4 Configuring a Transmit Message Object ...................................................................... 1485
22.3.5 Updating a Transmit Message Object ......................................................................... 1486
22.3.6 Accepting Received Message Objects ........................................................................ 1486
22.3.7 Receiving a Data Frame ............................................................................................ 1487
22.3.8 Receiving a Remote Frame ........................................................................................ 1487
22.3.9 Receive/Transmit Priority ........................................................................................... 1487
22.3.10 Configuring a Receive Message Object ...................................................................... 1488
22.3.11 Handling of Received Message Objects ...................................................................... 1489
22.3.12 Handling of Interrupts ................................................................................................ 1491
22.3.13 Test Mode ................................................................................................................. 1492
22.3.14 Bit Timing Configuration Error Considerations ............................................................. 1494
22.3.15 Bit Time and Bit Rate ................................................................................................. 1494
22.3.16 Calculating the Bit Timing Parameters ........................................................................ 1496
22.4 Register Map ............................................................................................................ 1499
22.5 CAN Register Descriptions ......................................................................................... 1500
23 Ethernet Controller ............................................................................................ 1531
23.1 Block Diagram ........................................................................................................... 1532
23.2 Signal Description ..................................................................................................... 1532
23.3 Functional Description ............................................................................................... 1533
23.3.1 Ethernet Clock Control ............................................................................................... 1533
23.3.2 DMA Controller ......................................................................................................... 1534
23.3.3 TX/RX Controller ....................................................................................................... 1558
23.3.4 MAC Operation ......................................................................................................... 1562
23.3.5 IEEE 1588 and Advanced Timestamp Function ........................................................... 1564
23.3.6 Frame Filtering .......................................................................................................... 1573
23.3.7 Source Address, VLAN, and CRC Insertion, Replacement or Deletion .......................... 1574
23.3.8 Checksum Offload Engine .......................................................................................... 1576
23.3.9 MAC Management Counters ...................................................................................... 1577
23.3.10 Power Management Module ....................................................................................... 1578
23.3.11 Serial Management Interface ..................................................................................... 1581
23.3.12 Interrupt Configuration ............................................................................................... 1581
23.4 Ethernet PHY ............................................................................................................ 1581
23.4.1 Integrated PHY Block Diagram ................................................................................... 1581
23.4.2 Functional Description ............................................................................................... 1582
June 18, 201410
Texas Instruments-Production Data
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