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Tiva

™

TM4C129ENCPDT Microcontroller

DATA SHEET

Texas Instruments Incorporated

DS-TM4C129ENCPDT-15863.2743

SPMS441B

TEXAS INSTRUMENTS-PRODUCTION DATA

Summary of content (2046 pages)

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TE X AS I NS TRUM E NTS - P RO DUCTION D ATA Tiva™ TM4C129ENCPDT Microcontroller D ATA SHE E T D S -T M 4C 129ENCP DT - 1 5 8 6 3 .
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Copyright Copyright © 2007-2014 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. All other trademarks are the property of others. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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Tiva™ TM4C129ENCPDT Microcontroller Table of Contents Revision History ............................................................................................................................. 49 About This Document .................................................................................................................... 52 Audience .............................................................................................................................................. About This Manual .
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Table of Contents 2.4.5 2.4.6 2.4.7 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 2.5.7 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.7 2.7.1 2.7.2 2.8 Bit-Banding ................................................................................................................. Data Storage .............................................................................................................. Synchronization Primitives ...........................................................................................
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Tiva™ TM4C129ENCPDT Microcontroller 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.3 5.4 5.5 5.6 Device Identification .................................................................................................... Reset Control .............................................................................................................. Non-Maskable Interrupt ............................................................................................... Power Control .........................................
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Table of Contents 8.3 8.4 8.5 8.6 Register Map .............................................................................................................. 629 Internal Memory Register Descriptions (Internal Memory Control Offset) ......................... 632 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 658 Memory Register Descriptions (System Control Offset) ..................................................
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Tiva™ TM4C129ENCPDT Microcontroller 11.4.2 11.4.3 11.4.4 11.5 11.6 SDRAM Mode ............................................................................................................. Host Bus Mode ........................................................................................................... General-Purpose Mode ............................................................................................... Register Map ......................................................................
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Table of Contents 15.1.2 15.1.3 15.1.4 15.1.5 15.1.6 15.1.7 15.2 15.3 15.4 Power Management .................................................................................................. 1046 Reset Management ................................................................................................... 1046 µDMA and Interrupt Requests .................................................................................... 1046 Operation Description ....................................................
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Tiva™ TM4C129ENCPDT Microcontroller 18.4.1 18.4.2 18.5 18.6 Module Initialization ................................................................................................... Sample Sequencer Configuration ............................................................................... Register Map ............................................................................................................ Register Descriptions .........................................................................
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Table of Contents 21.4 21.4.1 21.4.2 21.5 21.6 21.7 21.8 Initialization and Configuration .................................................................................... Configure the I2C Module to Transmit a Single Byte as a Master .................................. Configure the I2C Master to High Speed Mode ............................................................ Register Map ............................................................................................................
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Tiva™ TM4C129ENCPDT Microcontroller 23.4.3 23.5 23.5.1 23.6 23.7 23.8 Interface Configuration ............................................................................................... Initialization and Configuration .................................................................................... Ethernet PHY Initialization .......................................................................................... Register Map ......................................................................
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Table of Contents 29.5 29.6 Possible Pin Assignments for Alternate Functions ....................................................... 1935 Connections for Unused Signals ................................................................................. 1940 30 Electrical Characteristics .................................................................................. 1942 30.1 Maximum Ratings ...................................................................................................... 1942 30.
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Tiva™ TM4C129ENCPDT Microcontroller List of Figures Figure 1-1. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 3-1. Figure 3-2. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 5-6. Figure 7-1. Figure 7-2. Figure 7-3. Figure 7-4. Figure 7-5. Figure 7-6. Figure 7-7. Figure 7-8. Figure 8-1. Figure 8-2. Figure 8-3. Figure 8-4. Figure 8-5. Figure 8-6. Figure 8-7. Figure 9-1. Figure 9-2.
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Table of Contents Figure 10-4. Figure 11-1. Figure 11-2. Figure 11-3. Figure 11-4. Figure 11-5. Figure 11-6. Figure 11-7. Figure 11-8. Figure 11-9. Figure 11-10. Figure 11-11. Figure 11-12. Figure 11-13. Figure 11-14. Figure 11-15. Figure 11-16. Figure 11-17. Figure 11-18. Figure 11-19. Figure 11-20. Figure 11-21. Figure 11-22. Figure 11-23. Figure 11-24. Figure 11-25. Figure 11-26. Figure 11-27. Figure 11-28. Figure 11-29. Figure 13-1. Figure 13-2. Figure 13-3. Figure 13-4. Figure 13-5. Figure 13-6.
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Tiva™ TM4C129ENCPDT Microcontroller Figure 14-4. Figure 14-5. Figure 14-6. Figure 14-7. Figure 15-1. Figure 15-2. Figure 15-3. Figure 16-1. Figure 16-2. Figure 16-3. Figure 16-4. Figure 16-5. Figure 16-6. Figure 16-7. Figure 16-8. Figure 17-1. Figure 18-1. Figure 18-2. Figure 18-3. Figure 18-4. Figure 18-5. Figure 18-6. Figure 18-7. Figure 18-8. Figure 18-9. Figure 18-10. Figure 18-11. Figure 18-12. Figure 18-13. Figure 18-14. Figure 19-1. Figure 19-2. Figure 19-3. Figure 20-1. Figure 20-2. Figure 20-3.
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Table of Contents Figure 21-7. Figure 21-8. Figure 21-9. Figure 21-10. Figure 21-11. Figure 21-12. Figure 21-13. Figure 21-14. Figure 21-15. Figure 22-1. Figure 22-2. Figure 22-3. Figure 22-4. Figure 23-1. Figure 23-2. Figure 23-3. Figure 23-4. Figure 23-5. Figure 23-6. Figure 23-7. Figure 23-8. Figure 23-9. Figure 23-10. High-Speed Data Format .................................................................................. 1410 Master Single TRANSMIT ....................................................
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Tiva™ TM4C129ENCPDT Microcontroller Figure 30-8. Figure 30-9. Figure 30-10. Figure 30-11. Figure 30-12. Figure 30-13. Figure 30-14. Figure 30-15. Figure 30-16. Figure 30-17. Figure 30-18. Figure 30-19. Figure 30-20. Figure 30-21. Figure 30-22. Figure 30-23. Figure 30-24. Figure 30-25. Figure 30-26. Figure 30-27. Figure 30-28. Figure 30-29. Figure 30-30. Figure 30-31. Figure 30-32. Figure 30-33. Figure 30-34. Figure 30-35. Figure 30-36. Figure 30-37. Figure 30-38. Figure 30-39. Figure 30-40. Figure 30-41.
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Table of Contents List of Tables Table 1. Table 2. Table 1-1. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 2-10. Table 2-11. Table 2-12. Table 2-13. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 3-10. Table 4-1. Table 4-2. Table 4-3. Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 5-8. Table 5-9. Table 5-10. Table 5-11. Table 5-12. Table 5-13. Table 5-14.
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Tiva™ TM4C129ENCPDT Microcontroller Table 5-18. Table 5-19. Table 5-20. Table 5-21. Table 5-22. Table 5-23. Table 5-24. Table 5-25. Table 5-26. Table 5-27. Table 5-28. Table 5-29. Table 5-30. Table 5-31. Table 5-32. Table 5-33. Table 5-34. Table 6-1. Table 7-1. Table 7-2. Table 7-3. Table 8-1. Table 8-2. Table 8-3. Table 8-4. Table 8-5. Table 8-6. Table 9-1. Table 9-2. Table 9-3. Table 9-4. Table 9-5. Table 9-6. Table 9-7. Table 9-8. Table 9-9. Table 9-10. Table 9-11. Table 9-12. Table 9-13. Table 10-1.
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Table of Contents Table 10-8. Table 10-9. Table 10-10. Table 10-11. Table 10-12. Table 10-13. Table 11-1. Table 11-2. Table 11-3. Table 11-4. Table 11-5. Table 11-6. Table 11-7. Table 11-8. Table 11-9. Table 11-10. Table 11-11. Table 11-12. Table 11-13. Table 11-14. Table 11-15. Table 12-1. Table 12-2. Table 12-3. Table 13-1. Table 13-2. Table 13-3. Table 13-4. Table 13-5. Table 13-6. Table 14-1. Table 14-2. Table 14-3. Table 14-4. Table 14-5. Table 14-6. Table 14-7. Table 14-8. Table 14-9. Table 15-1.
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Tiva™ TM4C129ENCPDT Microcontroller Table 15-10. Table 15-11. Table 15-12. Table 15-13. Table 16-1. Table 16-2. Table 16-3. Table 16-4. Table 16-5. Table 16-6. Table 16-7. Table 16-8. Table 16-9. Table 16-10. Table 16-11. Table 17-1. Table 18-1. Table 18-2. Table 18-3. Table 18-4. Table 18-5. Table 18-6. Table 18-7. Table 18-8. Table 18-9. Table 18-10. Table 19-1. Table 19-2. Table 19-3. Table 20-1. Table 20-2. Table 20-3. Table 20-4. Table 20-5. Table 21-1. Table 21-2. Table 21-3. Table 21-4. Table 21-5.
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Table of Contents Table 23-5. Table 23-6. Table 23-7. Table 23-8. Table 23-9. Table 23-10. Table 23-11. Table 23-12. Table 23-13. Table 23-14. Table 23-15. Table 23-16. Table 23-17. Table 23-18. Table 23-19. Table 23-20. Table 23-21. Table 23-22. Table 23-23. Table 23-24. Table 24-1. Table 24-2. Table 25-1. Table 25-2. Table 25-3. Table 25-4. Table 25-5. Table 26-1. Table 26-2. Table 27-1. Table 27-2. Table 29-1. Table 29-2. Table 29-3. Table 29-4. Table 29-5. Table 29-6. Table 29-7. Table 30-1.
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Tiva™ TM4C129ENCPDT Microcontroller Table 30-9. Table 30-10. Table 30-11. Table 30-12. Table 30-13. Table 30-14. Table 30-15. Table 30-16. Table 30-17. Table 30-18. Table 30-19. Table 30-20. Table 30-21. Table 30-22. Table 30-23. Table 30-24. Table 30-25. Table 30-26. Table 30-27. Table 30-28. Table 30-29. Table 30-30. Table 30-31. Table 30-32. Table 30-33. Table 30-34. Table 30-35. Table 30-36. Table 30-37. Table 30-38. Table 30-39. Table 30-40. Table 30-41. Table 30-42. Table 30-43. Table 30-44.
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Table of Contents Table 30-57. Table 30-58. Table 30-59. Table 30-60. Table 30-61. Table 30-62. Table 30-63. Table 30-64. ULPI Interface Timing ....................................................................................... 1999 Analog Comparator Characteristics ................................................................... 2001 Analog Comparator Voltage Reference Characteristics ...................................... 2001 Analog Comparator Voltage Reference Characteristics, VDDA = 3.
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Tiva™ TM4C129ENCPDT Microcontroller List of Registers The Cortex-M4F Processor ........................................................................................................... 86 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Cortex General-Purpose Register 0 (R0) ....
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Table of Contents Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Register 51: Register 52: Register 53: Register 54: Register 55: Register 56: Register 57: Register 58: Register 59:
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Tiva™ TM4C129ENCPDT Microcontroller Register 70: Register 71: Register 72: Register 73: Register 74: Register 75: Register 76: Register 77: Register 78: Register 79: Register 80: Register 81: Register 82: Register 83: MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 201 MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 203 MPU Region Base Address (MPUBASE), offset 0xD9C .........................
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Table of Contents Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Register 51: Register 52: Register 53: Register 54: Register 55: Register 56: Register 57: Register 58: Register 59: Register 60: Register 61: Register 62: Register 63: Register 64: Register 65: Register 66: Register 67: Register 68: Register 69: Register 70:
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Tiva™ TM4C129ENCPDT Microcontroller Register 80: Register 81: Register 82: Register 83: Register 84: Register 85: Register 86: Register 87: Register 88: Register 89: Register 90: Register 91: Register 92: Register 93: Register 94: Register 95: Register 96: Register 97: Register 98: Register 99: Register 100: Register 101: Register 102: Register 103: Register 104: Register 105: Register 106: Register 107: Register 108: Register 109: Register 110: Register 111: Register 112: Register 113: Register 114: Regis
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Table of Contents Register 117: Controller Area Network Sleep Mode Clock Gating Control (SCGCCAN), offset 0x734 ....... 426 Register 118: Analog-to-Digital Converter Sleep Mode Clock Gating Control (SCGCADC), offset 0x738 ........................................................................................................................... 427 Register 119: Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP), offset 0x73C ..........
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Tiva™ TM4C129ENCPDT Microcontroller Register 151: Register 152: Register 153: Register 154: Register 155: Register 156: Register 157: Register 158: Register 159: Register 160: Register 161: Register 162: Register 163: Register 164: Register 165: Register 166: Register 167: Register 168: Register 169: Register 170: Register 171: Register 172: Register 173: Register 174: Register 175: Register 176: Register 177: Register 178: Register 179: Register 180: Register 181: Register 182: Register 183: Register 184:
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Table of Contents Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 ..................................................
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Tiva™ TM4C129ENCPDT Microcontroller Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Register 51: Register 52: Register 53: Register 54: Register 55: Registe
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Table of Contents Register 68: Register 69: Register 70: Register 71: Register 72: Boot Configuration (BOOTCFG), offset 0x1D0 ................................................................. User Register 0 (USER_REG0), offset 0x1E0 .................................................................. User Register 1 (USER_REG1), offset 0x1E4 .................................................................. User Register 2 (USER_REG2), offset 0x1E8 ..........................................................
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Tiva™ TM4C129ENCPDT Microcontroller Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: GPIO Mas
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Table of Contents Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: EPI Read Size 1 (EPIRSIZE1), offset 0
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Tiva™ TM4C129ENCPDT Microcontroller Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: AES Key 2_1 (AES_KEY2
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Table of Contents Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: DES Revision Number (DES_REVISION), offset 0x030 .................................................. 1033 DES System Configuration (DES_SYSCONFIG), offset 0x034 ........................................ 1034 DES System Status (DES_SYSSTATUS), offset 0x038 .................................................. 1036 DES Interrupt Status (DES_IRQSTATUS), offset 0x03C .
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Tiva™ TM4C129ENCPDT Microcontroller Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: SHA System Status (SHA_SYSSTATUS), offset 0x114 ................................................... SHA Interrupt Status (SHA_IRQSTATUS), offset 0x118 .................................................. SHA Interrupt Enable (SHA_IRQENABLE), offset 0x11C ................................................ SHA DMA Interrupt Mask (SHA_DMAIM), offset 0x010 ................................
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Table of Contents Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC .............................. Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ............................... Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ............................... Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................
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Tiva™ TM4C129ENCPDT Microcontroller Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Register 51: Register 52: Register 53: Register 54: Register 55: Register 56: Register 57: Register 58: Register 59: Register 60: Register 61: Register 62: Register 63: Register 64: Register 65: Register 66: ADC Sample Sequence Extended Input Multiplexer Select 1 (ADCSSEMUX1), offset 0x078 .
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Table of Contents Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: UART 9-Bit Self Address (UART9BITADDR), offset 0x0A4 ............................................. 1333 UART 9-Bit Self Address Mask (UART9BITAMASK), offset 0x0A8 .................................. 1334 UART Peripheral Properties (UARTPP), offset 0xFC0 ...............................
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Tiva™ TM4C129ENCPDT Microcontroller Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 .......................................... 1445 I2C Master Interrupt Clear (I2CMICR), offset 0x01C ..............................................
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Table of Contents Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ............................................................... 1526 CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ............................................................... 1526 CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ...............................................................
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Tiva™ TM4C129ENCPDT Microcontroller Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Register 51: Register 52: Register 53: Register 54: Register 55: Register 56: Register 57: Register 58: Register 59: Register 60: Register 61: Register 62: Register 63: Register 64: Register 65: Register 66: Register 67: Registe
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Table of Contents Register 76: Register 77: Ethernet PHY Auto-Negotiation Advertisement - MR4 (EPHYANA), address 0x004 .......... 1721 Ethernet PHY Auto-Negotiation Link Partner Ability - MR5 (EPHYANLPA), address 0x005 .......................................................................................................................... 1723 Register 78: Ethernet PHY Auto-Negotiation Expansion - MR6 (EPHYANER), address 0x006 .............
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Tiva™ TM4C129ENCPDT Microcontroller Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register
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Table of Contents Register 57: Register 58: Register 59: Register 60: Register 61: Register 62: Register 63: Register 64: Register 65: Register 66: Register 67: Register 68: Register 69: Register 70: Register 71: Register 72: Register 73: Register 74: Register 75: Register 76: Register 77: Register 78: Register 79: Register 80: Register 81: Register 82: Register 83: Register 84: Register 85: Register 86: Register 87: Register 88: Register 89: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ...
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Tiva™ TM4C129ENCPDT Microcontroller Revision History The revision history table notes changes made between the indicated revisions of the TM4C129ENCPDT data sheet. Table 1. Revision History Date June 2014 April 2014 Revision Description 15863.2743 ■ In ADC chapter, clarified section "Sample and Hold Window Control". ■ In SSI chapter: – Noted that during idle periods the transmit data line SSInTx is tristated. – Added clarification to uDMA section about wait states.
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Revision History Table 1. Revision History (continued) Date Revision Description – – December 2013 Corrected figure ADC Input Equivalency. Removed Dither Enable bit and corrected reset for ADCCTL register. ■ In the UART chapter, clarified that for a receive timeout, the RTIM bit in the UARTIM register must be set to see the RTMIS and RTRIS status in the UARTMIS and UARTRIS registers. ■ In the SSI chapter: – Clarified Receive FIFO operation. – Clarified DMA operation.
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Tiva™ TM4C129ENCPDT Microcontroller Table 1. Revision History (continued) Date Revision Description – – – – October 2013 Added subsections to "Flash Memory" section about Execute-Only Protection, Read-Only Protection and Permanently Disabling Debug. Removed INVPL bit from EEPROM Done Status (EEDONE) register. Updated table "MEMTIM0 Register Configuration vs. Frequency" with lower wait states, and improved performance values.
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About This Document About This Document This data sheet provides reference information for the TM4C129ENCPDT microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M4F core. Audience This manual is intended for system software developers, hardware designers, and application developers. About This Manual This document is organized into sections that correspond to each major feature.
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Tiva™ TM4C129ENCPDT Microcontroller Documentation Conventions This document uses the conventions shown in Table 2 on page 53. Table 2. Documentation Conventions Notation Meaning General Register Notation REGISTER APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register.
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About This Document Table 2. Documentation Conventions (continued) Notation Meaning assert a signal Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below).
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Tiva™ TM4C129ENCPDT Microcontroller 1 Architectural Overview ® Texas Instrument's Tiva™ C Series microcontrollers provide designers a high-performance ARM Cortex™-M-based architecture with a broad set of integration capabilities and a strong ecosystem of software and development tools. Targeting performance and flexibility, the Tiva™ C Series architecture offers a 120 MHz Cortex-M with FPU, a variety of integrated memories and multiple programmable GPIO.
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Architectural Overview In addition, Tiva™ C Series microcontrollers offer the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure, and a large user community. Additionally, these microcontrollers use ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, the TM4C129ENCPDT microcontroller is code-compatible to all members of the extensive Tiva™ C Series, providing flexibility to fit precise needs.
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Tiva™ TM4C129ENCPDT Microcontroller Table 1-1. TM4C129ENCPDT Microcontroller Features (continued) Feature Description Hibernation Module (HIB) Low-power battery-backed Hibernation module General-Purpose Input/Output (GPIO) 15 physical GPIO blocks Advanced Motion Control Pulse Width Modulator (PWM) One PWM module, with four PWM generator blocks and a control block, for a total of 8 PWM outputs.
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Architectural Overview Figure 1-1. Tiva™ TM4C129ENCPDT Microcontroller High-Level Block Diagram JTAG/SWD ARM® Cortex™-M4F ROM (120MHz) System Control and Clocks (w/ Precis. Osc.
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Tiva™ TM4C129ENCPDT Microcontroller 1.3 TM4C129ENCPDT Microcontroller Features The TM4C129ENCPDT microcontroller component features and general function are discussed in more detail in the following section. 1.3.1 ARM Cortex-M4F Processor Core All members of the Tiva™ C Series, including the TM4C129ENCPDT microcontroller, are designed around an ARM Cortex-M processor core.
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Architectural Overview ■ Migration from the ARM7™ processor family for better performance and power efficiency ■ Optimized for single-cycle Flash memory usage up to specific frequencies; see “Internal Memory” on page 608 for more information. ■ Ultra-low power consumption with integrated sleep modes 1.3.1.2 System Timer (SysTick) (see page 142) ARM Cortex-M4F includes an integrated system timer, SysTick.
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Tiva™ TM4C129ENCPDT Microcontroller 1.3.1.6 Floating-Point Unit (FPU) (see page 149) The FPU fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions.
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Architectural Overview 1.3.2.2 Flash Memory (see page 612) The TM4C129ENCPDT microcontroller provides 1024 KB of on-chip Flash memory. The Flash memory is configured as four banks of 16K x 128 bits (4 * 256 KB total) which are two-way interleaved. Memory blocks can be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified.
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Tiva™ TM4C129ENCPDT Microcontroller 1.3.2.
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Architectural Overview – Includes automatic refresh and access to all banks/rows – Includes a Sleep/Standby mode to keep contents active with minimal power draw – Multiplexed address/data interface for reduced pin count ■ Host-Bus mode – Traditional x8 and x16 MCU bus interface capabilities – Similar device compatibility options as PIC, ATmega, 8051, and others – Access to SRAM, NOR Flash memory, and other devices, with up to 1 MB of addressing in non-multiplexed mode and 256 MB in multiplexed mode (512 MB
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Tiva™ TM4C129ENCPDT Microcontroller 1.3.4 Cyclical Redundancy Check (CRC) (see page 954) The TM4C129ENCPDT microcontroller includes a CRC computation module for uses such as message transfer and safety system checks. This module can be used in conjunction with the AES and DES modules. The CRC has the following features: ■ Support four major CRC forms: – CRC16-CCITT as used by CCITT/ITU X.25 – CRC16-IBM as used by USB and ANSI – CRC32-IEEE as used by IEEE802.3 and MPEG2 – CRC32C as used by G.
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Architectural Overview ■ Support for CBC_MAC and Fedora 9 (F9) authentication modes ■ Basic GHASH operation (when selecting no encryption) ■ Key scheduling in hardware ■ Support for µDMA transfers ■ Fully synchronous design 1.3.6 Data Encryption Standard (DES) Accelerator (see page 1015) The DES module provides hardware accelerated data encryption and decryption functions.
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Tiva™ TM4C129ENCPDT Microcontroller 1.3.8 Serial Communications Peripherals The TM4C129ENCPDT controller supports both asynchronous and synchronous serial communications with: ■ 10/100 Ethernet MAC with Advanced IEEE 1588 PTP hardware and both Media Independent Interface (MII) and Reduced MII (RMII) support; integrated PHY provided ■ Two CAN 2.0 A/B controllers ■ USB 2.
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Architectural Overview – Promiscuous mode support ■ Processor offloading – Programmable insertion (TX) or deletion (RX) of preamble and start-of-frame data – Programmable generation (TX) or deletion (RX) of CRC and pad data – IP header and hardware checksum checking (IPv4, IPv6, TCP/UDP/ICMP) ■ Highly configurable – LED activity selection – Supports network statistics with RMON/MIB counters – Supports Magic Packet and wakeup frames ■ Efficient transfers using integrated Direct Memory Access (DMA) – Dual-bu
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Tiva™ TM4C129ENCPDT Microcontroller ■ Maskable interrupt ■ Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications ■ Programmable loopback mode for self-test operation ■ Programmable FIFO mode enables storage of multiple message objects ■ Gluelessly attaches to an external CAN transceiver through the CANnTX and CANnRX signals 1.3.8.
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Architectural Overview The TM4C129ENCPDT microcontroller includes eight fully programmable 16C550-type UARTs. Although the functionality is similar to a 16C550 UART, this UART design is not register compatible. The UART can generate individually masked interrupts from the Rx, Tx, modem flow control, modem status, and error conditions. The module generates a single combined interrupt when any of the interrupts are asserted and are unmasked.
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Tiva™ TM4C129ENCPDT Microcontroller ■ Standard FIFO-level and End-of-Transmission interrupts ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level – Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level ■ Global Alternate Clock (ALTCLK) resource or System Clock (SYSCLK) can be u
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Architectural Overview – High-speed mode (3.
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Tiva™ TM4C129ENCPDT Microcontroller ■ Internal loopback test mode for diagnostic/debug testing ■ Standard FIFO-based interrupts and End-of-Transmission interrupt ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted when FIFO contains 4 entries – Transmit single request asserted when there is space in the FIFO; burst request asserted when four or more entries ar
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Architectural Overview ■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes – Basic for simple transfer scenarios – Ping-pong for continuous data flow – Scatter-gather for a programmable list of up to 256 arbitrary transfers initiated from a single request ■ Highly flexible and configurable channel operation – Independently configured and operated channels – Dedicated channels for supported on-chip modules – Flexible channel assignments – One channel eac
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Tiva™ TM4C129ENCPDT Microcontroller – On-chip fixed Low Drop-Out (LDO) voltage regulator – Hibernation module handles the power-up/down 3.3 V sequencing and control for the core digital logic and analog circuits – Low-power options for microcontroller: Sleep and Deep-Sleep modes with clock gating – Low-power options for on-chip modules: software controls shutdown of individual peripherals and memory – 3.
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Architectural Overview Real-Time Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions and DMA transfers. The General-Purpose Timer Module (GPTM) contains eight 16/32-bit GPTM blocks with the following functional options: ■ Operating modes: – 16- or 32-bit programmable one-shot timer – 16- or 32-bit programmable periodic timer – 16-bit general-purpose timer with an 8-bit prescaler – 32-bit Real-Time Clock (RTC) when using an external 32.
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Tiva™ TM4C129ENCPDT Microcontroller The TM4C129ENCPDT microcontroller includes twelve 16/32-bit CCP pins that can be programmed to operate in the following modes: ■ Capture: The GP Timer is incremented/decremented by programmed events on the CCP input. The GP Timer captures and stores the current timer value when a programmed event occurs. ■ Compare: The GP Timer is incremented/decremented by programmed events on the CCP input.
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Architectural Overview – Logging of up to four tamper events – Optional BBRAM erase on tamper detection – Tamper wake from hibernate capability – Hibernation clock input failure detect with a switch to the internal oscillator on detection ■ RTC operational and hibernation memory valid as long as VDD or VBAT is valid ■ Low-battery detection, signaling, and interrupt generation, with optional wake on low battery ■ GPIO pin state can be retained during hibernation ■ Clock source from an internal low frequency
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Tiva™ TM4C129ENCPDT Microcontroller an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports 0-90 programmable input/output pins. The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page 1896 for the signals available to each GPIO pin). ■ Up to 90 GPIOs, depending on configuration ■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions ■ 3.
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Architectural Overview ■ One Quadrature Encoder Input (QEI) The following provides more detail on these motion control functions. 1.3.10.1 PWM (see page 1793) The TM4C129ENCPDT microcontroller contains one PWM module, with four PWM generator blocks and a control block, for a total of 8 PWM outputs. Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
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Tiva™ TM4C129ENCPDT Microcontroller The control block determines the polarity of the PWM signals and which signals are passed through to the pins. The output of the PWM generation blocks are managed by the output control block before being passed to the device pins.
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Architectural Overview 1.3.11 Analog The TM4C129ENCPDT microcontroller provides analog functions integrated into the device, including: ■ Two 12-bit Analog-to-Digital Converters (ADC), with a total of 20 analog input channels and each with a sample rate of two million samples/second ■ Three analog comparators ■ On-chip voltage regulator The following provides more detail on these analog functions. 1.3.11.
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Tiva™ TM4C129ENCPDT Microcontroller ■ Eight digital comparators ■ Converter uses signals VREFA+ and GNDA as the voltage reference ■ Power and ground for the analog circuitry is separate from the digital power and ground ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Dedicated channel for each sample sequencer – ADC module uses burst requests for DMA ■ Global Alternate Clock (ALTCLK) resource or System Clock (SYSCLK) can be used to generate ADC clock 1.3.11.
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Architectural Overview ■ Four-bit Instruction Register (IR) chain for storing JTAG instructions ■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, and EXTEST ■ ARM additional instructions: APACC, DPACC and ABORT ■ Integrated ARM Serial Wire Debug (SWD) – Serial Wire JTAG Debug Port (SWJ-DP) – Flash Patch and Breakpoint (FPB) unit for implementing breakpoints – Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and system profiling – Instrumentation Trace Macroc
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Tiva™ TM4C129ENCPDT Microcontroller See the Tiva series website at http://www.ti.com/tiva-c for the latest tools available, or ask your distributor. 1.6 Support Information For support on Tiva™ C Series products, contact the TI Worldwide Product Information Center nearest you.
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The Cortex-M4F Processor 2 The Cortex-M4F Processor The ARM® Cortex™-M4F processor provides a high-performance, low-cost platform that meets the system requirements of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts.
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Tiva™ TM4C129ENCPDT Microcontroller The Tiva™ C Series microcontrollers builds on this core to bring high-performance 32-bit computing to cost-conscious applications requiring significant control processing and connectivity capabilities such as: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Low power, hand-held smart devices Gaming equipment Network appliances and switches Home and commercial site monitoring and control Electronic point-of-sale (POS) machines Motion control Medical instrumentation Remote connectivity and m
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The Cortex-M4F Processor Figure 2-1. CPU Block Diagram Nested Vectored Interrupt Controller FPU Interrupts Sleep ARM Cortex-M4F CM4 Core Debug Instructions Data Embedded Trace Macrocell Memory Protection Unit Flash Patch and Breakpoint Instrumentation Data Watchpoint Trace Macrocell and Trace ROM Table Private Peripheral Bus (internal) Adv. Peripheral Bus Bus Matrix Serial Wire JTAG Debug Port Debug Access Port 2.2 Overview 2.2.
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Tiva™ TM4C129ENCPDT Microcontroller The Embedded Trace Macrocell (ETM) delivers unrivaled instruction trace capture in an area smaller than traditional trace units, enabling full instruction trace. For more details on the ARM ETM, see the ARM® Embedded Trace Macrocell Architecture Specification. The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators that debuggers can use.
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The Cortex-M4F Processor An embedded interrupt controller that supports low latency interrupt processing (see “Nested Vectored Interrupt Controller (NVIC)” on page 143). ■ System Control Block (SCB) The programming model interface to the processor. The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions (see “System Control Block (SCB)” on page 144).
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Tiva™ TM4C129ENCPDT Microcontroller Only privileged software can write to the CONTROL register to change the privilege level for software execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to privileged software. 2.3.2 Stacks The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item on the memory.
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The Cortex-M4F Processor Figure 2-3. Cortex-M4F Register Set R0 R1 R2 R3 Low registers R4 R5 General-purpose registers R6 R7 R8 R9 High registers R10 R11 R12 Stack Pointer SP (R13) Link Register LR (R14) Program Counter PC (R15) PSP‡ PSR MSP‡ ‡ Banked version of SP Program status register PRIMASK FAULTMASK Exception mask registers Special registers BASEPRI CONTROL CONTROL register Table 2-2.
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Tiva™ TM4C129ENCPDT Microcontroller Table 2-2. Processor Register Map (continued) Offset Name Type Reset Description See page - R12 RW - Cortex General-Purpose Register 12 94 - SP RW - Stack Pointer 95 - LR RW 0xFFFF.FFFF Link Register 96 - PC RW - Program Counter 97 - PSR RW 0x0100.0000 Program Status Register 98 - PRIMASK RW 0x0000.0000 Priority Mask Register 102 - FAULTMASK RW 0x0000.0000 Fault Mask Register 103 - BASEPRI RW 0x0000.
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The Cortex-M4F Processor Register 1: Cortex General-Purpose Register 0 (R0) Register 2: Cortex General-Purpose Register 1 (R1) Register 3: Cortex General-Purpose Register 2 (R2) Register 4: Cortex General-Purpose Register 3 (R3) Register 5: Cortex General-Purpose Register 4 (R4) Register 6: Cortex General-Purpose Register 5 (R5) Register 7: Cortex General-Purpose Register 6 (R6) Register 8: Cortex General-Purpose Register 7 (R7) Register 9: Cortex General-Purpose Register 8 (R8) Register 10: Cortex General
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Tiva™ TM4C129ENCPDT Microcontroller Register 14: Stack Pointer (SP) The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear, this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value from address 0x0000.0000.
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The Cortex-M4F Processor Register 15: Link Register (LR) The Link Register (LR) is register R14, and it stores the return information for subroutines, function calls, and exceptions. The Link Register can be accessed from either privileged or unprivileged mode. EXC_RETURN is loaded into the LR on exception entry. See Table 2-10 on page 130 for the values and description. Link Register (LR) Type RW, reset 0xFFFF.
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Tiva™ TM4C129ENCPDT Microcontroller Register 16: Program Counter (PC) The Program Counter (PC) is register R15, and it contains the current program address. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit 0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register can be accessed in either privileged or unprivileged mode.
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The Cortex-M4F Processor Register 17: Program Status Register (PSR) Note: This register is also referred to as xPSR.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 31 N RW 0 Description APSR Negative or Less Flag Value Description 1 The previous operation result was negative or less than. 0 The previous operation result was positive, zero, greater than, or equal. The value of this bit is only meaningful when accessing PSR or APSR. 30 Z RW 0 APSR Zero Flag Value Description 1 The previous operation result was zero. 0 The previous operation result was non-zero.
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The Cortex-M4F Processor Bit/Field Name Type Reset 26:25 ICI / IT RO 0x0 Description EPSR ICI / IT status These bits, along with bits 15:10, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction. When EPSR holds the ICI execution state, bits 26:25 are zero. The If-Then block contains up to four instructions following an IT instruction.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 15:10 ICI / IT RO 0x0 Description EPSR ICI / IT status These bits, along with bits 26:25, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction.
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The Cortex-M4F Processor Register 18: Priority Mask Register (PRIMASK) The PRIMASK register prevents activation of all exceptions with programmable priority. Reset, non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode.
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Tiva™ TM4C129ENCPDT Microcontroller Register 19: Fault Mask Register (FAULTMASK) The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. The MSR and MRS instructions are used to access the FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK register.
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The Cortex-M4F Processor Register 20: Base Priority Mask Register (BASEPRI) The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode.
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Tiva™ TM4C129ENCPDT Microcontroller Register 21: Control Register (CONTROL) The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode, and indicates whether the FPU state is active. This register is only accessible in privileged mode. Handler mode always uses the MSP, so the processor ignores explicit writes to the ASP bit of the CONTROL register when in Handler mode.
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The Cortex-M4F Processor Bit/Field Name Type Reset 1 ASP RW 0 Description Active Stack Pointer Value Description 1 The PSP is the current stack pointer. 0 The MSP is the current stack pointer In Handler mode, this bit reads as zero and ignores writes. The Cortex-M4F updates this bit automatically on exception return. 0 TMPL RW 0 Thread Mode Privilege Level Value Description 1 Unprivileged software can be executed in Thread mode. 0 Only privileged software can be executed in Thread mode.
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Tiva™ TM4C129ENCPDT Microcontroller Register 22: Floating-Point Status Control (FPSC) The FPSC register provides all necessary user-level control of the floating-point system.
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The Cortex-M4F Processor Bit/Field Name Type Reset 23:22 RMODE RW - Description Rounding Mode The specified rounding mode is used by almost all floating-point instructions. The RMODE bit in the FPDSC register holds the default value for this bit.
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Tiva™ TM4C129ENCPDT Microcontroller 2.3.5 Exceptions and Interrupts The Cortex-M4F processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses Handler mode to handle all exceptions except for reset. See “Exception Entry and Return” on page 127 for more information. The NVIC registers control interrupt handling.
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The Cortex-M4F Processor Table 2-4. Memory Map (continued) Start End Description For details, see page ... 0x4000.4000 0x4000.4FFF GPIO Port A 763 0x4000.5000 0x4000.5FFF GPIO Port B 763 0x4000.6000 0x4000.6FFF GPIO Port C 763 0x4000.7000 0x4000.7FFF GPIO Port D 763 0x4000.8000 0x4000.8FFF SSI0 1367 0x4000.9000 0x4000.9FFF SSI1 1367 0x4000.A000 0x4000.AFFF SSI2 1367 0x4000.B000 0x4000.BFFF SSI3 1367 0x4000.C000 0x4000.CFFF UART0 1297 0x4000.D000 0x4000.
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Tiva™ TM4C129ENCPDT Microcontroller Table 2-4. Memory Map (continued) Start End Description For details, see page ... 0x4003.D000 0x4003.DFFF GPIO Port J 763 0x4003.E000 0x4003.FFFF Reserved - 0x4004.0000 0x4004.0FFF CAN0 Controller 1499 0x4004.1000 0x4004.1FFF CAN1 Controller 1499 0x4004.2000 0x4004.FFFF Reserved - 0x4005.0000 0x4005.0FFF USB 1770 0x4005.1000 0x4005.7FFF Reserved - 0x4005.8000 0x4005.8FFF GPIO Port A (AHB aperture) 763 0x4005.9000 0x4005.
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The Cortex-M4F Processor Table 2-4. Memory Map (continued) Start End Description For details, see page ... 0x400F.A000 0x400F.BFFF Reserved - 0x400F.C000 0x400F.CFFF Hibernation Module 559 0x400F.D000 0x400F.DFFF Flash memory control 629 0x400F.E000 0x400F.EFFF System control 254 0x400F.F000 0x400F.FFFF µDMA 709 0x4010.0000 0x41FF.FFFF Reserved - 0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF - 0x4400.0000 0x4402.FFFF Reserved - 0x4403.
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Tiva™ TM4C129ENCPDT Microcontroller ■ Strongly Ordered: The processor preserves transaction order relative to all other transactions. The different ordering requirements for Device and Strongly Ordered memory mean that the memory system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory. An additional memory attribute is Execute Never (XN), which means the processor prevents instruction accesses.
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The Cortex-M4F Processor The Cortex-M4F prefetches instructions ahead of execution and speculatively prefetches from branch target addresses. 2.4.4 Software Ordering of Memory Accesses The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions for the following reasons: ■ The processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence.
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Tiva™ TM4C129ENCPDT Microcontroller ■ Memory map switching If the system contains a memory map switching mechanism, use a DSB instruction after switching the memory map in the program. The DSB instruction ensures subsequent instruction execution uses the updated memory map. ■ Dynamic exception priority change When an exception priority has to change when the exception is pending or active, use DSB instructions after the change. The change then takes effect on completion of the DSB instruction.
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The Cortex-M4F Processor bit_word_offset = (byte_offset x 32) + (bit_number x 4) bit_word_addr = bit_band_base + bit_word_offset where: bit_word_offset The position of the target bit in the bit-band memory region. bit_word_addr The address of the word in the alias memory region that maps to the targeted bit. bit_band_base The starting address of the alias region. byte_offset The number of the byte in the bit-band region that contains the targeted bit. bit_number The bit position, 0-7, of the targeted bit.
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Tiva™ TM4C129ENCPDT Microcontroller Figure 2-4. Bit-Band Mapping 32-MB Alias Region 0x23FF.FFFC 0x23FF.FFF8 0x23FF.FFF4 0x23FF.FFF0 0x23FF.FFEC 0x23FF.FFE8 0x23FF.FFE4 0x23FF.FFE0 0x2200.001C 0x2200.0018 0x2200.0014 0x2200.0010 0x2200.000C 0x2200.0008 0x2200.0004 0x2200.0000 7 3 1-MB SRAM Bit-Band Region 7 6 5 4 3 2 1 0 7 6 0x200F.FFFF 7 6 5 4 3 2 0x2000.0003 2.4.5.1 5 4 3 2 1 0 7 6 0x200F.FFFE 1 0 7 6 5 4 3 2 5 4 3 2 1 0 6 0x200F.
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The Cortex-M4F Processor Figure 2-5. Data Storage Memory 7 Register 0 31 2.4.7 Address A B0 A+1 B1 A+2 B2 A+3 B3 lsbyte 24 23 B3 16 15 B2 8 7 B1 0 B0 msbyte Synchronization Primitives The Cortex-M4F instruction set includes pairs of synchronization primitives which provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location.
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Tiva™ TM4C129ENCPDT Microcontroller If the status bit is clear, the read-modify-write completed successfully. If the status bit is set, no write was performed, which indicates that the value returned at step 1 might be out of date. The software must retry the entire read-modify-write sequence. Software can use the synchronization primitives to implement a semaphore as follows: 1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free. 2.
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The Cortex-M4F Processor the NVIC sees the interrupt as still asserted, causing the interrupt handler to be re-entered errantly. This situation can be avoided by either clearing the interrupt source at the beginning of the interrupt handler or by performing a read or write after the write to clear the interrupt source (and flush the write buffer). See “Nested Vectored Interrupt Controller (NVIC)” on page 143 for more information on exceptions and interrupts. 2.5.
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Tiva™ TM4C129ENCPDT Microcontroller ■ Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction execution, such as: – An undefined instruction – An illegal unaligned access – Invalid state on instruction execution – An error on exception return An unaligned address on a word or halfword memory access or division by zero can cause a usage fault when the core is properly configured. ■ SVCall.
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The Cortex-M4F Processor Table 2-8. Exception Types (continued) Exception Type a Vector Number Priority Bus Fault 5 programmable Usage Fault 6 7-10 - Vector Address or b Offset Activation c 0x0000.0014 Synchronous when precise and asynchronous when imprecise programmable c 0x0000.0018 Synchronous - c c Reserved SVCall 11 programmable 0x0000.002C Synchronous Debug Monitor 12 programmable 0x0000.0030 Synchronous - 13 - 0x0000.0038 Asynchronous c 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Table 2-9. Interrupts (continued) Vector Number Interrupt Number (Bit in Interrupt Registers) Vector Address or Offset Description 38 22 0x0000.0098 16/32-Bit Timer 1B 39 23 0x0000.009C 16/32-Bit Timer 2A 40 24 0x0000.00A0 16/32-Bit Timer 2B 41 25 0x0000.00A4 Analog Comparator 0 42 26 0x0000.00A8 Analog Comparator 1 43 27 0x0000.00AC Analog Comparator 2 44 28 0x0000.00B0 System Control 45 29 0x0000.
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The Cortex-M4F Processor Table 2-9. Interrupts (continued) Vector Number Interrupt Number (Bit in Interrupt Registers) Vector Address or Offset Description 79 63 0x0000.013C Timer 4A 80 64 0x0000.0140 Timer 4B 81 65 0x0000.0144 Timer 5A 82 66 0x0000.0148 Timer 5B 83 67 0x0000.014C Floating-Point Exception (imprecise) 84-85 68-69 - 86 70 0x0000.0158 I2C 4 87 71 0x0000.015C I2C 5 88 72 0x0000.0160 GPIO Port M 89 73 0x0000.0164 GPIO Port N 90 74 - 91 75 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Table 2-9. Interrupts (continued) 2.5.3 Vector Number Interrupt Number (Bit in Interrupt Registers) Vector Address or Offset 126 110 0x0000.01F8 127-129 111-113 - Description I2C 9 Reserved Exception Handlers The processor handles exceptions using: ■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs. ■ Fault Handlers.
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The Cortex-M4F Processor Figure 2-6. Vector Table Exception number IRQ number Offset 0x040 + 0x(N*4) . . . 0x004C Vector 2 0x0048 IRQ2 17 1 0x0044 IRQ1 16 0 0x0040 IRQ0 15 -1 0x003C Systick 14 -2 0x0038 PendSV (N+16) (N) . . . 18 IRQ N . . .
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Tiva™ TM4C129ENCPDT Microcontroller If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1]. When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs.
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The Cortex-M4F Processor return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply. 2.5.7.1 Exception Entry Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in Thread mode or the new exception is of higher priority than the exception being handled, in which case the new exception preempts the original exception. When one exception preempts another, the exceptions are nested.
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Tiva™ TM4C129ENCPDT Microcontroller Figure 2-7. Exception Stack Frame ... {aligner} FPSCR S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 xPSR PC LR R12 R3 R2 R1 R0 Exception frame with floating-point storage Pre-IRQ top of stack Decreasing memory address IRQ top of stack ... {aligner} xPSR PC LR R12 R3 R2 R1 R0 Pre-IRQ top of stack IRQ top of stack Exception frame without floating-point storage Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.
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The Cortex-M4F Processor ■ An LDM or POP instruction that loads the PC ■ A BX instruction using any register ■ An LDR instruction with the PC as the destination EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest five bits of this value provide information on the return stack and processor mode.
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Tiva™ TM4C129ENCPDT Microcontroller ■ An internally detected error such as an undefined instruction or an attempt to change state with a BX instruction. ■ Attempting to execute an instruction from a memory region marked as Non-Executable (XN). ■ An MPU fault because of a privilege violation or an attempt to access an unmanaged region. 2.6.
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The Cortex-M4F Processor Usually, the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler as described in “Exception Model” on page 119. In some situations, a fault with configurable priority is treated as a hard fault. This process is called priority escalation, and the fault is described as escalated to hard fault.
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Tiva™ TM4C129ENCPDT Microcontroller 2.7 Power Management The Cortex-M4F processor sleep modes reduce power consumption: ■ Sleep mode stops the processor clock. ■ Deep-sleep mode stops the system clock and switches off the PLL and Flash memory. The SLEEPDEEP bit of the System Control (SYSCTRL) register selects which sleep mode is used (see page 180). For more information about the behavior of the sleep modes, see “System Control” on page 246.
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The Cortex-M4F Processor 2.7.2.1 Wake Up from WFI or Sleep-on-Exit Normally, the processor wakes up only when the NVIC detects an exception with sufficient priority to cause exception entry. Some embedded systems might have to execute system restore tasks after the processor wakes up and before executing an interrupt handler. Entry to the interrupt handler can be delayed by setting the PRIMASK bit and clearing the FAULTMASK bit.
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Tiva™ TM4C129ENCPDT Microcontroller Table 2-13.
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The Cortex-M4F Processor Table 2-13.
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Tiva™ TM4C129ENCPDT Microcontroller Table 2-13.
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The Cortex-M4F Processor Table 2-13.
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Tiva™ TM4C129ENCPDT Microcontroller Table 2-13.
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The Cortex-M4F Processor Table 2-13. Cortex-M4F Instruction Summary (continued) Mnemonic Operands Brief Description Flags VFNMA.F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply Accumulate - VFMS.F32 {Sd,} Sn, Sm Floating-point Fused Multiply Subtract - VFNMS.F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply Subtract - VLDM.F<32|64> Rn{!}, list Load Multiple extension registers - VLDR.F<32|64> , [Rn] Load an extension register from memory - VLMA.
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Tiva™ TM4C129ENCPDT Microcontroller 3 Cortex-M4 Peripherals This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4 processor peripherals, including: ■ SysTick (see page 142) Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism.
PAGE 142
Cortex-M4 Peripherals 3.1.1 System Timer (SysTick) Cortex-M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example as: ■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock.
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Tiva™ TM4C129ENCPDT Microcontroller 3.1.2 Nested Vectored Interrupt Controller (NVIC) This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: ■ 106 interrupts. ■ A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. ■ Low-latency exception and interrupt handling. ■ Level and pulse detection of interrupt signals.
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Cortex-M4 Peripherals ■ The processor enters the ISR for the interrupt, changing the state of the interrupt from pending to active. Then: – For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive.
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Tiva™ TM4C129ENCPDT Microcontroller Table 3-2 on page 145 shows the possible MPU region attributes. See the section called “MPU Configuration for a Tiva™ C Series Microcontroller” on page 149 for guidelines for programming a microcontroller implementation. Table 3-2. Memory Attributes Summary Memory Type Description Strongly Ordered All accesses to Strongly Ordered memory occur in program order.
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Cortex-M4 Peripherals STR R1, [R0, #0x0] BIC R2, R2, #1 STRH R2, [R0, #0x8] STR R4, [R0, #0x4] STRH R3, [R0, #0xA] ORR R2, #1 STRH R2, [R0, #0x8] ; ; ; ; ; ; ; Region Number Disable Region Size and Enable Region Base Address Region Attribute Enable Region Size and Enable Software must use memory barrier instructions: ■ Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in MPU settings.
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Tiva™ TM4C129ENCPDT Microcontroller ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0, =MPUBASE ; 0xE000ED9C, MPU Region Base register STR R1, [R0, #0x0] ; Region base address and region number combined ; with VALID (bit 4) set STR R2, [R0, #0x4] ; Region Attribute, Size and Enable Subregions Regions of 256 bytes or more are divided into eight equal-sized subregions.
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Cortex-M4 Peripherals Table 3-3. TEX, S, C, and B Bit Field Encoding (continued) TEX S C B Memory Type Shareability 000 0 1 0 Normal Not shareable 000 1 1 0 Normal Shareable 000 0 1 1 Normal Not shareable 000 1 1 1 Normal Shareable Other Attributes Outer and inner write-through. No write allocate. 001 0 0 0 Normal Not shareable 001 1 0 0 Normal Shareable Outer and inner non-cacheable.
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Tiva™ TM4C129ENCPDT Microcontroller Table 3-5. AP Bit Field Encoding (continued) AP Bit Field Privileged Permissions Unprivileged Permissions Description 110 RO RO Read-only, by privileged or unprivileged software. 111 RO RO Read-only, by privileged or unprivileged software. MPU Configuration for a Tiva™ C Series Microcontroller Tiva™ C Series microcontrollers have only a single processor and no caches. As a result, the MPU should be programmed as shown in Table 3-6 on page 149. Table 3-6.
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Cortex-M4 Peripherals 3.1.5.1 FPU Views of the Register Bank The FPU provides an extension register file containing 32 single-precision registers. These can be viewed as: ■ Sixteen 64-bit doubleword registers, D0-D15 ■ Thirty-two 32-bit single-word registers, S0-S31 ■ A combination of registers from the above views Figure 3-2. FPU Register Bank S0 S1 S2 S3 S4 S5 S6 S7 ... S28 S29 S30 S31 D0 D1 D2 D3 ...
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Tiva™ TM4C129ENCPDT Microcontroller VNEG, and VMOV operations. All other CDP operations ignore any information in the fraction bits of an input NaN. 3.1.5.3 Compliance with the IEEE 754 standard When Default NaN (DN) and Flush-to-Zero (FZ) modes are disabled, FPv4 functionality is compliant with the IEEE 754 standard in hardware. No support code is required to achieve this compliance. 3.1.5.
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Cortex-M4 Peripherals Table 3-7. QNaN and SNaN Handling Instruction Type Default NaN Mode With QNaN Operand With SNaN Operand Off The QNaN or one of the QNaN operands, if there is more than one, is returned according to the rules given in the ARM Architecture Reference Manual. IOC set. The SNaN is quieted and the result NaN is determined by the rules given in the ARM Architecture Reference Manual. On Default NaN returns. IOC set. Default NaN returns.
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Tiva™ TM4C129ENCPDT Microcontroller Control (CPAC) register. The below example code sequence enables the FPU in both privileged and user modes. ; CPACR is located at address 0xE000ED88 LDR.W R0, =0xE000ED88 ; Read CPACR LDR R1, [R0] ; Set bits 20-23 to enable CP10 and CP11 coprocessors ORR R1, R1, #(0xF << 20) ; Write back the modified value to the CPACR STR R1, [R0]; wait for store to complete DSB ;reset pipeline now the FPU is enabled ISB 3.
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Cortex-M4 Peripherals Table 3-8. Peripherals Register Map (continued) Offset Name 0x280 Description See page Type Reset UNPEND0 RW 0x0000.0000 Interrupt 0-31 Clear Pending 164 0x284 UNPEND1 RW 0x0000.0000 Interrupt 32-63 Clear Pending 164 0x288 UNPEND2 RW 0x0000.0000 Interrupt 64-95 Clear Pending 164 0x28C UNPEND3 RW 0x0000.0000 Interrupt 96-113 Clear Pending 164 0x300 ACTIVE0 RO 0x0000.0000 Interrupt 0-31 Active Bit 165 0x304 ACTIVE1 RO 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Table 3-8. Peripherals Register Map (continued) Description See page Offset Name Type Reset 0x460 PRI24 RW 0x0000.0000 Interrupt 96-99 Priority 168 0x464 PRI25 RW 0x0000.0000 Interrupt 100-103 Priority 168 0x468 PRI26 RW 0x0000.0000 Interrupt 104-107 Priority 168 0x46C PRI27 RW 0x0000.0000 Interrupt 108-111 Priority 168 0x470 PRI28 RW 0x0000.0000 Interrupt 112-113 Priority 168 0xF00 SWTRIG WO 0x0000.
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Cortex-M4 Peripherals Table 3-8. Peripherals Register Map (continued) Offset Name 0xDB4 0xDB8 Description See page Type Reset MPUBASE3 RW 0x0000.0000 MPU Region Base Address Alias 3 204 MPUATTR3 RW 0x0000.0000 MPU Region Attribute and Size Alias 3 206 Floating-Point Unit (FPU) Registers 0xD88 CPAC RW 0x0000.0000 Coprocessor Access Control 209 0xF34 FPCC RW 0xC000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 Note: This register can only be accessed from privileged mode. The SysTick STCTRL register enables the SysTick features. SysTick Control and Status Register (STCTRL) Base 0xE000.E000 Offset 0x010 Type RW, reset 0x0000.
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Cortex-M4 Peripherals Bit/Field Name Type Reset 1 INTEN RW 0 0 ENABLE RW 0 Description Interrupt Enable Value Description 0 Interrupt generation is disabled. Software can use the COUNT bit to determine if the counter has ever reached 0. 1 An interrupt is generated to the NVIC when SysTick counts to 0. Enable Value Description 0 The counter is disabled. 1 Enables SysTick to operate in a multi-shot way. That is, the counter loads the RELOAD value and begins counting down.
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Tiva™ TM4C129ENCPDT Microcontroller Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 Note: This register can only be accessed from privileged mode. The STRELOAD register specifies the start value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. The start value can be between 0x1 and 0x00FF.FFFF. A start value of 0 is possible but has no effect because the SysTick interrupt and the COUNT bit are activated when counting from 1 to 0.
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Cortex-M4 Peripherals Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 Note: This register can only be accessed from privileged mode. The STCURRENT register contains the current value of the SysTick counter. SysTick Current Value Register (STCURRENT) Base 0xE000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 Register 5: Interrupt 32-63 Set Enable (EN1), offset 0x104 Register 6: Interrupt 64-95 Set Enable (EN2), offset 0x108 Register 7: Interrupt 96-113 Set Enable (EN3), offset 0x10C Note: This register can only be accessed from privileged mode. The ENn registers enable interrupts and show which interrupts are enabled. Bit 0 of EN0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31.
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Cortex-M4 Peripherals Register 8: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 Register 9: Interrupt 32-63 Clear Enable (DIS1), offset 0x184 Register 10: Interrupt 64-95 Clear Enable (DIS2), offset 0x188 Register 11: Interrupt 96-113 Clear Enable (DIS3), offset 0x18C Note: This register can only be accessed from privileged mode. The DISn registers disable interrupts. Bit 0 of DIS0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31.
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Tiva™ TM4C129ENCPDT Microcontroller Register 12: Interrupt 0-31 Set Pending (PEND0), offset 0x200 Register 13: Interrupt 32-63 Set Pending (PEND1), offset 0x204 Register 14: Interrupt 64-95 Set Pending (PEND2), offset 0x208 Register 15: Interrupt 96-113 Set Pending (PEND3), offset 0x20C Note: This register can only be accessed from privileged mode. The PENDn registers force interrupts into the pending state and show which interrupts are pending.
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Cortex-M4 Peripherals Register 16: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 Register 17: Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284 Register 18: Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288 Register 19: Interrupt 96-113 Clear Pending (UNPEND3), offset 0x28C Note: This register can only be accessed from privileged mode. The UNPENDn registers show which interrupts are pending and remove the pending state from interrupts.
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Tiva™ TM4C129ENCPDT Microcontroller Register 20: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 Register 21: Interrupt 32-63 Active Bit (ACTIVE1), offset 0x304 Register 22: Interrupt 64-95 Active Bit (ACTIVE2), offset 0x308 Register 23: Interrupt 96-127 Active Bit (ACTIVE3), offset 0x30C Note: This register can only be accessed from privileged mode. The UNPENDn registers indicate which interrupts are active. Bit 0 of ACTIVE0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31.
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Cortex-M4 Peripherals Register 24: Interrupt 0-3 Priority (PRI0), offset 0x400 Register 25: Interrupt 4-7 Priority (PRI1), offset 0x404 Register 26: Interrupt 8-11 Priority (PRI2), offset 0x408 Register 27: Interrupt 12-15 Priority (PRI3), offset 0x40C Register 28: Interrupt 16-19 Priority (PRI4), offset 0x410 Register 29: Interrupt 20-23 Priority (PRI5), offset 0x414 Register 30: Interrupt 24-27 Priority (PRI6), offset 0x418 Register 31: Interrupt 28-31 Priority (PRI7), offset 0x41C Register 32: Interrupt
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Tiva™ TM4C129ENCPDT Microcontroller Interrupt 0-3 Priority (PRI0) Base 0xE000.E000 Offset 0x400 Type RW, reset 0x0000.
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Cortex-M4 Peripherals Register 40: Interrupt 64-67 Priority (PRI16), offset 0x440 Register 41: Interrupt 68-71 Priority (PRI17), offset 0x444 Register 42: Interrupt 72-75 Priority (PRI18), offset 0x448 Register 43: Interrupt 76-79 Priority (PRI19), offset 0x44C Register 44: Interrupt 80-83 Priority (PRI20), offset 0x450 Register 45: Interrupt 84-87 Priority (PRI21), offset 0x454 Register 46: Interrupt 88-91 Priority (PRI22), offset 0x458 Register 47: Interrupt 92-95 Priority (PRI23), offset 0x45C Register
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Tiva™ TM4C129ENCPDT Microcontroller Interrupt 64-67 Priority (PRI16) Base 0xE000.E000 Offset 0x440 Type RW, reset 0x0000.
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Cortex-M4 Peripherals Register 53: Software Trigger Interrupt (SWTRIG), offset 0xF00 Note: Only privileged software can enable unprivileged access to the SWTRIG register. Writing an interrupt number to the SWTRIG register generates a Software Generated Interrupt (SGI). See Table 2-9 on page 122 for interrupt assignments. When the MAINPEND bit in the Configuration and Control (CFGCTRL) register (see page 182) is set, unprivileged software can access the SWTRIG register.
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Tiva™ TM4C129ENCPDT Microcontroller Register 54: Auxiliary Control (ACTLR), offset 0x008 Note: This register can only be accessed from privileged mode. The ACTLR register provides disable bits for IT folding, write buffer use for accesses to the default memory map, and interruption of multi-cycle instructions. By default, this register is set to provide optimum performance from the Cortex-M4 processor and does not normally require modification. Auxiliary Control (ACTLR) Base 0xE000.
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Cortex-M4 Peripherals Bit/Field Name Type Reset 1 DISWBUF RW 0 Description Disable Write Buffer Value Description 0 No effect. 1 Disables write buffer use during default memory map accesses. In this situation, all bus faults are precise bus faults but performance is decreased because any store to memory must complete before the processor can execute the next instruction. Note: 0 DISMCYC RW 0 This bit only affects write buffers implemented in the Cortex-M4 processor.
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Tiva™ TM4C129ENCPDT Microcontroller Register 55: CPU ID Base (CPUID), offset 0xD00 Note: This register can only be accessed from privileged mode. The CPUID register contains the ARM® Cortex™-M4 processor part number, version, and implementation information. CPU ID Base (CPUID) Base 0xE000.E000 Offset 0xD00 Type RO, reset 0x410F.
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Cortex-M4 Peripherals Register 56: Interrupt Control and State (INTCTRL), offset 0xD04 Note: This register can only be accessed from privileged mode. The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and clear-pending bits for the PendSV and SysTick exceptions.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 27 UNPENDSV WO 0 Description PendSV Clear Pending Value Description 0 On a write, no effect. 1 On a write, removes the pending state from the PendSV exception. This bit is write only; on a register read, its value is unknown. 26 PENDSTSET RW 0 SysTick Set Pending Value Description 0 On a read, indicates a SysTick exception is not pending. On a write, no effect. 1 On a read, indicates a SysTick exception is pending.
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Cortex-M4 Peripherals Bit/Field Name Type Reset Description 19:12 VECPEND RO 0x00 Interrupt Pending Vector Number This field contains the exception number of the highest priority pending enabled exception. The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register.
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Tiva™ TM4C129ENCPDT Microcontroller Register 57: Vector Table Offset (VTABLE), offset 0xD08 Note: This register can only be accessed from privileged mode. The VTABLE register indicates the offset of the vector table base address from memory address 0x0000.0000. Vector Table Offset (VTABLE) Base 0xE000.E000 Offset 0xD08 Type RW, reset 0x0000.
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Cortex-M4 Peripherals Register 58: Application Interrupt and Reset Control (APINT), offset 0xD0C Note: This register can only be accessed from privileged mode. The APINT register provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. To write to this register, 0x05FA must be written to the VECTKEY field, otherwise the write is ignored.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 10:8 PRIGROUP RW 0x0 Description Interrupt Priority Grouping This field determines the split of group priority from subpriority (see Table 3-9 on page 178 for more information). 7:3 reserved RO 0x0 2 SYSRESREQ WO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
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Cortex-M4 Peripherals Register 59: System Control (SYSCTRL), offset 0xD10 Note: This register can only be accessed from privileged mode. The SYSCTRL register controls features of entry to and exit from low-power state. System Control (SYSCTRL) Base 0xE000.E000 Offset 0xD10 Type RW, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1 SLEEPEXIT RW 0 Description Sleep on ISR Exit Value Description 0 When returning from Handler mode to Thread mode, do not sleep when returning to Thread mode. 1 When returning from Handler mode to Thread mode, enter sleep or deep sleep on return from an ISR. Setting this bit enables an interrupt-driven application to avoid returning to an empty main application.
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Cortex-M4 Peripherals Register 60: Configuration and Control (CFGCTRL), offset 0xD14 Note: This register can only be accessed from privileged mode. The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero and unaligned accesses; and access to the SWTRIG register by unprivileged software (see page 170). Configuration and Control (CFGCTRL) Base 0xE000.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 DIV0 RW 0 Description Trap on Divide by 0 This bit enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0. Value Description 3 UNALIGNED RW 0 0 Do not trap on divide by 0. A divide by zero returns a quotient of 0. 1 Trap on divide by 0. Trap on Unaligned Access Value Description 0 Do not trap on unaligned halfword and word accesses.
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Cortex-M4 Peripherals Register 61: System Handler Priority 1 (SYSPRI1), offset 0xD18 Note: This register can only be accessed from privileged mode. The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory management fault exception handlers. This register is byte-accessible. System Handler Priority 1 (SYSPRI1) Base 0xE000.E000 Offset 0xD18 Type RW, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 62: System Handler Priority 2 (SYSPRI2), offset 0xD1C Note: This register can only be accessed from privileged mode. The SYSPRI2 register configures the priority level, 0 to 7 of the SVCall handler. This register is byte-accessible. System Handler Priority 2 (SYSPRI2) Base 0xE000.E000 Offset 0xD1C Type RW, reset 0x0000.
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Cortex-M4 Peripherals Register 63: System Handler Priority 3 (SYSPRI3), offset 0xD20 Note: This register can only be accessed from privileged mode. The SYSPRI3 register configures the priority level, 0 to 7 of the SysTick exception and PendSV handlers. This register is byte-accessible. System Handler Priority 3 (SYSPRI3) Base 0xE000.E000 Offset 0xD20 Type RW, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 64: System Handler Control and State (SYSHNDCTRL), offset 0xD24 Note: This register can only be accessed from privileged mode. The SYSHNDCTRL register enables the system handlers, and indicates the pending status of the usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status of the system handlers. If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as a hard fault.
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Cortex-M4 Peripherals Bit/Field Name Type Reset 16 MEM RW 0 Description Memory Management Fault Enable Value Description 15 SVC RW 0 0 Disables the memory management fault exception. 1 Enables the memory management fault exception. SVC Call Pending Value Description 0 An SVC call exception is not pending. 1 An SVC call exception is pending. This bit can be modified to change the pending status of the SVC call exception.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 10 PNDSV RW 0 Description PendSV Exception Active Value Description 0 A PendSV exception is not active. 1 A PendSV exception is active. This bit can be modified to change the active status of the PendSV exception, however, see the Caution above before setting this bit. 9 reserved RO 0 Software should not rely on the value of a reserved bit.
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Cortex-M4 Peripherals Bit/Field Name Type Reset 0 MEMA RW 0 Description Memory Management Fault Active Value Description 0 Memory management fault is not active. 1 Memory management fault is active. This bit can be modified to change the active status of the memory management fault exception, however, see the Caution above before setting this bit.
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Tiva™ TM4C129ENCPDT Microcontroller Register 65: Configurable Fault Status (FAULTSTAT), offset 0xD28 Note: This register can only be accessed from privileged mode. The FAULTSTAT register indicates the cause of a memory management fault, bus fault, or usage fault. Each of these functions is assigned to a subregister as follows: ■ Usage Fault Status (UFAULTSTAT), bits 31:16 ■ Bus Fault Status (BFAULTSTAT), bits 15:8 ■ Memory Management Fault Status (MFAULTSTAT), bits 7:0 FAULTSTAT is byte accessible.
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Cortex-M4 Peripherals Bit/Field Name Type Reset 25 DIV0 RW1C 0 Description Divide-by-Zero Usage Fault Value Description 0 No divide-by-zero fault has occurred, or divide-by-zero trapping is not enabled. 1 The processor has executed an SDIV or UDIV instruction with a divisor of 0. When this bit is set, the PC value stacked for the exception return points to the instruction that performed the divide by zero.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 17 INVSTAT RW1C 0 Description Invalid State Usage Fault Value Description 0 A usage fault has not been caused by an invalid state. 1 The processor has attempted to execute an instruction that makes illegal use of the EPSR register. When this bit is set, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the Execution Program Status Register (EPSR) register.
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Cortex-M4 Peripherals Bit/Field Name Type Reset 12 BSTKE RW1C 0 Description Stack Bus Fault Value Description 0 No bus fault has occurred on stacking for exception entry. 1 Stacking for an exception entry has caused one or more bus faults. When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 8 IBUS RW1C 0 Description Instruction Bus Error Value Description 0 An instruction bus error has not occurred. 1 An instruction bus error has occurred. The processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction. When this bit is set, a fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it.
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Cortex-M4 Peripherals Bit/Field Name Type Reset 3 MUSTKE RW1C 0 Description Unstack Access Violation Value Description 0 No memory management fault has occurred on unstacking for a return from exception. 1 Unstacking for a return from exception has caused one or more access violations. This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present.
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Tiva™ TM4C129ENCPDT Microcontroller Register 66: Hard Fault Status (HFAULTSTAT), offset 0xD2C Note: This register can only be accessed from privileged mode. The HFAULTSTAT register gives information about events that activate the hard fault handler. Bits are cleared by writing a 1 to them. Hard Fault Status (HFAULTSTAT) Base 0xE000.E000 Offset 0xD2C Type RW1C, reset 0x0000.
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Cortex-M4 Peripherals Register 67: Memory Management Fault Address (MMADDR), offset 0xD34 Note: This register can only be accessed from privileged mode. The MMADDR register contains the address of the location that generated a memory management fault. When an unaligned access faults, the address in the MMADDR register is the actual address that faulted.
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Tiva™ TM4C129ENCPDT Microcontroller Register 68: Bus Fault Address (FAULTADDR), offset 0xD38 Note: This register can only be accessed from privileged mode. The FAULTADDR register contains the address of the location that generated a bus fault. When an unaligned access faults, the address in the FAULTADDR register is the one requested by the instruction, even if it is not the address of the fault.
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Cortex-M4 Peripherals Register 69: MPU Type (MPUTYPE), offset 0xD90 Note: This register can only be accessed from privileged mode. The MPUTYPE register indicates whether the MPU is present, and if so, how many regions it supports. MPU Type (MPUTYPE) Base 0xE000.E000 Offset 0xD90 Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 70: MPU Control (MPUCTRL), offset 0xD94 Note: This register can only be accessed from privileged mode. The MPUCTRL register enables the MPU, enables the default memory map background region, and enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and Fault Mask Register (FAULTMASK) escalated handlers.
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Cortex-M4 Peripherals Bit/Field Name Type Reset 2 PRIVDEFEN RW 0 Description MPU Default Region This bit enables privileged software access to the default memory map. Value Description 0 If the MPU is enabled, this bit disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. 1 If the MPU is enabled, this bit enables use of the default memory map as a background region for privileged software accesses.
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Tiva™ TM4C129ENCPDT Microcontroller Register 71: MPU Region Number (MPUNUMBER), offset 0xD98 Note: This register can only be accessed from privileged mode. The MPUNUMBER register selects which memory region is referenced by the MPU Region Base Address (MPUBASE) and MPU Region Attribute and Size (MPUATTR) registers. Normally, the required region number should be written to this register before accessing the MPUBASE or the MPUATTR register.
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Cortex-M4 Peripherals Register 72: MPU Region Base Address (MPUBASE), offset 0xD9C Register 73: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 Register 74: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC Register 75: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 Note: This register can only be accessed from privileged mode.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 VALID WO 0 Description Region Number Valid Value Description 0 The MPUNUMBER register is not changed and the processor updates the base address for the region specified in the MPUNUMBER register and ignores the value of the REGION field. 1 The MPUNUMBER register is updated with the value of the REGION field and the base address is updated for the region specified in the REGION field. This bit is always read as 0.
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Cortex-M4 Peripherals Register 76: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 Register 77: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 Register 78: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 Register 79: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 Note: This register can only be accessed from privileged mode.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset Description 31:29 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 XN RW 0 Instruction Access Disable Value Description 0 Instruction fetches are enabled. 1 Instruction fetches are disabled. 27 reserved RO 0 Software should not rely on the value of a reserved bit.
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Cortex-M4 Peripherals Bit/Field Name Type Reset 0 ENABLE RW 0 Description Region Enable Value Description 3.7 0 The region is disabled. 1 The region is enabled. Floating-Point Unit (FPU) Register Descriptions This section lists and describes the Floating-Point Unit (FPU) registers, in numerical order by address offset.
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Tiva™ TM4C129ENCPDT Microcontroller Register 80: Coprocessor Access Control (CPAC), offset 0xD88 The CPAC register specifies the access privileges for coprocessors. Coprocessor Access Control (CPAC) Base 0xE000.E000 Offset 0xD88 Type RW, reset 0x0000.
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Cortex-M4 Peripherals Register 81: Floating-Point Context Control (FPCC), offset 0xF34 The FPCC register sets or returns FPU control data. Floating-Point Context Control (FPCC) Base 0xE000.E000 Offset 0xF34 Type RW, reset 0xC000.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 HFRDY RW 0 Description Hard Fault Ready When set, priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated. 3 THREAD RW 0 Thread Mode When set, mode was Thread Mode when the floating-point stack frame was allocated. 2 reserved RO 0 Software should not rely on the value of a reserved bit.
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Cortex-M4 Peripherals Register 82: Floating-Point Context Address (FPCA), offset 0xF38 The FPCA register holds the location of the unpopulated floating-point register space allocated on an exception stack frame. Floating-Point Context Address (FPCA) Base 0xE000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 83: Floating-Point Default Status Control (FPDSC), offset 0xF3C The FPDSC register holds the default values for the Floating-Point Status Control (FPSC) register. Floating-Point Default Status Control (FPDSC) Base 0xE000.E000 Offset 0xF3C Type RW, reset 0x0000.
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JTAG Interface 4 JTAG Interface The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components.
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Tiva™ TM4C129ENCPDT Microcontroller 4.1 Block Diagram Figure 4-1. JTAG Module Block Diagram TCK TMS TAP Controller TDI Instruction Register (IR) BYPASS Data Register TDO Boundary Scan Data Register IDCODE Data Register ABORT Data Register DPACC Data Register APACC Data Register Cortex-M4F Debug Port 4.2 Signal Description The following table lists the external signals of the JTAG/SWD controller and describes the function of each.
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JTAG Interface 4.3 Functional Description A high-level conceptual drawing of the JTAG module is shown in Figure 4-1 on page 215. The JTAG module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel update registers. The TAP controller is a simple state machine controlled by the TCK and TMS inputs. The current state of the TAP controller depends on the sequence of values captured on TMS at the rising edge of TCK.
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Tiva™ TM4C129ENCPDT Microcontroller Note: The following pins are configured as JTAG port pins out of reset. Refer to “General-Purpose Input/Outputs (GPIOs)” on page 750 for information on how to reprogram the configuration of these pins. Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion 4.3.1.
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JTAG Interface 4.3.1.4 Test Data Output (TDO) The TDO pin provides an output stream of serial information from the IR chain or the DR chains. The value of TDO depends on the current TAP state, the current instruction, and the data in the chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin is placed in an inactive drive state when not actively shifting out data.
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Tiva™ TM4C129ENCPDT Microcontroller Figure 4-2. Test Access Port State Machine Test Logic Reset 1 0 Run Test Idle 0 Select DR Scan 1 Select IR Scan 1 0 1 Capture DR 1 Capture IR 0 0 Shift DR Shift IR 0 1 Exit 1 DR Exit 1 IR 1 Pause IR 0 1 Exit 2 DR 0 1 0 Exit 2 IR 1 1 Update DR 4.3.3 1 0 Pause DR 1 0 1 0 0 1 0 0 Update IR 1 0 Shift Registers The Shift Registers consist of a serial shift register chain and a parallel load register.
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JTAG Interface alternate hardware function (AFSEL[3:0] set in the Port C GPIO Alternate Function Select (GPIOAFSEL) register) on the JTAG/SWD pins. See page 778, page 784, page 786, and page 789. It is possible for software to configure these pins as GPIOs after reset by clearing AFSEL[3:0] in the Port C GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or board-level testing, this provides four more GPIOs for use in the design.
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Tiva™ TM4C129ENCPDT Microcontroller 3. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence on the section called “JTAG-to-SWD Switching” on page 221. 4. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence on the section called “SWD-to-JTAG Switching” on page 222. 5. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 6. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 7. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 8.
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JTAG Interface complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD are in their reset states. 2. Send the 16-bit JTAG-to-SWD switch command, 0xE79E, on TMS/SWDIO. 3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already in SWD mode before sending the switch sequence, the SWD goes into the line reset state.
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Tiva™ TM4C129ENCPDT Microcontroller 4.5.1 Instruction Register (IR) The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct states, bits can be shifted into the IR. Once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. The decode of the IR bits is shown in Table 4-3.
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JTAG Interface 4.5.1.3 ABORT Instruction The ABORT instruction connects the associated ABORT Data Register chain between TDI and TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates a DAP abort of a previous request. See the “ABORT Data Register” on page 226 for more information. 4.5.1.
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Tiva™ TM4C129ENCPDT Microcontroller The major uses of the JTAG port are for manufacturer testing of component assembly and program development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE instruction outputs a value of 0x4BA0.0477. This value allows the debuggers to automatically configure themselves to work correctly with the Cortex-M4F during debug. Figure 4-3. IDCODE Register Format 31 TDI 4.5.2.
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JTAG Interface 4.5.2.5 DPACC Data Register The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. 4.5.2.6 ABORT Data Register The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification.
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Tiva™ TM4C129ENCPDT Microcontroller 5 System Control System control configures the overall operation of the device and provides information about the device. Configurable features include reset control, NMI operation, power control, clock control, and low-power modes. 5.1 Signal Description The following table lists the external signals of the System Control module and describes the function of each. The NMI signal is the alternate function for two GPIO signals, which default to GPIO after reset.
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System Control Timer Peripheral Present (PPWD) register, provide information on how many of each type of module are included on the device. Finally, information about the capabilities of the on-chip peripherals are provided at offset 0xFC0 in each peripheral's register space in the Peripheral Properties registers, such as the GPTM Peripheral Properties (GPTMPP).
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Tiva™ TM4C129ENCPDT Microcontroller Table 5-2.
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System Control 2. The internal reset is released and the core executes a full initialization of the device. Upon completion, the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The internal POR is only active on the initial power-up of the microcontroller, when the microcontroller wakes from hibernation, and when the VDD supply drops below the its defined operating limit.
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Tiva™ TM4C129ENCPDT Microcontroller Figure 5-1. Basic RST Configuration VDD Tiva™ Microcontroller RPU RST Note: RPU = 0 to 100 kΩ Figure 5-2. External Circuitry to Extend Power-On Reset VDD Tiva™ Microcontroller RPU RST C1 Note: RPU = 1 kΩ to 100 kΩ C1 = 1 nF to 10 µF Figure 5-3. Reset Circuit Controlled by Switch VDD Tiva™ Microcontroller RPU RST C1 Note: RS Typical RPU = 10 kΩ Typical RS = 470 Ω C1 = 10 nF 5.2.2.
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System Control The application can identify the type of BOR event that occurred by reading the Power-Temperature Cause (PWRTC) register. The BOR detection circuits can be programmed to generate a reset, System Control interrupt, or NMI in the Power-Temp Brown Out Control (PTBOCTL) register. The default settings at reset are as follows: ■ VDDA under BOR detection default setting is for no action to occur. ■ VDD under BOR detection default setting is to execute a full POR.
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Tiva™ TM4C129ENCPDT Microcontroller 3. The internal reset is released and the microcontroller fetches and loads the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. The result of a brown-out reset is equivalent to that of an assertion of the external RST input, and the reset is held active until the proper voltage level is restored.
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System Control generation has been enabled through the RESEN bit in the Watchdog Control Register (WDTCTL), the watchdog timer asserts its reset signal to the microcontroller. The reset generated can be a full Power-On Reset or a system reset depending on the value programmed in WDOGn bit field of the Reset Behavior Control Register (RESBEHAVCTL).
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Tiva™ TM4C129ENCPDT Microcontroller 5.2.2.9 HSSR Reset The Hardware System Service Request (HSSR) register can be used to restore the device back to factory settings. A successful write to the Hardware System Service Request (HSSR) register initiates a system reset. The reset initialization process executes before examining the HSSR register and processing the command. This register can only be accessed in privileged mode.
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System Control which action occurs. In either case, the system clock source is automatically switched to the PIOSC. If a MOSC failure reset occurs, the NMI handler is used to address the main oscillator verification failure because the necessary code can be removed from the general reset handler, speeding up reset processing. The detection circuit is enabled by setting the CVAL bit in the Main Oscillator Control (MOSCCTL) register.
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Tiva™ TM4C129ENCPDT Microcontroller 5.2.5 Clock Control The system control module determines the control of clocks in this part. 5.2.5.1 Fundamental Clock Sources There are multiple clock sources for use in the microcontroller. The Run and Sleep Mode Configuration Register (RSCLKCFG) can be used to configure the required clock source for the device after Power-On Reset, as well as the system clock divisor encodings. The available clock sources are as follows: ■ Precision Internal Oscillator (PIOSC).
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System Control The internal system clock (SysClk), is derived from any of the above sources. An internal PLL can also be used by the PIOSC or MOSC clock to generate the system clock and peripheral clocks. Table 5-3 on page 238 shows how the various clock sources can be used in a system. Table 5-3.
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Tiva™ TM4C129ENCPDT Microcontroller Note: The clock sources in Figure 5-5 include a superset of peripherals available in the family. Some peripheral clock sources may not be present on your specific device.
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System Control Figure 5-5.
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Tiva™ TM4C129ENCPDT Microcontroller Peripheral Clock Sources In addition to the main clock tree described above, the ADC, USB, Ethernet, PWM, UART, and QSSI all have a Clock Control register in their register map at offset 0xFC8 that can be used to control the clock generation for the module. ADC Clock Control The ADC digital block is clocked by the system clock and the ADC analog block is clocked from a separate conversion clock (ADC clock).
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System Control ■ The PHY receives the main oscillator (MOSC) which must be 25 MHz ± 50 ppm for proper operation. The MOSC source can be a single-ended source or a crystal. PWM Clock Control The PWMCC register can be used to select the System Clock as the PWM clock source or a divided System Clock. For more information, see page 1871.
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Tiva™ TM4C129ENCPDT Microcontroller 5.2.5.3 Precision Internal Oscillator Operation (PIOSC) The microcontroller powers up with the PIOSC running. If another clock source is desired, the PIOSC must remain enabled because it is used for internal functions. The PIOSC can only be disabled during Deep-Sleep mode. It can be powered down by setting the PIOSCPD bit in the DSCLKCFG register. The PIOSC generates a 16-MHz clock with a ±FPIOSC accuracy (see Table 30-19 on page 1961).
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System Control ■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output. The modes are programmed using the PLLPWR bit in the PLLFREQ0 register (see page 299). PLL Configuration The PLL is disabled by default during power-on reset and is enabled later by software if required. Software specifies the output divisor to set the system clock frequency and enables the PLL to drive the output. The PLL is controlled using the PLLFREQ0, PLLFREQ1 and PLLSTAT registers.
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Tiva™ TM4C129ENCPDT Microcontroller If the main oscillator provides the clock reference to the PLL, the translation provided by hardware and used to program the PLL is available for software in the PLL Frequency n (PLLFREQn) registers (see page 299). The internal translation provides a translation within ± 1% of the targeted PLL VCO frequency. Table 5-7 on page 245 shows the actual PLL frequency and error for a given crystal choice.
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System Control Hardware is provided to keep the PLL from being used as a system clock until the TREADY condition is met after one of the two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator) before the RSCLKCFG register is re-programmed to enable the PLL.
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Tiva™ TM4C129ENCPDT Microcontroller Hibernation Module Low-Frequency Oscillator (HIBLFIOSC). If this clock source is selected, it has to be enabled in the Hibernation Module as well. The selection of these alternate sources is through the OSCSRC field in the RSCLKCFG register. 5.2.6.2 Sleep Mode In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor and the memory subsystem are not clocked and therefore no longer execute code.
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System Control For further power savings the PIOSC can be disabled through the PIOSCPD bit in the DSCLKCFG register. When the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep duration. If the PIOSC is used as the PLL reference clock source, it may continue to provide the clock during Deep-Sleep. See page 288.
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Tiva™ TM4C129ENCPDT Microcontroller Figure 5-6. Module Clock Selection Clock Control Register PIOSC or ALTCLK 1 Baud Clock 0 Deep Sleep 1 Module Clock 0 System Clock Additional power management modes are available that lower the power consumption of the peripheral memory, Flash, and SRAM memory. However, the lower power consumption modes have slower deep-sleep and wake-up times. Note: 5.2.6.
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System Control ■ LDO Deep-Sleep Power Calibration (LDODPCAL): Provides factory recommendations for the LDO value in Deep-Sleep mode ■ Sleep Power Configuration (SLPPWRCFG): Controls the power saving modes for Flash memory and SRAM in Sleep mode ■ Deep-Sleep Power Configuration (DSLPPWRCFG): Controls the power saving modes for Flash memory and SRAM in Deep-Sleep mode ■ Deep-Sleep Clock Configuration (DSCLKCFG): Controls the clocking in Deep-Sleep mode ■ Sleep / Deep-Sleep Power Mode Status (SDPMST): Provide
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Tiva™ TM4C129ENCPDT Microcontroller LDO Power Control Note: While the device is connected through JTAG, the LDO control settings for Sleep or Deep-Sleep are not available and will not be applied. Software can configure the LDOSPCTL register (see page 307) and/or the LDODPCTL register (see page 310) to dynamically raise or lower the LDO voltage in Sleep and Deep-Sleep mode depending on whether an increase in performance or reduction in power consumption is required.
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System Control ■ The SRAM can be put into standby or low power mode. For typical power consumption and sleep/wake-up times, refer to “Current Consumption ” on page 2004 and “Sleep Modes” on page 1967. The SDPMST register provides results on the Dynamic Power Management command issued. It also has some real time status that can be viewed by a debugger or the core if it is running. These events do not trigger an interrupt and are meant to provide information to help tune software for power management.
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Tiva™ TM4C129ENCPDT Microcontroller ■ Data 1 (32 bits) = 0x0201.0100 ■ Data 2 (32 bits) = 0x0D08.0503 ■ Data 3 (32 bits) = 0x5937.2215 If the data bytes are correct, then the device is returned to factory condition. During the return-to-factory settings function, the following events occur: ■ The RAM is erased in the Hibernation module ■ The system SRAM is erased ■ The FMPPEn registers are set to 0xFFFF.
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System Control If it is necessary to keep the MOSC powered on during automatic (deep-sleep) or accidental power down, then the MOSCDPD bit should be set to 0x1. Otherwise, if the MOSCDPD bit is set to 0x0, the MOSC is powered off when deep-sleep is entered or automatic power down occurs. The following table describes the relationship between the PWRDN bit in the MOSCCTL register and the MOSCDPD bit in the DSCLKCFG register: Table 5-10.
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Tiva™ TM4C129ENCPDT Microcontroller Table 5-11. System Control Register Map (continued) Offset Name 0x050 Description See page Type Reset RIS RO 0x0000.0000 Raw Interrupt Status 268 0x054 IMC RW 0x0000.0000 Interrupt Mask Control 270 0x058 MISC RW1C 0x0000.0000 Masked Interrupt Status and Clear 272 0x05C RESC RW 0x0000.0002 Reset Cause 274 0x060 PWRTC RW1C 0x0000.0000 Power-Temperature Cause 277 0x064 NMIC RW 0x0000.
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System Control Table 5-11. System Control Register Map (continued) Offset Name 0x28C See page Type Reset Description EMACMPC RW 0x0000.0003 Ethernet MAC Memory Power Control 322 0x298 CAN0PDS RO 0x0000.003F CAN 0 Power Domain Status 323 0x29C CAN0MPC RW 0x0000.0003 CAN 0 Memory Power Control 324 0x2A0 CAN1PDS RO 0x0000.003F CAN 1 Power Domain Status 325 0x2A4 CAN1MPC RW 0x0000.0003 CAN 1 Memory Power Control 326 0x300 PPWD RO 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Table 5-11. System Control Register Map (continued) Offset Name 0x39C Description See page Type Reset PPEMAC RO 0x0000.0001 Ethernet MAC Peripheral Present 358 0x3A0 PPPRB RO 0x0000.0000 Power Regulator Bus Peripheral Present 359 0x3A4 PPHIM RO 0x0000.0000 Human Interface Master Peripheral Present 360 0x500 SRWD RW 0x0000.0000 Watchdog Timer Software Reset 361 0x504 SRTIMER RW 0x0000.
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System Control Table 5-11. System Control Register Map (continued) Offset Name 0x61C See page Type Reset Description RCGCSSI RW 0x0000.0000 Synchronous Serial Interface Run Mode Clock Gating Control 397 0x620 RCGCI2C RW 0x0000.0000 Inter-Integrated Circuit Run Mode Clock Gating Control 398 0x628 RCGCUSB RW 0x0000.0000 Universal Serial Bus Run Mode Clock Gating Control 400 0x630 RCGCEPHY RW 0x0000.0000 Ethernet PHY Run Mode Clock Gating Control 401 0x634 RCGCCAN RW 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Table 5-11. System Control Register Map (continued) Offset Name 0x740 Description See page Type Reset SCGCPWM RW 0x0000.0000 Pulse Width Modulator Sleep Mode Clock Gating Control 429 0x744 SCGCQEI RW 0x0000.0000 Quadrature Encoder Interface Sleep Mode Clock Gating Control 430 0x758 SCGCEEPROM RW 0x0000.0000 EEPROM Sleep Mode Clock Gating Control 431 0x774 SCGCCCM RW 0x0000.
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System Control Table 5-11. System Control Register Map (continued) See page Offset Name Type Reset Description 0x900 PCWD RW 0x0000.0003 Watchdog Timer Power Control 458 0x904 PCTIMER RW 0x0000.00FF 16/32-Bit General-Purpose Timer Power Control 460 0x908 PCGPIO RW 0x0000.7FFF General-Purpose Input/Output Power Control 463 0x90C PCDMA RW 0x0000.0001 Micro Direct Memory Access Power Control 468 0x910 PCEPI RW 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Table 5-11. System Control Register Map (continued) Offset Name 0xA38 Description See page Type Reset PRADC RO 0x0000.0000 Analog-to-Digital Converter Peripheral Ready 522 0xA3C PRACMP RO 0x0000.0000 Analog Comparator Peripheral Ready 523 0xA40 PRPWM RO 0x0000.0000 Pulse Width Modulator Peripheral Ready 524 0xA44 PRQEI RO 0x0000.0000 Quadrature Encoder Interface Peripheral Ready 525 0xA58 PREEPROM RO 0x0000.
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System Control Register 1: Device Identification 0 (DID0), offset 0x000 This register identifies the version of the microcontroller. Each microcontroller is uniquely identified by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1 register. The MAJOR and MINOR bit fields indicate the die revision number. Combined, the MAJOR and MINOR bit fields indicate the part revision number.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 15:8 MAJOR RO - Description Major Revision This field specifies the major revision number of the microcontroller. The major revision reflects changes to base layers of the design. The major revision number is indicated in the part number as a letter (A for first revision, B for second, and so on).
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System Control Register 2: Device Identification 1 (DID1), offset 0x004 This register identifies the device family, part number, temperature range, pin count, and package type. Each microcontroller is uniquely identified by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1 register. Device Identification 1 (DID1) Base 0x400F.E000 Offset 0x004 Type RO, reset 0x102D.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 15:13 PINCOUNT RO 0x6 Description Package Pin Count This field specifies the number of pins on the device package.
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System Control Register 3: Power-Temp Brown Out Control (PTBOCTL), offset 0x038 This register determines, based on an individual event level, the appropriate next level of action (for example, NONE, System Control Interrupt, NMI, or reset) when an event occurs. Power-temperature event actions are directed to the core as a System Control Interrupt or NMI. When a reset occurs, its behavior is controlled by the Reset Behavior Control (RESBEHAVCTL) register.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1:0 VDD_UBOR RW 0x3 Description VDD under BOR Event Action An event occurs when VDD trips under the VDD_BOR threshold found in Table 30-13 on page 1950. This field determines the action to take on the event.
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System Control Register 4: Raw Interrupt Status (RIS), offset 0x050 This register indicates the status for system control raw interrupts. An interrupt is sent to the interrupt controller if the corresponding bit in the Interrupt Mask Control (IMC) register is set. Writing a 1 to the corresponding bit in the Masked Interrupt Status and Clear (MISC) register clears an interrupt status bit. Raw Interrupt Status (RIS) Base 0x400F.E000 Offset 0x050 Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3 MOFRIS RO 0 Description Main Oscillator Failure Raw Interrupt Status Value Description 0 The main oscillator has not failed. 1 The MOSCIM bit in the MOSCCTL register is set and the main oscillator has failed. This bit is cleared by writing a 1 to the MOFMIS bit in the MISC register. 2 reserved RO 0 Software should not rely on the value of a reserved bit.
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System Control Register 5: Interrupt Mask Control (IMC), offset 0x054 This register contains the mask bits for system control raw interrupts. A raw interrupt, indicated by a bit being set in the Raw Interrupt Status (RIS) register, is sent to the interrupt controller if the corresponding bit in this register is set. Interrupt Mask Control (IMC) Base 0x400F.E000 Offset 0x054 Type RW, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3 MOFIM RW 0 Description Main Oscillator Failure Interrupt Mask Value Description 0 The MOFRIS interrupt is suppressed and not sent to the interrupt controller. 1 An interrupt is sent to the interrupt controller when the MOFRIS bit in the RIS register is set. 2 reserved RO 0 Software should not rely on the value of a reserved bit.
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System Control Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 On a read, this register gives the current masked status value of the corresponding interrupt in the Raw Interrupt Status (RIS) register. All of the bits are RW1C, thus writing a 1 to a bit clears the corresponding raw interrupt bit in the RIS register (see page 268). Masked Interrupt Status and Clear (MISC) Base 0x400F.E000 Offset 0x058 Type RW1C, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 5:4 reserved RO 0x0 3 MOFMIS RW1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Main Oscillator Failure Masked Interrupt Status Value Description 0 When read, a 0 indicates that the main oscillator has not failed. A write of 0 has no effect on the state of this bit.
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System Control Register 7: Reset Cause (RESC), offset 0x05C This register is set with the reset cause after reset. The bits in this register are sticky and maintain their state across multiple reset sequences. If a full POK-POR is initiated, the POR bit in the RESC register is set and all other bits are cleared. If the WDOGn, BOR or EXTRES configuration fields are set to 0x3 in the RESBEHAVCTL register and a simulated POR is initiated, the cause of the reset is reflected in the RESC register.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 12 HSSR RW - Description HSSR Reset Value Description 0 When read, this bit indicates that a HSSR request has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. 1 When read, this bit indicates that a HSSR request has generated a reset. 11:6 reserved RO 0 Software should not rely on the value of a reserved bit.
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System Control Bit/Field Name Type Reset 2 BOR RW 0 Description Brown-Out Reset Note that for this bit, the BOR event that causes the Brown-Out Reset can be any of the following: ■ The VDD supply drops below its acceptable operating range. ■ The VDDA supply drops below its acceptable operating range. Value Description 0 When read, this bit indicates that a brown-out reset has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it.
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Tiva™ TM4C129ENCPDT Microcontroller Register 8: Power-Temperature Cause (PWRTC), offset 0x060 This register provides detailed information on the power subsystem event that caused a reset or interrupt. The event sets the condition in this register without regard to whether it is used to generate a System control Interrupt, Reset, NMI, or no action. The PTBOCTL register contains the action to be taken on the specific events.
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System Control Register 9: NMI Cause Register (NMIC), offset 0x064 This register provides the detailed information on the cause of an NMI interrupt. These bits are set via hardware when the event occurs AND the higher level control indicates that it should be NMI event. Note: The NMIC register has to be cleared by the following sequence: 1. Read the NMIC register to identify the source of the NMI. 2. Clear the source of the NMI. 3. Read the NMIC register again to check the status. 4.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 9 TAMPER RW 0 Description Tamper Event NMI Value Description 0 No tamper event has occurred. 1 An NMI has occurred due to a tamper event See the HIB module tamper registers for more details on the tamper event. 8:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
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System Control Register 10: Main Oscillator Control (MOSCCTL), offset 0x07C This register provides control over the features of the main oscillator, including the ability to enable the MOSC clock verification circuit, what action to take when the MOSC fails, and whether or not a crystal is connected. When enabled, this circuit monitors the frequency of the MOSC to verify that the oscillator is operating within specified limits.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 2 NOXTAL RW 1 Description No MOSC/Crystal Connected Provides the user control over the power drawn from the main oscillator circuit. This bit should be set when either crystal or single-ended mode is being used. If the application needs MOSC, this bit should be cleared.
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System Control Register 11: Run and Sleep Mode Configuration Register (RSCLKCFG), offset 0x0B0 Important: When transitioning the system clock configuration to use the MOSC as the fundamental clock source, the PWRDN bit must be set in the MOSCCTL register prior to reselecting the MOSC for proper operation. Run and Sleep Mode Configuration Register (RSCLKCFG) Base 0x400F.E000 Offset 0x0B0 Type RW, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 28 USEPLL RW 0 Description Use PLL This bit controls whether the clock source is specified by the OSCSRC field or the output of the PLL is provided to the system clock divider and serves as the system clock source. Value Description 27:24 PLLSRC RW 0 0 Clock source specified by OSCSRC field.
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System Control Register 12: Memory Timing Parameter Register 0 for Main Flash and EEPROM (MEMTIM0), offset 0x0C0 The MEMTIM0 register provides timing parameters for the main Flash and EEPROM memories. The timing parameters apply to the memory while the system is in run or sleep mode; the clocking for these modes is consistent and unchanged since the system clock frequency and source remains unchanged during transitions between run-to-sleep and sleep-back-to-run.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 25:22 EBCHT RW 0x0 Description EEPROM Clock High Time Specifies the length of the EEPROM bank clock high time Value Description 21 EBCE RW 1 0x0 1/2 system clock period 0x1 1 system clock period 0x2 1.5 system clock periods 0x3 2 system clock periods 0x4 2.5 system clock periods 0x5 3 system clock periods 0x6 3.5 system clock periods 0x7 4 system clock periods 0x8 4.
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System Control Bit/Field Name Type Reset 9:6 FBCHT RW 0x0 Description Flash Bank Clock High Time Specifies the length of the flash bank clock high time Value Description 5 FBCE RW 1 0x0 1/2 system clock period 0x1 1 system clock period 0x2 1.5 system clock periods 0x3 2 system clock periods 0x4 2.5 system clock periods 0x5 3 system clock periods 0x6 3.5 system clock periods 0x7 4 system clock periods 0x8 4.
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Tiva™ TM4C129ENCPDT Microcontroller Register 13: Alternate Clock Configuration (ALTCLKCFG), offset 0x138 The ALTCLKCFG register specifies the alternate clock source used by many of the peripherals. Alternate Clock Configuration (ALTCLKCFG) Base 0x400F.E000 Offset 0x138 Type RW, reset 0x0000.
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System Control Register 14: Deep Sleep Clock Configuration Register (DSCLKCFG), offset 0x144 The DSCLKCFG register specifies the behavior of the clock system while in deep sleep. Note that the MOSCDPD bit not only affects deep-sleep mode, but all other modes as well depending on the value of the bit. Please refer to the following table when programming this bit: Table 5-13.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 31 PIOSCPD RW 0 Description PIOSC Power Down Value Description 30 MOSCDPD RW 0 0 The PIOSC is active during deep sleep mode. 1 The PIOSC is disabled during sleep mode for additional power savings. MOSC Disable Power Down This bit inhibits the MOSC from automatic or accidental power down.
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System Control Bit/Field Name Type Reset 9:0 DSSYSDIV RW 0x0 Description Deep Sleep Clock Divisor This field specifies the system clock divisor value during deep sleep mode. The clock source selected by DSOSCSRC is divided by DSSYSDIV + 1: fSYSCLK=fOSCCLK/(DSSYSDIV + 1) Note: Values 0x0 and 0x1 should not be used.
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Tiva™ TM4C129ENCPDT Microcontroller Register 15: Divisor and Source Clock Configuration (DIVSCLK), offset 0x148 The DIVSCLK register specifies the source and divisor of the DIVSCLK reference clock output. This signal can be used as a clock source to an external device but bears no timing relationship to other signals. Note: The DIVSCLK signal output is not synchronized to the System Clock. Divisor and Source Clock Configuration (DIVSCLK) Base 0x400F.E000 Offset 0x148 Type RW, reset 0x0000.
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System Control Bit/Field Name Type Reset 7:0 DIV RW 0 Description Divisor Value This field controls the ratio of the source clock to the output clock. The output clock frequency is equal to the source clock frequency divided by the DIV field value plus 1. Value Description 0x0 Divided by 1 0x1 Divided by 2 .... ......
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Tiva™ TM4C129ENCPDT Microcontroller Register 16: System Properties (SYSPROP), offset 0x14C This register provides information on whether certain System Control properties are present on the microcontroller. System Properties (SYSPROP) Base 0x400F.E000 Offset 0x14C Type RO, reset 0x0003.
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System Control Bit/Field Name Type Reset 11 SRAMSM RO 0x1 Description SRAM Sleep/Deep-Sleep Standby Mode Present This bit determines whether the SRAMPM field in the SLPPWRCFG and DSLPPWRCFG registers can be configured to put the SRAM into Standby mode while in Sleep or Deep-Sleep mode. Value Description 10 SRAMLPM RO 0x1 0 A value of 0x1 in the SRAMPM fields is ignored. 1 The SRAMPM fields can be configured to put the SRAM into Standby mode while in Sleep or Deep-Sleep mode.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4:1 reserved RO 0 0 FPU RO 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. FPU Present This bit indicates if the FPU is present in the Cortex-M4 core. Value Description 0 FPU is not present. 1 FPU is present.
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System Control Register 17: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 This register provides the ability to update or recalibrate the precision internal oscillator. Note that a 32.768-kHz oscillator must be used as the Hibernation module clock source for the user to be able to calibrate the PIOSC. Precision Internal Oscillator Calibration (PIOSCCAL) Base 0x400F.E000 Offset 0x150 Type RW, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 6:0 UT RW 0x0 Description User Trim Value User trim value that can be loaded into the PIOSC.
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System Control Register 18: Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 This register provides the user information on the PIOSC calibration. Note that a 32.768-kHz oscillator must be used as the Hibernation module clock source for the user to be able to calibrate the PIOSC. Precision Internal Oscillator Statistics (PIOSCSTAT) Base 0x400F.E000 Offset 0x154 Type RO, reset 0x0040.
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Tiva™ TM4C129ENCPDT Microcontroller Register 19: PLL Frequency 0 (PLLFREQ0), offset 0x160 This register always contains the variables used to configure the PLL. If the PLL is reprogrammed, it must go through a relock sequence which is defined by the parameter TREADY in Table 30-16 on page 1959. When controlling this register directly, software must change this value while the PLL is powered down.
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System Control Register 20: PLL Frequency 1 (PLLFREQ1), offset 0x164 This register always contains the current Q and N values presented to the system PLL. If the PLL is reconfigured, it must go through a relock sequence which takes about 128 PIOSC clocks. When controlling this register directly, software must change this value while the PLL is powered down. Writes to PLLFREQ0 are delayed from affecting the PLL until the RSCLKCFG register NEWFREQ bit is written with a 1.
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Tiva™ TM4C129ENCPDT Microcontroller Register 21: PLL Status (PLLSTAT), offset 0x168 This register shows the direct status of the PLL lock. PLL Status (PLLSTAT) Base 0x400F.E000 Offset 0x168 Type RO, reset 0x0000.
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System Control Register 22: Sleep Power Configuration (SLPPWRCFG), offset 0x188 This register provides configuration information for the power control of the SRAM and Flash memory while in Sleep mode. Sleep Power Configuration (SLPPWRCFG) Base 0x400F.E000 Offset 0x188 Type RW, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1:0 SRAMPM RW 0x0 Description SRAM Power Modes This field controls the low power modes of the on-chip SRAM , including the USB SRAM while the microcontroller is in Sleep mode. Value Description 0x0 Active Mode SRAM is not placed in a lower power mode. This mode provides the fastest time to sleep and wakeup but the highest power consumption while the microcontroller is in Sleep mode.
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System Control Register 23: Deep-Sleep Power Configuration (DSLPPWRCFG), offset 0x18C This register provides configuration information for the power control of the SRAM and Flashmemory while in Deep-Sleep mode. Deep-Sleep Power Configuration (DSLPPWRCFG) Base 0x400F.E000 Offset 0x18C Type RW, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 5:4 FLASHPM RW 0x0 Description Flash Power Modes This field enables the Flash to be placed in a Low Power Mode. Refer to “Sleep Modes” on page 1967 for information regarding wake times from Sleep and Deep-Sleep. If using the LFIOSC as the Deep-Sleep clock source, FLASHPM = 0x2 must be used. If FLASHPM = 0x0 and the LFIOSC is used, current could be higher and could vary.
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System Control Register 24: Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 This register is predefined by the part and can be used to verify features. Non-Volatile Memory Information (NVMSTAT) Base 0x400F.E000 Offset 0x1A0 Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 25: LDO Sleep Power Control (LDOSPCTL), offset 0x1B4 This register specifies the LDO output voltage in Sleep mode. This register should be configured while in Run Mode. If the VADJEN bit is set, writes can be made to the VLDO field within the provided encodings. The following table shows the maximum clock frequencies with respect to LDO Voltage. Table 5-14.
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System Control Bit/Field Name Type Reset Description 7:0 VLDO RW 0x18 LDO Output Voltage This field provides program control of the LDO output voltage in Sleep mode. The value of the field is only used for the LDO voltage when the VADJEN bit is set. Value Description 0x12 0.90 V 0x13 0.95 V 0x14 1.00 V 0x15 1.05 V 0x16 1.10 V 0x17 1.15 V 0x18 1.20 V 0x19 - 0xFF reserved Note: When using the USB module, the LDO must be configured to 1.2 V.
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Tiva™ TM4C129ENCPDT Microcontroller Register 26: LDO Sleep Power Calibration (LDOSPCAL), offset 0x1B8 This register provides factory determined values that are recommended for the VLDO field in the LDOSPCTL register while in Sleep mode. The reset value of this register cannot be determined until the product has been characterized. LDO Sleep Power Calibration (LDOSPCAL) Base 0x400F.E000 Offset 0x1B8 Type RO, reset 0x0000.
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System Control Register 27: LDO Deep-Sleep Power Control (LDODPCTL), offset 0x1BC This register specifies the LDO output voltage in Sleep mode. This register should be configured while in Run Mode. If the VADJEN bit is set, writes can be made to the VLDO field within the provided encodings. The following table shows the maximum clock frequencies with respect to LDO Voltage. Table 5-15.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset Description 7:0 VLDO RW 0x12 LDO Output Voltage This field provides program control of the LDO output voltage in Deep-Sleep mode. The value of the field is only used for the LDO voltage when the VADJEN bit is set. Value Description 0x12 0.90 V 0x13 0.95 V 0x14 1.00 V 0x15 1.05 V 0x16 1.10 V 0x17 1.15 V 0x18 1.
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System Control Register 28: LDO Deep-Sleep Power Calibration (LDODPCAL), offset 0x1C0 This register provides factory determined values that are recommended for the VLDO field in the LDODPCTL register while in Deep-Sleep mode. The reset value of this register cannot be determined until the product has been characterized. LDO Deep-Sleep Power Calibration (LDODPCAL) Base 0x400F.E000 Offset 0x1C0 Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 29: Sleep / Deep-Sleep Power Mode Status (SDPMST), offset 0x1CC This register provides status information on the Sleep and Deep-Sleep power modes as well as some real time status that can be viewed by a debugger or the core if it is running. These events do not trigger an interrupt and are meant to provide information that can help tune software for power management.
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System Control Bit/Field Name Type Reset 16 PRACT RO 0 Description Sleep or Deep-Sleep Power Request Active Value Description 15:8 reserved RO 0x00 7 PPDW RO 0 0 A power request is not active. 1 The microcontroller is currently in Deep-Sleep mode or is in Sleep mode and a request to put the SRAM and/or Flash memory into a lower power mode is currently active as configured by the SLPPWRCFG register. Software should not rely on the value of a reserved bit.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3 LDMINERR RO 0 Description VLDO Value Below Minimum Error in Deep-Sleep Mode Value Description 0 No error. 1 An error has occurred because software has requested that the LDO voltage be below the minimum value allowed using the VLDO bit in the LDODPCTL register. In this situation, the LDO voltage is not changed when entering Deep-Sleep mode. 2 PPDERR RO 0 PIOSC Power Down Request Error Value Description 0 No error.
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System Control Register 30: Reset Behavior Control Register (RESBEHAVCTL), offset 0x1D8 The Reset Behavior Control Register contains system management controls. The RESBEHAVCTL register effect occurs immediately when the register is changed. The next power-on reset sequence returns the reset value. If any bit field below is set to 0x3 when a reset occurs, a simulated POR will be generated and the appropriate reset cause will be set in the Reset Cause (RESC) register.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3:2 BOR RW 0x3 Description BOR Reset operation This field defines operation of BOR when the USER has defined the BOR operation to be a reset. Note: Value If the BOR operation is defined as an interrupt, this setting has no effect. Description 0x0 - 0x1 Reserved. Default operation is performed. 1:0 EXTRES RW 0x3 0x2 Brown Out Reset issues system reset. 0x3 Brown Out Reset issues a simulated POR sequence (default).
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System Control Register 31: Hardware System Service Request (HSSR), offset 0x1F4 The HSSR register is used to control system configuration functions, such as Return-to-Factory settings. A write to the HSSR register stores a command descriptor pointer (CDOFF) value if the KEY field is correct (0xCA). A successful write to this register also initiates a system reset. The initialization process executes before examining the HSSR register and processing the command.
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Tiva™ TM4C129ENCPDT Microcontroller Register 32: USB Power Domain Status (USBPDS), offset 0x280 This register provides the status of power to the USB SRAM memory array. Note: If the USBMPC register's PWRCTL field is set to 0x3 and the power domain to the USB is turned off by writing a 0 to the P0 bit of the PCUSB register, then the SRAM memory goes into retention and the MEMSTAT field of the USBPDS register reads as 0x1 (retention). USB Power Domain Status (USBPDS) Base 0x400F.
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System Control Register 33: USB Memory Power Control (USBMPC), offset 0x284 This register provides power control to the peripheral memory array. Note: If the USBMPC register's PWRCTL field is set to 0x3 and the power domain to the USB is turned off by writing a 0 to the P0 bit of the PCUSB register, then the SRAM memory goes into retention and the MEMSTAT field of the USBPDS register reads as 0x1 (retention). USB Memory Power Control (USBMPC) Base 0x400F.E000 Offset 0x284 Type RW, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 34: Ethernet MAC Power Domain Status (EMACPDS), offset 0x288 This register provides the status of power to the EMAC SRAM memory array. Note: The EMAC memory array does not support retention and can only be turned ON and OFF. Memory array OFF is supported only when the power domain is off.
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System Control Register 35: Ethernet MAC Memory Power Control (EMACMPC), offset 0x28C This register provides power control to the peripheral memory array. Note: The EMAC memory array does not support retention and can only be turned ON and OFF. Memory array OFF is supported only when the power domain is off.
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Tiva™ TM4C129ENCPDT Microcontroller Register 36: CAN 0 Power Domain Status (CAN0PDS), offset 0x298 This register provides the status of power to the CAN0 SRAM memory array. Note: The CAN0 memory array does not support retention and can only be turned ON and OFF.
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System Control Register 37: CAN 0 Memory Power Control (CAN0MPC), offset 0x29C This register provides power control to the peripheral memory array. Note: The CAN0 memory array does not support retention and can only be turned ON and OFF.
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Tiva™ TM4C129ENCPDT Microcontroller Register 38: CAN 1 Power Domain Status (CAN1PDS), offset 0x2A0 This register provides the status of power to the CAN 1 SRAM memory array. Note: The CAN1 memory array does not support retention and can only be turned ON and OFF.
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System Control Register 39: CAN 1 Memory Power Control (CAN1MPC), offset 0x2A4 This register provides power control to the peripheral memory array. Note: The CAN1 memory array does not support retention and can only be turned ON and OFF. If the memory array is currently turned on (PWRCTL = 0x3) and the power control to CAN1 is subsequently removed by clearing the P1 bit of the PCCAN register, the event causes the memory array to turn off and the MEMSTAT bit in the CAN1PDS register to be 0x0 (array OFF).
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Tiva™ TM4C129ENCPDT Microcontroller Register 40: Watchdog Timer Peripheral Present (PPWD), offset 0x300 The PPWD register provides software information regarding the watchdog modules. Important: This register should be used to determine which watchdog timers are implemented on this microcontroller. Watchdog Timer Peripheral Present (PPWD) Base 0x400F.E000 Offset 0x300 Type RO, reset 0x0000.
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System Control Register 41: 16/32-Bit General-Purpose Timer Peripheral Present (PPTIMER), offset 0x304 The PPTIMER register provides software information regarding the 16/32-bit general-purpose timer modules. Important: This register should be used to determine which timers are implemented on this microcontroller. 16/32-Bit General-Purpose Timer Peripheral Present (PPTIMER) Base 0x400F.E000 Offset 0x304 Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3 P3 RO 0x1 Description 16/32-Bit General-Purpose Timer 3 Present Value Description 2 P2 RO 0x1 0 16/32-bit general-purpose timer module 3 is not present. 1 16/32-bit general-purpose timer module 3 is present. 16/32-Bit General-Purpose Timer 2 Present Value Description 1 P1 RO 0x1 0 16/32-bit general-purpose timer module 2 is not present. 1 16/32-bit general-purpose timer module 2 is present.
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System Control Register 42: General-Purpose Input/Output Peripheral Present (PPGPIO), offset 0x308 The PPGPIO register provides software information regarding the general-purpose input/output modules. Important: This register should be used to determine which GPIO ports are implemented on this microcontroller. General-Purpose Input/Output Peripheral Present (PPGPIO) Base 0x400F.E000 Offset 0x308 Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 10 P10 RO 0x1 Description GPIO Port L Present Value Description 9 P9 RO 0x1 0 GPIO Port L is not present. 1 GPIO Port L is present. GPIO Port K Present Value Description 8 P8 RO 0x1 0 GPIO Port K is not present. 1 GPIO Port K is present. GPIO Port J Present Value Description 7 P7 RO 0x1 0 GPIO Port J is not present. 1 GPIO Port J is present.
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System Control Bit/Field Name Type Reset 3 P3 RO 0x1 Description GPIO Port D Present Value Description 2 P2 RO 0x1 0 GPIO Port D is not present. 1 GPIO Port D is present. GPIO Port C Present Value Description 1 P1 RO 0x1 0 GPIO Port C is not present. 1 GPIO Port C is present. GPIO Port B Present Value Description 0 P0 RO 0x1 0 GPIO Port B is not present. 1 GPIO Port B is present. GPIO Port A Present Value Description 0 GPIO Port A is not present.
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Tiva™ TM4C129ENCPDT Microcontroller Register 43: Micro Direct Memory Access Peripheral Present (PPDMA), offset 0x30C The PPDMA register provides software information regarding the μDMA module. Important: This register should be used to determine if the μDMA module is implemented on this microcontroller. Micro Direct Memory Access Peripheral Present (PPDMA) Base 0x400F.E000 Offset 0x30C Type RO, reset 0x0000.
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System Control Register 44: EPI Peripheral Present (PPEPI), offset 0x310 The PPEPI register provides software information regarding the EPI module. Important: This register should be used to determine if the EPI module is implemented on this microcontroller. EPI Peripheral Present (PPEPI) Base 0x400F.E000 Offset 0x310 Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 45: Hibernation Peripheral Present (PPHIB), offset 0x314 The PPHIB register provides software information regarding the Hibernation module. Important: This register should be used to determine if the Hibernation module is implemented on this microcontroller. Hibernation Peripheral Present (PPHIB) Base 0x400F.E000 Offset 0x314 Type RO, reset 0x0000.
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System Control Register 46: Universal Asynchronous Receiver/Transmitter Peripheral Present (PPUART), offset 0x318 The PPUART register provides software information regarding the UART modules. Important: This register should be used to determine which UART modules are implemented on this microcontroller. Universal Asynchronous Receiver/Transmitter Peripheral Present (PPUART) Base 0x400F.E000 Offset 0x318 Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3 P3 RO 0x1 Description UART Module 3 Present Value Description 2 P2 RO 0x1 0 UART module 3 is not present. 1 UART module 3 is present. UART Module 2 Present Value Description 1 P1 RO 0x1 0 UART module 2 is not present. 1 UART module 2 is present. UART Module 1 Present Value Description 0 P0 RO 0x1 0 UART module 1 is not present. 1 UART module 1 is present.
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System Control Register 47: Synchronous Serial Interface Peripheral Present (PPSSI), offset 0x31C The PPSSI register provides software information regarding the SSI modules. Important: This register should be used to determine which SSI modules are implemented on this microcontroller. However, to support legacy software, the DC2 register is available. A read of the DC2 register correctly identifies if a legacy SSI module is present.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 0 P0 RO 0x1 Description SSI Module 0 Present Value Description 0 SSI module 0 is not present. 1 SSI module 0 is present.
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System Control Register 48: Inter-Integrated Circuit Peripheral Present (PPI2C), offset 0x320 The PPI2C register provides software information regarding the I2C modules. Important: This register should be used to determine which I2C modules are implemented on this microcontroller. Inter-Integrated Circuit Peripheral Present (PPI2C) Base 0x400F.E000 Offset 0x320 Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 5 P5 RO 0x1 Description I2C Module 5 Present Value Description 4 P4 RO 0x1 0 I2C module 5 is not present. 1 I2C module 5 is present. I2C Module 4 Present Value Description 3 P3 RO 0x1 0 I2C module 4 is not present. 1 I2C module 4 is present. I2C Module 3 Present Value Description 2 P2 RO 0x1 0 I2C module 3 is not present. 1 I2C module 3 is present.
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System Control Register 49: Universal Serial Bus Peripheral Present (PPUSB), offset 0x328 The PPUSB register provides software information regarding the USB module. Important: This register should be used to determine if the USB module is implemented on this microcontroller. Universal Serial Bus Peripheral Present (PPUSB) Base 0x400F.E000 Offset 0x328 Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 50: Ethernet PHY Peripheral Present (PPEPHY), offset 0x330 The PPEPHY register provides software information regarding the Ethernet PHY module. Important: This register should be used to determine if the Ethernet PHY module is implemented on this microcontroller. Ethernet PHY Peripheral Present (PPEPHY) Base 0x400F.E000 Offset 0x330 Type RO, reset 0x0000.
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System Control Register 51: Controller Area Network Peripheral Present (PPCAN), offset 0x334 The PPCAN register provides software information regarding the CAN modules. Important: This register should be used to determine which CAN modules are implemented on this microcontroller. Controller Area Network Peripheral Present (PPCAN) Base 0x400F.E000 Offset 0x334 Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 52: Analog-to-Digital Converter Peripheral Present (PPADC), offset 0x338 The PPADC register provides software information regarding the ADC modules. Important: This register should be used to determine which ADC modules are implemented on this microcontroller. Analog-to-Digital Converter Peripheral Present (PPADC) Base 0x400F.E000 Offset 0x338 Type RO, reset 0x0000.
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System Control Register 53: Analog Comparator Peripheral Present (PPACMP), offset 0x33C The PPACMP register provides software information regarding the analog comparator module. Important: This register should be used to determine if the analog comparator module is implemented on this microcontroller. Note that the Analog Comparator Peripheral Properties (ACMPPP) register indicates how many analog comparator blocks are included in the module. Analog Comparator Peripheral Present (PPACMP) Base 0x400F.
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Tiva™ TM4C129ENCPDT Microcontroller Register 54: Pulse Width Modulator Peripheral Present (PPPWM), offset 0x340 The PPPWM register provides software information regarding the PWM modules. Important: This register should be used to determine which PWM modules are implemented on this microcontroller. Pulse Width Modulator Peripheral Present (PPPWM) Base 0x400F.E000 Offset 0x340 Type RO, reset 0x0000.
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System Control Register 55: Quadrature Encoder Interface Peripheral Present (PPQEI), offset 0x344 The PPQEI register provides software information regarding the QEI modules. Important: This register should be used to determine which QEI modules are implemented on this microcontroller. Quadrature Encoder Interface Peripheral Present (PPQEI) Base 0x400F.E000 Offset 0x344 Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 56: Low Pin Count Interface Peripheral Present (PPLPC), offset 0x348 The PPLPC register provides software information regarding the LPC module. Low Pin Count Interface Peripheral Present (PPLPC) Base 0x400F.E000 Offset 0x348 Type RO, reset 0x0000.
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System Control Register 57: Platform Environment Control Interface Peripheral Present (PPPECI), offset 0x350 The PPPECI register provides software information regarding the PECI module. Platform Environment Control Interface Peripheral Present (PPPECI) Base 0x400F.E000 Offset 0x350 Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 58: Fan Control Peripheral Present (PPFAN), offset 0x354 The PPFAN register provides software information regarding the FAN module. Fan Control Peripheral Present (PPFAN) Base 0x400F.E000 Offset 0x354 Type RO, reset 0x0000.
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System Control Register 59: EEPROM Peripheral Present (PPEEPROM), offset 0x358 The PPEEPROM register provides software information regarding the EEPROM module. EEPROM Peripheral Present (PPEEPROM) Base 0x400F.E000 Offset 0x358 Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 60: 32/64-Bit Wide General-Purpose Timer Peripheral Present (PPWTIMER), offset 0x35C The PPWTIMER register provides software information regarding the 32/64-bit wide general-purpose timer modules. 32/64-Bit Wide General-Purpose Timer Peripheral Present (PPWTIMER) Base 0x400F.E000 Offset 0x35C Type RO, reset 0x0000.
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System Control Register 61: Remote Temperature Sensor Peripheral Present (PPRTS), offset 0x370 The PPRTS register provides software information regarding the Remote Temperature Sensor (RTS) module. Important: This register should be used to determine which RTS modules are implemented on this microcontroller. Remote Temperature Sensor Peripheral Present (PPRTS) Base 0x400F.E000 Offset 0x370 Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 62: CRC and Cryptographic Modules Peripheral Present (PPCCM), offset 0x374 The PPCCM register provides software information regarding the CRC and Cryptographic Modules (AES, DES, and SHA). Important: This register should be used to determine if the CRC and Cryptographic Modules (AES, DES, SHA/MD5) are implemented on this microcontroller. CRC and Cryptographic Modules Peripheral Present (PPCCM) Base 0x400F.E000 Offset 0x374 Type RO, reset 0x0000.
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System Control Register 63: LCD Peripheral Present (PPLCD), offset 0x390 The PPLCD register provides software information regarding the LCD module. Important: This register should be used to determine if an LCD controller is implemented on this microcontroller. LCD Peripheral Present (PPLCD) Base 0x400F.E000 Offset 0x390 Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 64: 1-Wire Peripheral Present (PPOWIRE), offset 0x398 The PPOWIRE register provides software information regarding the 1-Wire module. Important: This register should be used to determine which 1-Wire modules are implemented on this microcontroller. 1-Wire Peripheral Present (PPOWIRE) Base 0x400F.E000 Offset 0x398 Type RO, reset 0x0000.
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System Control Register 65: Ethernet MAC Peripheral Present (PPEMAC), offset 0x39C The PPEMAC register provides software information regarding the Ethernet controller module. Important: This register should be used to determine which Ethernet controller modules are implemented on this microcontroller. Ethernet MAC Peripheral Present (PPEMAC) Base 0x400F.E000 Offset 0x39C Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 66: Power Regulator Bus Peripheral Present (PPPRB), offset 0x3A0 The PPPRB register provides software information regarding the Power Regulator Bus module. Important: This register should be used to determine which Power Regulator Bus modules are implemented on this microcontroller. Power Regulator Bus Peripheral Present (PPPRB) Base 0x400F.E000 Offset 0x3A0 Type RO, reset 0x0000.
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System Control Register 67: Human Interface Master Peripheral Present (PPHIM), offset 0x3A4 The PPHIM register provides software information regarding the Human Interface Master (HIM) module. Important: This register should be used to determine which HIM modules are implemented on this microcontroller. Human Interface Master Peripheral Present (PPHIM) Base 0x400F.E000 Offset 0x3A4 Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 68: Watchdog Timer Software Reset (SRWD), offset 0x500 The SRWD register provides software the capability to reset the available watchdog modules. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRWD register. While the SRWD bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRWD bit.
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System Control Register 69: 16/32-Bit General-Purpose Timer Software Reset (SRTIMER), offset 0x504 The SRTIMER register provides software the capability to reset the available 16/32-bit timer modules. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRTIMER register. While the SRTIMER bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRTIMER bit.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 5 R5 RW 0 Description 16/32-Bit General-Purpose Timer 5 Software Reset Value Description 4 R4 RW 0 0 16/32-bit general-purpose timer module 5 is not reset. 1 16/32-bit general-purpose timer module 5 is reset. 16/32-Bit General-Purpose Timer 4 Software Reset Value Description 3 R3 RW 0 0 16/32-bit general-purpose timer module 4 is not reset. 1 16/32-bit general-purpose timer module 4 is reset.
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System Control Register 70: General-Purpose Input/Output Software Reset (SRGPIO), offset 0x508 The SRGPIO register provides software the capability to reset the available GPIO modules. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRGPIO register. While the SRGPIO bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRGPIO bit.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 12 R12 RW 0 Description GPIO Port N Software Reset Value Description 11 R11 RW 0 0 GPIO Port N is not reset. 1 GPIO Port N is reset. GPIO Port M Software Reset Value Description 10 R10 RW 0 0 GPIO Port M is not reset. 1 GPIO Port M is reset. GPIO Port L Software Reset Value Description 9 R9 RW 0 0 GPIO Port L is not reset. 1 GPIO Port L is reset.
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System Control Bit/Field Name Type Reset 5 R5 RW 0 Description GPIO Port F Software Reset Value Description 4 R4 RW 0 0 GPIO Port F is not reset. 1 GPIO Port F is reset. GPIO Port E Software Reset Value Description 3 R3 RW 0 0 GPIO Port E is not reset. 1 GPIO Port E is reset. GPIO Port D Software Reset Value Description 2 R2 RW 0 0 GPIO Port D is not reset. 1 GPIO Port D is reset. GPIO Port C Software Reset Value Description 1 R1 RW 0 0 GPIO Port C is not reset.
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Tiva™ TM4C129ENCPDT Microcontroller Register 71: Micro Direct Memory Access Software Reset (SRDMA), offset 0x50C The SRDMA register provides software the capability to reset the available μDMA module. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRDMA register. While the SRDMA bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRDMA bit.
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System Control Register 72: EPI Software Reset (SREPI), offset 0x510 The SREPI register provides software the capability to reset the available EPI module. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SREPI register. While the SREPI bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SREPI bit. There may be latency from the clearing of the SREPI bit to when the peripheral is ready for use.
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Tiva™ TM4C129ENCPDT Microcontroller Register 73: Hibernation Software Reset (SRHIB), offset 0x514 The SRHIB register provides software the capability to reset the available Hibernation module. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRHIB register. While the SRHIB bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRHIB bit.
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System Control Register 74: Universal Asynchronous Receiver/Transmitter Software Reset (SRUART), offset 0x518 The SRUART register provides software the capability to reset the available UART modules. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRUART register. While the SRUART bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRUART bit.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 5 R5 RW 0 Description UART Module 5 Software Reset Value Description 4 R4 RW 0 0 UART module 5 is not reset. 1 UART module 5 is reset. UART Module 4 Software Reset Value Description 3 R3 RW 0 0 UART module 4 is not reset. 1 UART module 4 is reset. UART Module 3 Software Reset Value Description 2 R2 RW 0 0 UART module 3 is not reset. 1 UART module 3 is reset.
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System Control Register 75: Synchronous Serial Interface Software Reset (SRSSI), offset 0x51C The SRSSI register provides software the capability to reset the available SSI modules. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRSSI register. While the SRSSI bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRSSI bit.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1 R1 RW 0 Description SSI Module 1 Software Reset Value Description 0 R0 RW 0 0 SSI module 1 is not reset. 1 SSI module 1 is reset. SSI Module 0 Software Reset Value Description 0 SSI module 0 is not reset. 1 SSI module 0 is reset.
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System Control Register 76: Inter-Integrated Circuit Software Reset (SRI2C), offset 0x520 The SRI2C register provides software the capability to reset the available I2C modules. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRI2C register. While the SRI2C bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRI2C bit.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 6 R6 RW 0 Description I2C Module 6 Software Reset Value Description 5 R5 RW 0 0 I2C module 6 is not reset. 1 I2C module 6 is reset. I2C Module 5 Software Reset Value Description 4 R4 RW 0 0 I2C module 5 is not reset. 1 I2C module 5 is reset. I2C Module 4 Software Reset Value Description 3 R3 RW 0 0 I2C module 4 is not reset. 1 I2C module 4 is reset.
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System Control Register 77: Universal Serial Bus Software Reset (SRUSB), offset 0x528 The SRUSB register provides software the capability to reset the available USB module. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRUSB register. While the SRUSB bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRUSB bit.
PAGE 377
Tiva™ TM4C129ENCPDT Microcontroller Register 78: Ethernet PHY Software Reset (SREPHY), offset 0x530 The SREPHY register provides software the capability to reset the available PHY module. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SREPHY register. While the SREPHY bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SREPHY bit.
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System Control Register 79: Controller Area Network Software Reset (SRCAN), offset 0x534 The SRCAN register provides software the capability to reset the available CAN modules. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRCAN register. While the SRCAN bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRCAN bit.
PAGE 379
Tiva™ TM4C129ENCPDT Microcontroller Register 80: Analog-to-Digital Converter Software Reset (SRADC), offset 0x538 The SRADC register provides software the capability to reset the available ADC modules. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRADC register. While the SRADC bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRADC bit.
PAGE 380
System Control Register 81: Analog Comparator Software Reset (SRACMP), offset 0x53C The SRACMP register provides software the capability to reset the available analog comparator module. A block is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRACMP register. While the SRACMP bit is 1, the module is held in reset. 2. Software completes the reset process by clearing the SRACMP bit.
PAGE 381
Tiva™ TM4C129ENCPDT Microcontroller Register 82: Pulse Width Modulator Software Reset (SRPWM), offset 0x540 The SRPWM register provides software the capability to reset the available PWM modules. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRPWM register. While the SRPWM bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRPWM bit.
PAGE 382
System Control Register 83: Quadrature Encoder Interface Software Reset (SRQEI), offset 0x544 The SRQEI register provides software the capability to reset the available QEI modules. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SRQEI register. While the SRQEI bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SRQEI bit.
PAGE 383
Tiva™ TM4C129ENCPDT Microcontroller Register 84: EEPROM Software Reset (SREEPROM), offset 0x558 The SREEPROM register provides software the capability to reset the available EEPROM module. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SREEPROM register. While the SREEPROM bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SREEPROM bit.
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System Control Register 85: CRC and Cryptographic Modules Software Reset (SRCCM), offset 0x574 The SRCCM register provides software the capability to reset the CRC and Cryptographic Modules (AES, DES, and SHA/MD5). A module is reset by software using a simple two-step process: 1. Software sets the bit in the SRCCM register. While the SRCCM bit is 1, the peripherals are held in reset. 2. Software completes the reset process by clearing the SRCCM bit.
PAGE 385
Tiva™ TM4C129ENCPDT Microcontroller Register 86: Ethernet MAC Software Reset (SREMAC), offset 0x59C The SREMAC register provides software the capability to reset the available Ethernet MAC module. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in the SREMAC register. While the SREMAC bit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing the SREMAC bit.
PAGE 386
System Control Register 87: Watchdog Timer Run Mode Clock Gating Control (RCGCWD), offset 0x600 The RCGCWD register provides software the capability to enable and disable watchdog modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault.
PAGE 387
Tiva™ TM4C129ENCPDT Microcontroller Register 88: 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control (RCGCTIMER), offset 0x604 The RCGCGPT32 register provides software the capability to enable and disable 16/32-bit timer modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault.
PAGE 388
System Control Bit/Field Name Type Reset 4 R4 RW 0 Description 16/32-Bit General-Purpose Timer 4 Run Mode Clock Gating Control Value Description 3 R3 RW 0 0 16/32-bit general-purpose timer module 4 is disabled. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 4 in Run mode. 16/32-Bit General-Purpose Timer 3 Run Mode Clock Gating Control Value Description 2 R2 RW 0 0 16/32-bit general-purpose timer module 3 is disabled.
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Tiva™ TM4C129ENCPDT Microcontroller Register 89: General-Purpose Input/Output Run Mode Clock Gating Control (RCGCGPIO), offset 0x608 The RCGCGPIO register provides software the capability to enable and disable GPIO modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault.
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System Control Bit/Field Name Type Reset 10 R10 RW 0 Description GPIO Port L Run Mode Clock Gating Control Value Description 9 R9 RW 0 0 GPIO Port L is disabled. 1 Enable and provide a clock to GPIO Port L in Run mode. GPIO Port K Run Mode Clock Gating Control Value Description 8 R8 RW 0 0 GPIO Port K is disabled. 1 Enable and provide a clock to GPIO Port K in Run mode. GPIO Port J Run Mode Clock Gating Control Value Description 7 R7 RW 0 0 GPIO Port J is disabled.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3 R3 RW 0 Description GPIO Port D Run Mode Clock Gating Control Value Description 2 R2 RW 0 0 GPIO Port D is disabled. 1 Enable and provide a clock to GPIO Port D in Run mode. GPIO Port C Run Mode Clock Gating Control Value Description 1 R1 RW 0 0 GPIO Port C is disabled. 1 Enable and provide a clock to GPIO Port C in Run mode.
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System Control Register 90: Micro Direct Memory Access Run Mode Clock Gating Control (RCGCDMA), offset 0x60C The RCGCDMA register provides software the capability to enable and disable the μDMA module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. Important: This register should be used to control the clocking for the μDMA module.
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Tiva™ TM4C129ENCPDT Microcontroller Register 91: EPI Run Mode Clock Gating Control (RCGCEPI), offset 0x610 The RCGCEPI register provides software the capability to enable and disable the EPI module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. Important: This register should be used to control the clocking for the EPI module.
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System Control Register 92: Hibernation Run Mode Clock Gating Control (RCGCHIB), offset 0x614 The RCGCHIB register provides software the capability to enable and disable the Hibernation module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. Important: This register should be used to control the clocking for the Hibernation module.
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Tiva™ TM4C129ENCPDT Microcontroller Register 93: Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control (RCGCUART), offset 0x618 The RCGCUART register provides software the capability to enable and disable the UART modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault.
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System Control Bit/Field Name Type Reset 3 R3 RW 0 Description UART Module 3 Run Mode Clock Gating Control Value Description 2 R2 RW 0 0 UART module 3 is disabled. 1 Enable and provide a clock to UART module 3 in Run mode. UART Module 2 Run Mode Clock Gating Control Value Description 1 R1 RW 0 0 UART module 2 is disabled. 1 Enable and provide a clock to UART module 2 in Run mode.
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Tiva™ TM4C129ENCPDT Microcontroller Register 94: Synchronous Serial Interface Run Mode Clock Gating Control (RCGCSSI), offset 0x61C The RCGCSSI register provides software the capability to enable and disable the SSI modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault.
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System Control Register 95: Inter-Integrated Circuit Run Mode Clock Gating Control (RCGCI2C), offset 0x620 The RCGCI2C register provides software the capability to enable and disable the I2C modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. Important: This register should be used to control the clocking for the I2C modules.
PAGE 399
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 6 R6 RW 0 Description I2C Module 6 Run Mode Clock Gating Control Value Description 5 R5 RW 0 0 I2C module 6 is disabled. 1 Enable and provide a clock to I2C module 6 in Run mode. I2C Module 5 Run Mode Clock Gating Control Value Description 4 R4 RW 0 0 I2C module 5 is disabled. 1 Enable and provide a clock to I2C module 5 in Run mode.
PAGE 400
System Control Register 96: Universal Serial Bus Run Mode Clock Gating Control (RCGCUSB), offset 0x628 The RCGCUSB register provides software the capability to enable and disable the USB module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. Important: This register should be used to control the clocking for the USB module.
PAGE 401
Tiva™ TM4C129ENCPDT Microcontroller Register 97: Ethernet PHY Run Mode Clock Gating Control (RCGCEPHY), offset 0x630 The RCGCEPHY register provides software the capability to enable and disable the PHY module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. Important: This register should be used to control the clocking for the PHY module.
PAGE 402
System Control Register 98: Controller Area Network Run Mode Clock Gating Control (RCGCCAN), offset 0x634 The RCGCCAN register provides software the capability to enable and disable the CAN modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. Important: This register should be used to control the clocking for the CAN modules.
PAGE 403
Tiva™ TM4C129ENCPDT Microcontroller Register 99: Analog-to-Digital Converter Run Mode Clock Gating Control (RCGCADC), offset 0x638 The RCGCADC register provides software the capability to enable and disable the ADC modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault.
PAGE 404
System Control Register 100: Analog Comparator Run Mode Clock Gating Control (RCGCACMP), offset 0x63C The RCGCACMP register provides software the capability to enable and disable the analog comparator module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault.
PAGE 405
Tiva™ TM4C129ENCPDT Microcontroller Register 101: Pulse Width Modulator Run Mode Clock Gating Control (RCGCPWM), offset 0x640 The RCGCPWM register provides software the capability to enable and disable the PWM modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. Important: This register should be used to control the clocking for the PWM modules.
PAGE 406
System Control Register 102: Quadrature Encoder Interface Run Mode Clock Gating Control (RCGCQEI), offset 0x644 The RCGCQEI register provides software the capability to enable and disable the QEI modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. Important: This register should be used to control the clocking for the QEI modules.
PAGE 407
Tiva™ TM4C129ENCPDT Microcontroller Register 103: EEPROM Run Mode Clock Gating Control (RCGCEEPROM), offset 0x658 The RCGCEEPROM register provides software the capability to enable and disable the EEPROM module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. EEPROM Run Mode Clock Gating Control (RCGCEEPROM) Base 0x400F.
PAGE 408
System Control Register 104: CRC and Cryptographic Modules Run Mode Clock Gating Control (RCGCCCM), offset 0x674 The RCGCCCM register provides software the capability to enable and disable the CRC and Encryption Modules ( AES, DES, and SHA/MD5) in Run mode. When enabled, the modules are provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault.
PAGE 409
Tiva™ TM4C129ENCPDT Microcontroller Register 105: Ethernet MAC Run Mode Clock Gating Control (RCGCEMAC), offset 0x69C The RCGCEMAC register provides software the capability to enable and disable the Ethernet MAC module in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault.
PAGE 410
System Control Register 106: Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD), offset 0x700 The SCGCWD register provides software the capability to enable and disable watchdog modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the watchdog modules. Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD) Base 0x400F.E000 Offset 0x700 Type RW, reset 0x0000.
PAGE 411
Tiva™ TM4C129ENCPDT Microcontroller Register 107: 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control (SCGCTIMER), offset 0x704 The SCGCGPT32 register provides software the capability to enable and disable 16/32-bit timer modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the timer modules.
PAGE 412
System Control Bit/Field Name Type Reset 4 S4 RW 0 Description 16/32-Bit General-Purpose Timer 4 Sleep Mode Clock Gating Control Value Description 3 S3 RW 0 0 16/32-bit general-purpose timer module 4 is disabled in sleep mode. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 4 in sleep mode. 16/32-Bit General-Purpose Timer 3 Sleep Mode Clock Gating Control Value Description 2 S2 RW 0 0 16/32-bit general-purpose timer module 3 is disabled in sleep mode.
PAGE 413
Tiva™ TM4C129ENCPDT Microcontroller Register 108: General-Purpose Input/Output Sleep Mode Clock Gating Control (SCGCGPIO), offset 0x708 The SCGCGPIO register provides software the capability to enable and disable GPIO modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the GPIO modules. General-Purpose Input/Output Sleep Mode Clock Gating Control (SCGCGPIO) Base 0x400F.
PAGE 414
System Control Bit/Field Name Type Reset 10 S10 RW 0 Description GPIO Port L Sleep Mode Clock Gating Control Value Description 9 S9 RW 0 0 GPIO Port L is disabled in sleep mode. 1 Enable and provide a clock to GPIO Port L in sleep mode. GPIO Port K Sleep Mode Clock Gating Control Value Description 8 S8 RW 0 0 GPIO Port K is disabled in sleep mode. 1 Enable and provide a clock to GPIO Port K in sleep mode.
PAGE 415
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3 S3 RW 0 Description GPIO Port D Sleep Mode Clock Gating Control Value Description 2 S2 RW 0 0 GPIO Port D is disabled in sleep mode. 1 Enable and provide a clock to GPIO Port D in sleep mode. GPIO Port C Sleep Mode Clock Gating Control Value Description 1 S1 RW 0 0 GPIO Port C is disabled in sleep mode. 1 Enable and provide a clock to GPIO Port C in sleep mode.
PAGE 416
System Control Register 109: Micro Direct Memory Access Sleep Mode Clock Gating Control (SCGCDMA), offset 0x70C The SCGCDMA register provides software the capability to enable and disable the μDMA module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the μDMA module. Micro Direct Memory Access Sleep Mode Clock Gating Control (SCGCDMA) Base 0x400F.
PAGE 417
Tiva™ TM4C129ENCPDT Microcontroller Register 110: EPI Sleep Mode Clock Gating Control (SCGCEPI), offset 0x710 The SCGCEPI register provides software the capability to enable and disable the EPI module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the EPI module. EPI Sleep Mode Clock Gating Control (SCGCEPI) Base 0x400F.E000 Offset 0x710 Type RW, reset 0x0000.
PAGE 418
System Control Register 111: Hibernation Sleep Mode Clock Gating Control (SCGCHIB), offset 0x714 The SCGCHIB register provides software the capability to enable and disable the Hibernation module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the Hibernation module. Hibernation Sleep Mode Clock Gating Control (SCGCHIB) Base 0x400F.E000 Offset 0x714 Type RW, reset 0x0000.
PAGE 419
Tiva™ TM4C129ENCPDT Microcontroller Register 112: Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control (SCGCUART), offset 0x718 The SCGCUART register provides software the capability to enable and disable the UART modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the UART modules.
PAGE 420
System Control Bit/Field Name Type Reset 3 S3 RW 0 Description UART Module 3 Sleep Mode Clock Gating Control Value Description 2 S2 RW 0 0 UART module 3 is disabled in sleep mode. 1 Enable and provide a clock to UART module 3 in sleep mode. UART Module 2 Sleep Mode Clock Gating Control Value Description 1 S1 RW 0 0 UART module 2 is disabled in sleep mode. 1 Enable and provide a clock to UART module 2 in sleep mode.
PAGE 421
Tiva™ TM4C129ENCPDT Microcontroller Register 113: Synchronous Serial Interface Sleep Mode Clock Gating Control (SCGCSSI), offset 0x71C The SCGCSSI register provides software the capability to enable and disable the SSI modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the SSI modules. Synchronous Serial Interface Sleep Mode Clock Gating Control (SCGCSSI) Base 0x400F.
PAGE 422
System Control Register 114: Inter-Integrated Circuit Sleep Mode Clock Gating Control (SCGCI2C), offset 0x720 The SCGCI2C register provides software the capability to enable and disable the I2C modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the I2C modules. Inter-Integrated Circuit Sleep Mode Clock Gating Control (SCGCI2C) Base 0x400F.
PAGE 423
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 5 S5 RW 0 Description I2C Module 5 Sleep Mode Clock Gating Control Value Description 4 S4 RW 0 0 I2C module 5 is disabled in sleep mode. 1 Enable and provide a clock to I2C module 5 in sleep mode. I2C Module 4 Sleep Mode Clock Gating Control Value Description 3 S3 RW 0 0 I2C module 4 is disabled in sleep mode. 1 Enable and provide a clock to I2C module 4 in sleep mode.
PAGE 424
System Control Register 115: Universal Serial Bus Sleep Mode Clock Gating Control (SCGCUSB), offset 0x728 The SCGCUSB register provides software the capability to enable and disable the USB module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the USB module. Universal Serial Bus Sleep Mode Clock Gating Control (SCGCUSB) Base 0x400F.E000 Offset 0x728 Type RW, reset 0x0000.
PAGE 425
Tiva™ TM4C129ENCPDT Microcontroller Register 116: Ethernet PHY Sleep Mode Clock Gating Control (SCGCEPHY), offset 0x730 The SCGCEPHY register provides software the capability to enable and disable the PHY module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the PHY module. Ethernet PHY Sleep Mode Clock Gating Control (SCGCEPHY) Base 0x400F.
PAGE 426
System Control Register 117: Controller Area Network Sleep Mode Clock Gating Control (SCGCCAN), offset 0x734 The SCGCCAN register provides software the capability to enable and disable the CAN modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the CAN modules. Controller Area Network Sleep Mode Clock Gating Control (SCGCCAN) Base 0x400F.
PAGE 427
Tiva™ TM4C129ENCPDT Microcontroller Register 118: Analog-to-Digital Converter Sleep Mode Clock Gating Control (SCGCADC), offset 0x738 The SCGCADC register provides software the capability to enable and disable the ADC modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the ADC modules. Analog-to-Digital Converter Sleep Mode Clock Gating Control (SCGCADC) Base 0x400F.
PAGE 428
System Control Register 119: Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP), offset 0x73C The SCGCACMP register provides software the capability to enable and disable the analog comparator module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the analog comparator module. Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP) Base 0x400F.
PAGE 429
Tiva™ TM4C129ENCPDT Microcontroller Register 120: Pulse Width Modulator Sleep Mode Clock Gating Control (SCGCPWM), offset 0x740 The SCGCPWM register provides software the capability to enable and disable the PWM modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the PWM modules. Pulse Width Modulator Sleep Mode Clock Gating Control (SCGCPWM) Base 0x400F.
PAGE 430
System Control Register 121: Quadrature Encoder Interface Sleep Mode Clock Gating Control (SCGCQEI), offset 0x744 The SCGCQEI register provides software the capability to enable and disable the QEI modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the QEI modules. Quadrature Encoder Interface Sleep Mode Clock Gating Control (SCGCQEI) Base 0x400F.
PAGE 431
Tiva™ TM4C129ENCPDT Microcontroller Register 122: EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM), offset 0x758 The SCGCEEPROM register provides software the capability to enable and disable the EEPROM module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM) Base 0x400F.E000 Offset 0x758 Type RW, reset 0x0000.
PAGE 432
System Control Register 123: CRC and Cryptographic Modules Sleep Mode Clock Gating Control (SCGCCCM), offset 0x774 The SCGCCCM register provides software the capability to enable and disable the CRC and Encryption Control, AES, DES, and SHA/MD5 modules in sleep mode. When enabled, the modules are provided a clock . When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the CRC, AES, DES, and SHA/MD5 modules.
PAGE 433
Tiva™ TM4C129ENCPDT Microcontroller Register 124: Ethernet MAC Sleep Mode Clock Gating Control (SCGCEMAC), offset 0x79C The SCGCEMAC register provides software the capability to enable and disable the Ethernet MAC module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the Ethernet MAC module. Ethernet MAC Sleep Mode Clock Gating Control (SCGCEMAC) Base 0x400F.
PAGE 434
System Control Register 125: Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD), offset 0x800 The DCGCWD register provides software the capability to enable and disable watchdog modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the watchdog modules. Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD) Base 0x400F.
PAGE 435
Tiva™ TM4C129ENCPDT Microcontroller Register 126: 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCTIMER), offset 0x804 The DCGCGPT32 register provides software the capability to enable and disable 16/32-bit timer modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the timer modules.
PAGE 436
System Control Bit/Field Name Type Reset 4 D4 RW 0 Description 16/32-Bit General-Purpose Timer 4 Deep-Sleep Mode Clock Gating Control Value Description 3 D3 RW 0 0 16/32-bit general-purpose timer module 4 is disabled in deep-sleep mode. 1 Enable and provide a clock to 16/32-bit general-purpose timer module 4 in deep-sleep mode.
PAGE 437
Tiva™ TM4C129ENCPDT Microcontroller Register 127: General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO), offset 0x808 The DCGCGPIO register provides software the capability to enable and disable GPIO modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the GPIO modules.
PAGE 438
System Control Bit/Field Name Type Reset 10 D10 RW 0 Description GPIO Port L Deep-Sleep Mode Clock Gating Control Value Description 9 D9 RW 0 0 GPIO Port L is disabled in deep-sleep mode. 1 Enable and provide a clock to GPIO Port L in deep-sleep mode. GPIO Port K Deep-Sleep Mode Clock Gating Control Value Description 8 D8 RW 0 0 GPIO Port K is disabled in deep-sleep mode. 1 Enable and provide a clock to GPIO Port K in deep-sleep mode.
PAGE 439
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3 D3 RW 0 Description GPIO Port D Deep-Sleep Mode Clock Gating Control Value Description 2 D2 RW 0 0 GPIO Port D is disabled in deep-sleep mode. 1 Enable and provide a clock to GPIO Port D in deep-sleep mode. GPIO Port C Deep-Sleep Mode Clock Gating Control Value Description 1 D1 RW 0 0 GPIO Port C is disabled in deep-sleep mode. 1 Enable and provide a clock to GPIO Port C in deep-sleep mode.
PAGE 440
System Control Register 128: Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA), offset 0x80C The DCGCDMA register provides software the capability to enable and disable the μDMA module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the μDMA module. Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA) Base 0x400F.
PAGE 441
Tiva™ TM4C129ENCPDT Microcontroller Register 129: EPI Deep-Sleep Mode Clock Gating Control (DCGCEPI), offset 0x810 The DCGCEPI register provides software the capability to enable and disable the EPI module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the EPI module. EPI Deep-Sleep Mode Clock Gating Control (DCGCEPI) Base 0x400F.E000 Offset 0x810 Type RW, reset 0x0000.
PAGE 442
System Control Register 130: Hibernation Deep-Sleep Mode Clock Gating Control (DCGCHIB), offset 0x814 The DCGCHIB register provides software the capability to enable and disable the Hibernation module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the Hibernation module. Hibernation Deep-Sleep Mode Clock Gating Control (DCGCHIB) Base 0x400F.
PAGE 443
Tiva™ TM4C129ENCPDT Microcontroller Register 131: Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control (DCGCUART), offset 0x818 The DCGCUART register provides software the capability to enable and disable the UART modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the UART modules.
PAGE 444
System Control Bit/Field Name Type Reset 4 D4 RW 0 Description UART Module 4 Deep-Sleep Mode Clock Gating Control Value Description 3 D3 RW 0 0 UART module 4 is disabled in deep-sleep mode. 1 Enable and provide a clock to UART module 4 in deep-sleep mode. UART Module 3 Deep-Sleep Mode Clock Gating Control Value Description 2 D2 RW 0 0 UART module 3 is disabled in deep-sleep mode. 1 Enable and provide a clock to UART module 3 in deep-sleep mode.
PAGE 445
Tiva™ TM4C129ENCPDT Microcontroller Register 132: Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control (DCGCSSI), offset 0x81C The DCGCSSI register provides software the capability to enable and disable the SSI modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the SSI modules.
PAGE 446
System Control Register 133: Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control (DCGCI2C), offset 0x820 The DCGCI2C register provides software the capability to enable and disable the I2C modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the I2C modules. Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control (DCGCI2C) Base 0x400F.
PAGE 447
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 5 D5 RW 0 Description I2C Module 5 Deep-Sleep Mode Clock Gating Control Value Description 4 D4 RW 0 0 I2C module 5 is disabled in deep-sleep mode. 1 Enable and provide a clock to I2C module 5 in deep-sleep mode. I2C Module 4 Deep-Sleep Mode Clock Gating Control Value Description 3 D3 RW 0 0 I2C module 4 is disabled in deep-sleep mode. 1 Enable and provide a clock to I2C module 4 in deep-sleep mode.
PAGE 448
System Control Register 134: Universal Serial Bus Deep-Sleep Mode Clock Gating Control (DCGCUSB), offset 0x828 The DCGCUSB register provides software the capability to enable and disable the USB module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the USB module. Universal Serial Bus Deep-Sleep Mode Clock Gating Control (DCGCUSB) Base 0x400F.
PAGE 449
Tiva™ TM4C129ENCPDT Microcontroller Register 135: Ethernet PHY Deep-Sleep Mode Clock Gating Control (DCGCEPHY), offset 0x830 The DCGCEPHY register provides software the capability to enable and disable the PHY module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the PHY module. Ethernet PHY Deep-Sleep Mode Clock Gating Control (DCGCEPHY) Base 0x400F.
PAGE 450
System Control Register 136: Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN), offset 0x834 The DCGCCAN register provides software the capability to enable and disable the CAN modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the CAN modules. Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN) Base 0x400F.
PAGE 451
Tiva™ TM4C129ENCPDT Microcontroller Register 137: Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control (DCGCADC), offset 0x838 The DCGCADC register provides software the capability to enable and disable the ADC modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the ADC modules.
PAGE 452
System Control Register 138: Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP), offset 0x83C The DCGCACMP register provides software the capability to enable and disable the analog comparator module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the analog comparator module. Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP) Base 0x400F.
PAGE 453
Tiva™ TM4C129ENCPDT Microcontroller Register 139: Pulse Width Modulator Deep-Sleep Mode Clock Gating Control (DCGCPWM), offset 0x840 The DCGCPWM register provides software the capability to enable and disable the PWM modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the PWM modules. Pulse Width Modulator Deep-Sleep Mode Clock Gating Control (DCGCPWM) Base 0x400F.
PAGE 454
System Control Register 140: Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control (DCGCQEI), offset 0x844 The DCGCQEI register provides software the capability to enable and disable the QEI modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the QEI modules. Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control (DCGCQEI) Base 0x400F.
PAGE 455
Tiva™ TM4C129ENCPDT Microcontroller Register 141: EEPROM Deep-Sleep Mode Clock Gating Control (DCGCEEPROM), offset 0x858 The DCGCEEPROM register provides software the capability to enable and disable the EEPROM module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. EEPROM Deep-Sleep Mode Clock Gating Control (DCGCEEPROM) Base 0x400F.E000 Offset 0x858 Type RW, reset 0x0000.
PAGE 456
System Control Register 142: CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control (DCGCCCM), offset 0x874 The DCGCCCM register provides software the capability to enable and disable the CRC, AES, DES, and SHA/MD5 modules in deep-sleep mode. When enabled, the modules are provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the CRC, AES, DES, and SHA/MD modules.
PAGE 457
Tiva™ TM4C129ENCPDT Microcontroller Register 143: Ethernet MAC Deep-Sleep Mode Clock Gating Control (DCGCEMAC), offset 0x89C The DCGCEMAC register provides software the capability to enable and disable the Ethernet MAC module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. Important: This register should be used to control the clocking for the Ethernet MAC module. Ethernet MAC Deep-Sleep Mode Clock Gating Control (DCGCEMAC) Base 0x400F.
PAGE 458
System Control Register 144: Watchdog Timer Power Control (PCWD), offset 0x900 Important: The Watchdog Timer modules do not currently provide the ability to respond to the power down request. Setting a bit in this register has no effect on power consumption. This register is defined for future software compatibility. The PCWD register controls the power applied to the Watchdog Module module.
PAGE 459
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1 P1 RW 1 Description Watchdog Timer 1 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCWD, SCGCWD or DCGCWD register is clear. Value Description 0 Watchdog Timer 1 module is not powered and does not receive a clock. In this case, the module's state is not retained. This configuration provides the lowest power consumption state.
PAGE 460
System Control Register 145: 16/32-Bit General-Purpose Timer Power Control (PCTIMER), offset 0x904 Important: The Timer module does not currently provide the ability to respond to the power down request. Setting a bit in this register has no effect on power consumption. This register is defined for future software compatibility. The PCTIMER register controls the power applied to the Timer module.
PAGE 461
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset Description 31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 P7 RW 1 General-Purpose Timer 7 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCTIMER, SCGCTIMER or DCGCTIMER register is clear.
PAGE 462
System Control Bit/Field Name Type Reset 3 P3 RW 1 Description General-Purpose Timer 3 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCTIMER, SCGCTIMER or DCGCTIMER register is clear. Value Description 0 Timer 3 module is not powered and does not receive a clock. In this case, the module's state is not retained. This configuration provides the lowest power consumption state. 1 2 P2 RW 1 Timer 3 module is powered, but does not receive a clock.
PAGE 463
Tiva™ TM4C129ENCPDT Microcontroller Register 146: General-Purpose Input/Output Power Control (PCGPIO), offset 0x908 Important: The GPIO modules do not currently provide the ability to respond to the power down request. Setting a bit in this register has no effect on power consumption. This register is defined for future software compatibility. The PCGPIO register controls the power applied to the GPIO module.
PAGE 464
System Control Bit/Field Name Type Reset Description 31:15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 P14 RW 1 GPIO Port Q Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCGPIO, SCGCGPIO or DCGCGPIO register is clear.
PAGE 465
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 10 P10 RW 1 Description GPIO Port L Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCGPIO, SCGCGPIO or DCGCGPIO register is clear. Value Description 0 GPIO Port L is not powered and does not receive a clock. In this case, the module's state is not retained. This configuration provides the lowest power consumption state. 1 9 P9 RW 1 GPIO Port L is powered, but does not receive a clock.
PAGE 466
System Control Bit/Field Name Type Reset 6 P6 RW 1 Description GPIO Port G Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCGPIO, SCGCGPIO or DCGCGPIO register is clear. Value Description 0 GPIO Port G is not powered and does not receive a clock. In this case, the module's state is not retained. This configuration provides the lowest power consumption state. 1 5 P5 RW 1 GPIO Port G is powered, but does not receive a clock.
PAGE 467
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 2 P2 RW 1 Description GPIO Port C Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCGPIO, SCGCGPIO or DCGCGPIO register is clear. Value Description 0 GPIO Port C is not powered and does not receive a clock. In this case, the module's state is not retained. This configuration provides the lowest power consumption state. 1 1 P1 RW 1 GPIO Port C is powered, but does not receive a clock.
PAGE 468
System Control Register 147: Micro Direct Memory Access Power Control (PCDMA), offset 0x90C Important: The µDMA module does not currently provide the ability to respond to the power down request. Setting a bit in this register has no effect on power consumption. This register is defined for future software compatibility. The PCDMA register controls the power applied to the DMA module.
PAGE 469
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset Description 31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 P0 RW 1 μDMA Module Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCDMA, SCGCDMA or DCGCDMA register is clear.
PAGE 470
System Control Register 148: External Peripheral Interface Power Control (PCEPI), offset 0x910 Important: The EPI module does not currently provide the ability to respond to the power down request. Setting a bit in this register has no effect on power consumption. This register is defined for future software compatibility. The PCEPI register controls the power applied to the EPI module.
PAGE 471
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset Description 31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 P0 RW 1 EPI Module Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCEPI, SCGCEPI or DCGCEPI register is clear.
PAGE 472
System Control Register 149: Hibernation Power Control (PCHIB), offset 0x914 Important: The Hibernation module does not currently provide the ability to respond to the power down request. Setting a bit in this register has no effect on power consumption. This register is defined for future software compatibility. The PCHIB register controls the power applied to the HIB module.
PAGE 473
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 0 P0 RW 1 Description Hibernation Module Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCHIB, SCGCHIB or DCGCHIB register is clear. Value Description 0 The HIB module is not powered and does not receive a clock. In this case, the module's state is not retained. This configuration provides the lowest power consumption state. 1 The HIB module is powered, but does not receive a clock.
PAGE 474
System Control Register 150: Universal Asynchronous Receiver/Transmitter Power Control (PCUART), offset 0x918 Important: The UART module does not currently provide the ability to respond to the power down request. Setting a bit in this register has no effect on power consumption. This register is defined for future software compatibility. The PCUART register controls the power applied to the UART module.
PAGE 475
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset Description 31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 P7 RW 1 UART Module 7 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCUART, SCGCUART or DCGCUART register is clear.
PAGE 476
System Control Bit/Field Name Type Reset 3 P3 RW 1 Description UART Module 3 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCUART, SCGCUART or DCGCUART register is clear. Value Description 0 The UART module 3 is not powered and does not receive a clock. In this case, the module's state is not retained. This configuration provides the lowest power consumption state. 1 2 P2 RW 1 The UART module 3 is powered, but does not receive a clock.
PAGE 477
Tiva™ TM4C129ENCPDT Microcontroller Register 151: Synchronous Serial Interface Power Control (PCSSI), offset 0x91C Important: The SSI module does not currently provide the ability to respond to the power down request. Setting a bit in this register has no effect on power consumption. This register is defined for future software compatibility. The PCSSI register controls the power applied to the SSI module.
PAGE 478
System Control Bit/Field Name Type Reset Description 31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 P3 RW 1 SSI Module 3 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCSSI, SCGCSSI or DCGCSSI register is clear.
PAGE 479
Tiva™ TM4C129ENCPDT Microcontroller Register 152: Inter-Integrated Circuit Power Control (PCI2C), offset 0x920 Important: The I2C module does not currently provide the ability to respond to the power down request. Setting a bit in this register has no effect on power consumption. This register is defined for future software compatibility. The PCI2C register controls the power applied to the I2C module.
PAGE 480
System Control Bit/Field Name Type Reset 9 P9 RW 1 Description I2C Module 9 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCI2C, SCGCI2C or DCGCI2C register is clear. Value Description 0 The I2C module 9 is not powered and does not receive a clock. In this case, the module's state is not retained. This configuration provides the lowest power consumption state. 1 8 P8 RW 1 The I2C module 9 is powered, but does not receive a clock.
PAGE 481
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 5 P5 RW 1 Description I2C Module 5 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCI2C, SCGCI2C or DCGCI2C register is clear. Value Description 0 The I2C module 5 is not powered and does not receive a clock. In this case, the module's state is not retained. This configuration provides the lowest power consumption state. 1 4 P4 RW 1 The I2C module 5 is powered, but does not receive a clock.
PAGE 482
System Control Bit/Field Name Type Reset 1 P1 RW 1 Description I2C Module 1 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCI2C, SCGCI2C or DCGCI2C register is clear. Value Description 0 The I2C module 1 is not powered and does not receive a clock. In this case, the module's state is not retained. This configuration provides the lowest power consumption state. 1 0 P0 RW 1 The I2C module 1 is powered, but does not receive a clock.
PAGE 483
Tiva™ TM4C129ENCPDT Microcontroller Register 153: Universal Serial Bus Power Control (PCUSB), offset 0x928 The PCUSB register controls the power applied to the USB module. The function of this bit depends on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the corresponding bits in the RCGCUSB, SCGCUSB and DCGCUSB registers.
PAGE 484
System Control Bit/Field Name Type Reset 0 P0 RW 1 Description USB Module Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCUSB, SCGCUSB or DCGCUSB register is clear. Value Description 0 The USB module is not powered and does not receive a clock. In this case, the module's state is not retained. This configuration provides the lowest power consumption state. 1 The USB module is powered, but does not receive a clock. In this case, the module is inactive.
PAGE 485
Tiva™ TM4C129ENCPDT Microcontroller Register 154: Ethernet PHY Power Control (PCEPHY), offset 0x930 The PCEPHY register controls the power applied to the EEPROM module. The function of this bit depends on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the corresponding bits in the RCGCEPHY, SCGCEPHY and DCGCEPHY registers.
PAGE 486
System Control Bit/Field Name Type Reset Description 31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 P0 RW 0 Ethernet PHY Module Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCEPHY, SCGCEPHY or DCGCEPHY register is clear.
PAGE 487
Tiva™ TM4C129ENCPDT Microcontroller Register 155: Controller Area Network Power Control (PCCAN), offset 0x934 The PCCAN register controls the power applied to the CAN module. The function of this bit depends on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the corresponding bits in the RCGCCAN, SCGCCAN and DCGCCAN registers.
PAGE 488
System Control Bit/Field Name Type Reset 1 P1 RW 1 Description CAN Module 1 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCCAN, SCGCCAN or DCGCCAN register is clear. Value Description 0 The CAN module 1 is not powered and does not receive a clock. In this case, the module's state is not retained. This configuration provides the lowest power consumption state. 1 0 P0 RW 1 The CAN module 1 is powered, but does not receive a clock.
PAGE 489
Tiva™ TM4C129ENCPDT Microcontroller Register 156: Analog-to-Digital Converter Power Control (PCADC), offset 0x938 Important: The ADC module does not currently provide the ability to respond to the power down request. Setting a bit in this register has no effect on power consumption. This register is defined for future software compatibility. The PCADC register controls the power applied to the ADC module.
PAGE 490
System Control Bit/Field Name Type Reset Description 31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 P1 RW 1 ADC Module 1 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCADC, SCGCADC or DCGCADC register is clear.
PAGE 491
Tiva™ TM4C129ENCPDT Microcontroller Register 157: Analog Comparator Power Control (PCACMP), offset 0x93C Important: The ACMP module does not currently provide the ability to respond to the power down request. Setting a bit in this register has no effect on power consumption. This register is defined for future software compatibility. The PCACMP register controls the power applied to the ACMP module.
PAGE 492
System Control Bit/Field Name Type Reset 0 P0 RW 1 Description Analog Comparator Module 0 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCACMP, SCGCACMP or DCGCACMP register is clear. Value Description 0 The Analog Comparator module is not powered and does not receive a clock. In this case, the module's state is not retained. This configuration provides the lowest power consumption state.
PAGE 493
Tiva™ TM4C129ENCPDT Microcontroller Register 158: Pulse Width Modulator Power Control (PCPWM), offset 0x940 Important: The PWM module does not currently provide the ability to respond to the power down request. Setting a bit in this register has no effect on power consumption. This register is defined for future software compatibility. The PCPWM register controls the power applied to the PWM module.
PAGE 494
System Control Bit/Field Name Type Reset 0 P0 RW 1 Description PWM Module 0 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCPWM, SCGCPWM or DCGCPWM register is clear. Value Description 0 The PWM module 0 is not powered and does not receive a clock. In this case, the module's state is not retained. This configuration provides the lowest power consumption state. 1 The PWM module 0 is powered, but does not receive a clock.
PAGE 495
Tiva™ TM4C129ENCPDT Microcontroller Register 159: Quadrature Encoder Interface Power Control (PCQEI), offset 0x944 Important: The QEI module does not currently provide the ability to respond to the power down request. Setting a bit in this register has no effect on power consumption. This register is defined for future software compatibility. The PCQEI register controls the power applied to the QEI module.
PAGE 496
System Control Bit/Field Name Type Reset Description 31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 P0 RW 1 QEI Module 0 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCQEI, SCGCQEI or DCGCQEI register is clear. Value Description 0 QEI module 0 is not powered and does not receive a clock.
PAGE 497
Tiva™ TM4C129ENCPDT Microcontroller Register 160: EEPROM Power Control (PCEEPROM), offset 0x958 Important: The EEPROM module does not currently provide the ability to respond to the power down request. Setting a bit in this register has no effect on power consumption. This register is defined for future software compatibility. The PCEEPROM register controls the power applied to the EEPROM module.
PAGE 498
System Control Bit/Field Name Type Reset 0 P0 RW 1 Description EEPROM Module 0 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCEEPROM, SCGCEEPROM or DCGCEEPROM register is clear. Value Description 0 The EEPROM module is not powered and does not receive a clock. In this case, the module's state is not retained. This configuration provides the lowest power consumption state. 1 The EEPROM module is powered, but does not receive a clock.
PAGE 499
Tiva™ TM4C129ENCPDT Microcontroller Register 161: CRC and Cryptographic Modules Power Control (PCCCM), offset 0x974 The PCCCM register controls the power applied to the CRC and AES, DES, and SHA/MD5 modules. The function of this bit depends on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the corresponding bits in the RCGCCCM, SCGCCCM and DCGCCCM registers.
PAGE 500
System Control Bit/Field Name Type Reset 0 P0 RW 1 Description CRC and Cryptographic Modules Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCCCM, SCGCCCM or DCGCCCM register is clear. Value Description 0 The CRC, AES, DES, and SHA/MD5 modules are not powered and do not receive a clock. In this case, the module's state is not retained. This configuration provides the lowest power consumption state.
PAGE 501
Tiva™ TM4C129ENCPDT Microcontroller Register 162: Ethernet MAC Power Control (PCEMAC), offset 0x99C The PCEMAC register controls the power applied to the EMAC module. The function of this bit depends on the current state of the device (Run, Sleep or Deep-Sleep mode) and value of the corresponding bits in the RCGCEMAC, SCGCEMAC and DCGCEMAC registers.
PAGE 502
System Control Bit/Field Name Type Reset 0 P0 RW 1 Description Ethernet MAC Module 0 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCEMAC, SCGCEMAC or DCGCEMAC register is clear. Value Description 0 Ethernet MAC Module 0 is not powered and does not receive a clock. In this case, the module's state is not retained. This configuration provides the lowest power consumption state. 1 Ethernet MAC module 0 is powered, but does not receive a clock.
PAGE 503
Tiva™ TM4C129ENCPDT Microcontroller Register 163: Watchdog Timer Peripheral Ready (PRWD), offset 0xA00 The PRWD register indicates whether the watchdog modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCWD bit is changed from 0 to 1. A Run mode clocking change is initiated if the corresponding RCGCWD bit is changed.
PAGE 504
System Control Register 164: 16/32-Bit General-Purpose Timer Peripheral Ready (PRTIMER), offset 0xA04 The PRGPT32 register indicates whether the timer modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCGPT32 bit is changed from 0 to 1. A Run mode clocking change is initiated if the corresponding RCGCGPT32 bit is changed.
PAGE 505
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 R4 RO 0 Description 16/32-Bit General-Purpose Timer 4 Peripheral Ready Value Description 3 R3 RO 0 0 16/32-bit timer module 4 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 16/32-bit timer module 4 is ready for access. 16/32-Bit General-Purpose Timer 3 Peripheral Ready Value Description 2 R2 RO 0 0 16/32-bit timer module 3 is not ready for access.
PAGE 506
System Control Register 165: General-Purpose Input/Output Peripheral Ready (PRGPIO), offset 0xA08 The PRGPIO register indicates whether the GPIO modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCGPIO bit is changed from 0 to 1. A Run mode clocking change is initiated if the corresponding RCGCGPIO bit is changed. A reset change is initiated if the corresponding SRGPIO bit is changed from 0 to 1.
PAGE 507
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 11 R11 RO 0 Description GPIO Port M Peripheral Ready Value Description 10 R10 RO 0 0 GPIO Port M is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 GPIO Port M is ready for access. GPIO Port L Peripheral Ready Value Description 9 R9 RO 0 0 GPIO Port L is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence.
PAGE 508
System Control Bit/Field Name Type Reset 4 R4 RO 0 Description GPIO Port E Peripheral Ready Value Description 3 R3 RO 0 0 GPIO Port E is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 GPIO Port E is ready for access. GPIO Port D Peripheral Ready Value Description 2 R2 RO 0 0 GPIO Port D is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 GPIO Port D is ready for access.
PAGE 509
Tiva™ TM4C129ENCPDT Microcontroller Register 166: Micro Direct Memory Access Peripheral Ready (PRDMA), offset 0xA0C The PRDMA register indicates whether the μDMA module is ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCDMA bit is changed from 0 to 1. A Run mode clocking change is initiated if the corresponding RCGCDMA bit is changed.
PAGE 510
System Control Register 167: EPI Peripheral Ready (PREPI), offset 0xA10 The PREPI register indicates whether the EPI module is ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCEPI bit is changed from 0 to 1. A Run mode clocking change is initiated if the corresponding RCGCEPI bit is changed. A reset change is initiated if the corresponding SREPI bit is changed from 0 to 1.
PAGE 511
Tiva™ TM4C129ENCPDT Microcontroller Register 168: Hibernation Peripheral Ready (PRHIB), offset 0xA14 The PRHIB register indicates whether the Hibernation module is ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCHIB bit is changed from 0 to 1. A Run mode clocking change is initiated if the corresponding RCGCHIB bit is changed.
PAGE 512
System Control Register 169: Universal Asynchronous Receiver/Transmitter Peripheral Ready (PRUART), offset 0xA18 The PRUART register indicates whether the UART modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCUART bit is changed from 0 to 1. A Run mode clocking change is initiated if the corresponding RCGCUART bit is changed.
PAGE 513
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 R4 RO 0 Description UART Module 4 Peripheral Ready Value Description 3 R3 RO 0 0 UART module 4 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 UART module 4 is ready for access. UART Module 3 Peripheral Ready Value Description 2 R2 RO 0 0 UART module 3 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence.
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System Control Register 170: Synchronous Serial Interface Peripheral Ready (PRSSI), offset 0xA1C The PRSSI register indicates whether the SSI modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCSSI bit is changed from 0 to 1. A Run mode clocking change is initiated if the corresponding RCGCSSI bit is changed. A reset change is initiated if the corresponding SRSSI bit is changed from 0 to 1.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 0 R0 RO 0 Description SSI Module 0 Peripheral Ready Value Description 0 SSI module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 SSI module 0 is ready for access.
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System Control Register 171: Inter-Integrated Circuit Peripheral Ready (PRI2C), offset 0xA20 The PRI2C register indicates whether the I2C modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCI2C bit is changed from 0 to 1. A Run mode clocking change is initiated if the corresponding RCGCI2C bit is changed. A reset change is initiated if the corresponding SRI2C bit is changed from 0 to 1.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 6 R6 RO 0 Description I2C Module 6 Peripheral Ready Value Description 5 R5 RO 0 0 I2C module 6 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 I2C module 6 is ready for access. I2C Module 5 Peripheral Ready Value Description 4 R4 RO 0 0 I2C module 5 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence.
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System Control Bit/Field Name Type Reset 0 R0 RO 0 Description I2C Module 0 Peripheral Ready Value Description 0 I2C module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 1 I2C module 0 is ready for access.
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Tiva™ TM4C129ENCPDT Microcontroller Register 172: Universal Serial Bus Peripheral Ready (PRUSB), offset 0xA28 The PRUSB register indicates whether the USB module is ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCUSB bit is changed from 0 to 1. A Run mode clocking change is initiated if the corresponding RCGCUSB bit is changed.
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System Control Register 173: Ethernet PHY Peripheral Ready (PREPHY), offset 0xA30 The PREPHY register indicates whether the Ethernet PHY module is ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCEPHY bit is changed from 0 to 1. A Run mode clocking change is initiated if the corresponding RCGCEPHY bit is changed. A reset change is initiated if the corresponding SREPHY bit is changed from 0 to 1.
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Tiva™ TM4C129ENCPDT Microcontroller Register 174: Controller Area Network Peripheral Ready (PRCAN), offset 0xA34 The PRCAN register indicates whether the CAN modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCCAN bit is changed from 0 to 1. A Run mode clocking change is initiated if the corresponding RCGCCAN bit is changed.
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System Control Register 175: Analog-to-Digital Converter Peripheral Ready (PRADC), offset 0xA38 The PRADC register indicates whether the ADC modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCADC bit is changed from 0 to 1. A Run mode clocking change is initiated if the corresponding RCGCADC bit is changed. A reset change is initiated if the corresponding SRADC bit is changed from 0 to 1.
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Tiva™ TM4C129ENCPDT Microcontroller Register 176: Analog Comparator Peripheral Ready (PRACMP), offset 0xA3C The PRACMP register indicates whether the analog comparator module is ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCACMP bit is changed from 0 to 1. A Run mode clocking change is initiated if the corresponding RCGCACMP bit is changed.
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System Control Register 177: Pulse Width Modulator Peripheral Ready (PRPWM), offset 0xA40 The PRPWM register indicates whether the PWM modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCPWM bit is changed from 0 to 1. A Run mode clocking change is initiated if the corresponding RCGCPWM bit is changed. A reset change is initiated if the corresponding SRPWM bit is changed from 0 to 1.
PAGE 525
Tiva™ TM4C129ENCPDT Microcontroller Register 178: Quadrature Encoder Interface Peripheral Ready (PRQEI), offset 0xA44 The PRQEI register indicates whether the QEI modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCQEI bit is changed from 0 to 1. A Run mode clocking change is initiated if the corresponding RCGCQEI bit is changed.
PAGE 526
System Control Register 179: EEPROM Peripheral Ready (PREEPROM), offset 0xA58 The PREEPROM register indicates whether the EEPROM module is ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCEEPROM bit is changed from 0 to 1. A Run mode clocking change is initiated if the corresponding RCGCEEPROM bit is changed. A reset change is initiated if the corresponding SREEPROM bit is changed from 0 to 1.
PAGE 527
Tiva™ TM4C129ENCPDT Microcontroller Register 180: CRC and Cryptographic Modules Peripheral Ready (PRCCM), offset 0xA74 The PRCCM register indicates whether the CRC and Cryptographic Modules( AES, DES, and SHA/MD5) are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCCCM bit is changed from 0 to 1. A Run mode clocking change is initiated if the corresponding RCGCCCM bit is changed.
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System Control Register 181: Ethernet MAC Peripheral Ready (PREMAC), offset 0xA9C The PREMAC register indicates whether the Ethernet module is ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A power change is initiated if the corresponding PCEMAC bit is changed from 0 to 1. A Run mode clocking change is initiated if the corresponding RCGCEMAC bit is changed. A reset change is initiated if the corresponding SREMAC bit is changed from 0 to 1.
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Tiva™ TM4C129ENCPDT Microcontroller Register 182: Unique ID 0 (UNIQUEID0), offset 0xF20 Register 183: Unique ID 1 (UNIQUEID1), offset 0xF24 Register 184: Unique ID 2 (UNIQUEID2), offset 0xF28 Register 185: Unique ID 3 (UNIQUEID3), offset 0xF2C These registers contain a unique 128-bit identifier that cannot be modified by the user. This value is unique to each individual die but is not a random value.
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System Control Register 186: Cryptographic Modules Clock Gating Request (CCMCGREQ), offset 0x204 The Cryptographic Modules Clock Gating Request (CCMCGREQ) register is written to enable or disable clock gating in the AES, DES, and SHA/MD5 Module. Cryptographic Modules Clock Gating Request (CCMCGREQ) Base 0x400F.E000 Offset 0x204 Type RW, reset 0x0000.
PAGE 531
Tiva™ TM4C129ENCPDT Microcontroller 6 Processor Support and Exception Module This module is an AHB peripheral that handles system-level Cortex-M4 FPU exceptions. For functions with registers mapped into this aperture, if the function is not available on a device, then all writes to the associated registers are ignored and reads return zeros. 6.1 Functional Description The System Exception module provides control and status of the system-level interrupts.
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Processor Support and Exception Module Register 1: System Exception Raw Interrupt Status (SYSEXCRIS), offset 0x000 The SYSEXCRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt. A write has no effect. System Exception Raw Interrupt Status (SYSEXCRIS) Base 0x400F.9000 Offset 0x000 Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 2 FPIOCRIS RO 0 Description Floating-Point Invalid Operation Raw Interrupt Status Value Description 0 No interrupt 1 A floating-point invalid operation exception has occurred. This bit is cleared by writing a 1 to the IOCIC bit in the SYSEXCIC register. 1 FPDZCRIS RO 0 Floating-Point Divide By 0 Exception Raw Interrupt Status Value Description 0 No interrupt 1 A floating-point divide by 0 exception has occurred.
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Processor Support and Exception Module Register 2: System Exception Interrupt Mask (SYSEXCIM), offset 0x004 The SYSEXCIM register is the interrupt mask set/clear register. On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit prevents the raw interrupt signal from being sent to the interrupt controller. System Exception Interrupt Mask (SYSEXCIM) Base 0x400F.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 2 FPIOCIM RW 0 Description Floating-Point Invalid Operation Interrupt Mask Value Description 1 FPDZCIM RW 0 0 The FPIOCRIS interrupt is suppressed and not sent to the interrupt controller. 1 An interrupt is sent to the interrupt controller when the FPIOCRIS bit in the SYSEXCRIS register is set.
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Processor Support and Exception Module Register 3: System Exception Masked Interrupt Status (SYSEXCMIS), offset 0x008 The SYSEXCMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. System Exception Masked Interrupt Status (SYSEXCMIS) Base 0x400F.9000 Offset 0x008 Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 2 FPIOCMIS RO 0 Description Floating-Point Invalid Operation Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked interrupt was signaled due to an invalid operation. This bit is cleared by writing a 1 to the FPIOCIC bit in the SYSEXCIC register.
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Processor Support and Exception Module Register 4: System Exception Interrupt Clear (SYSEXCIC), offset 0x00C The SYSEXCIC register is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect. System Exception Interrupt Clear (SYSEXCIC) Base 0x400F.9000 Offset 0x00C Type W1C, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller 7 Hibernation Module The Hibernation Module manages removal and restoration of power to provide a means for reducing system power consumption. When the processor and peripherals are idle, power can be completely removed with only the Hibernation module remaining powered. Power can be restored based on an external signal or at a certain time using the built-in Real-Time Clock (RTC).
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Hibernation Module – Hibernation clock input failure detect with a switch to the internal oscillator on detection ■ RTC operational and hibernation memory valid as long as VDD or VBAT is valid ■ Low-battery detection, signaling, and interrupt generation, with optional wake on low battery ■ GPIO pin state can be retained during hibernation ■ Clock source from an internal low frequency oscillator (HIB LFIOSC) or a 32.
PAGE 541
Tiva™ TM4C129ENCPDT Microcontroller 7.1 Block Diagram Figure 7-1. Hibernation Module Block Diagram Alternate Clock for LPC Clock Source for System Clock To GPIO Module HIBCTL.CLK32EN & HIBCTL.OSCSEL HIBCC. ALTCLK1EN Low Frequency Oscillator XOSC0 32.786 kHz Oscillator I/O Config. HIBCC. SYSCLKEN HIBIO Interrupts HIBIM HIBRIS HIBMIS HIBIC Pre-Divider XOSC1 HIBRTCT HIBCTL.CLK32EN & HIBCTL.
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Hibernation Module Note: In addition to the Hibernation signals that are part of the Hibernation Module, GPIO pins K[7:4] can be configured as external wake sources. Refer to “Waking from Hibernate” on page 554 for more information. Note: Port pins PM[7:4] operate as Fast GPIO pads but support only 2-, 4-, 6-, and 8-mA drive capability. 10- and 12-mA drive are not supported. All standard GPIO register controls, except for the GPIODR12R register, apply to these port pins.
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Tiva™ TM4C129ENCPDT Microcontroller ■ The user initiates hibernation by setting the HIBREQ bit in the Hibernation Control (HIBCTL) register ■ Power is arbitrarily removed from VDD while a valid VBAT is applied Once in hibernation, the module signals an external voltage regulator to turn the power back on when an external pin (WAKE, RST or a wake-enabled GPIO pin) is asserted or when the internal RTC reaches a certain value.
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Hibernation Module Table 7-2. HIB Clock Source Configurations (continued) HIB Clock Source a Low-frequency internal oscillator (HIB LFIOSC) CLK32EN OSCSEL OSCBYP 1 1 0 a. The frequency can have wide variations; refer to “Hibernation Clock Source Specifications” on page 1961 for more details. To use an external crystal, a 32.768-kHz crystal is connected to the XOSC0 and XOSC1 pins. Alternatively, a 32.768-kHz oscillator can be connected to the XOSC0 pin, leaving XOSC1 unconnected.
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Tiva™ TM4C129ENCPDT Microcontroller Figure 7-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source Tiva™ Microcontroller Regulator or Switch Input Voltage IN OUT VDD EN XOSC0 X1 XOSC1 C1 C2 GNDX HIB RBAT WAKE Open drain external wake up circuit Note: VBAT 3V Battery CBAT GND RPU Some devices may not supply the GNDX signal. If GNDX is absent, the crystal load capacitors can be tied to GND externally.
PAGE 546
Hibernation Module 7.3.2.1 Hibernate Clock Output RTCOSC The clock source that is configured as the HIB clock has the option of becoming an internal output, RTCOSC, and being selected as the clock source for the system clock. To enable RTCOSC as a system clock source, the SYSCLKEN bit must be set in the Hibernate Clock Control (HIBCC) register. 7.3.
PAGE 547
Tiva™ TM4C129ENCPDT Microcontroller 7.3.4 Battery Management Important: System-level factors may affect the accuracy of the low-battery detect circuit. The designer should consider battery type, discharge characteristics, and a test load during battery voltage measurements. The Hibernation module can be independently powered by a battery or an auxiliary power source using the VBAT pin. The module can monitor the voltage level of the battery and detect when the voltage drops below VLOWBAT.
PAGE 548
Hibernation Module If the RTC is enabled, only a cold POR, where both VBAT and VDD are removed, resets the RTC registers. If any other reset occurs while the RTC is enabled, such as an external RST assertion or BOR reset, the RTC is not reset. The RTC registers can be reset under any type of system reset as long as the RTC, external wake pins and tamper pins are not enabled. A buffered version of the 32.
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Tiva™ TM4C129ENCPDT Microcontroller When reading the Hibernation Calendar n (HIBCALn) registers, the status of the VALID bit in the HIBCAL0/1 register must be checked to ensure the registers are in sync before reading.
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Hibernation Module Figure 7-5. Counter Behavior with a TRIM Value of 0x8002 RTCCLK RTCC[6:0] RTCSSC 0x00 0x01 0x7FFD 0x7FFE 0x7FFF 0x7FFD 0x7FFE 0x7FFF 0x02 0x0 0x7FFE 0x7FFF 0x0 0x1 In the case of a trim value below 0x7FFF, the RTCSSC value is advanced from 0x7FFF to the trim value while the RTCC value is incremented from 0x0 to 0x1. If the match value is within that range, the match interrupt is not triggered.
PAGE 551
Tiva™ TM4C129ENCPDT Microcontroller 7.3.6.2 Functional Description The Tamper module provides mechanisms to detect, respond, and log system tamper events. A tamper event is detected by state transitions on up to four GPIOs. The module may respond to a tamper event by clearing all or part of the hibernate module memory, generating a tamper event signal to the System Control module. The event will also be logged with a RTC time stamp to allow for tamper investigation.
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Hibernation Module ■ Tamper Register Status The tamper status is indicated by the STATE bit field of the HIB Tamper Status (HIBTPSTAT) register. The register bits are reset to 0x0 on cold POR. When the tamper I/O is enabled/configured, the STATE field shows 0x1. The STATE field is set to 0x2 when a tamper event is detected. The software may reset the trigger source and the STATE field by writing to the TPCLR bit in the HIBTPCTL register.
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Tiva™ TM4C129ENCPDT Microcontroller Tamper I/O Control Up to four tamper I/Os are available. These signals are individually enabled and the detection level can be configured per pin. Enabling the tamper IO will override all settings made in the GPIO module. Each tamper IO has a weak pull-up. Tamper Clocking The Hibernate clock is the clock source for the Tamper module. When an external oscillator is used and tamper is enabled, the external oscillator is monitored by the Tamper module.
PAGE 554
Hibernation Module 7.3.9 Power Control Using VDD3ON Mode The Hibernation module may also be configured to cut power to all internal modules during Hibernate mode. While in this state, if VDD3ON is set in the HIBCTL register, all pins are held in the state they were in prior to entering hibernation. For example, inputs remain inputs; outputs driven high remain driven high, and so on.
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Tiva™ TM4C129ENCPDT Microcontroller To use the RST pin as a wake source, the WURSTEN bit must be set in the Hibernate I/O Configuration (HIBIO) register and the WUUNLK bit must be set in the same register. To enable any of the assigned GPIO pins as a wake source, the WUUNLK bit must be set in the HIBIO register and the wake configuration must be programmed through the GPIOWAKEPEN and GPIOWAKELVL registers in the GPIO module.
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Hibernation Module If VDD is arbitrarily removed while a Flash memory or HIBDATA register write operation is in progress, the write operation must be retried after VDD is reapplied. 7.3.
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Tiva™ TM4C129ENCPDT Microcontroller If a 32.768-kHz single-ended oscillator is used as the Hibernation module clock source, then perform the following steps: 1. Write 0x0000.0010 to the HIBIM register to enable the WC interrupt. 2. Write 0x0001.0040 to the HIBCTL register at offset 0x10 to enable the oscillator input and bypass the on-chip oscillator. 3. Wait until the WC interrupt in the HIBMIS register has been triggered before performing any other operations with the Hibernation module.
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Hibernation Module 4. Write any data to be retained during hibernation to the HIBDATA register at offsets 0x030-0x06F. 5. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004B to the HIBCTL register at offset 0x010. 7.4.4 External Wake-Up from Hibernation Use the following steps to implement the Hibernation module with the external WAKE pin as the wake-up source for the microcontroller: 1. Write 0x0000.0040 to the HIBCTL register at offset 0x010 to enable 32.
PAGE 559
Tiva™ TM4C129ENCPDT Microcontroller 6. The hibernation sequence may be initiated by writing 0x4000.0152 to the HIBCTL register. Note for Port M external wake, the user must enable VDD3ON mode and set the RETCLR bit in the HIBCTL register. 7.4.5 RTC or External Wake-Up from Hibernation 1. Write 0x0000.0040 to the HIBCTL register at offset 0x010 to enable 32.768-kHz Hibernation oscillator. 2.
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Hibernation Module are accessed. In addition, the CLK32EN bit in the HIBCTL register must be set before accessing any other Hibernation module register. Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module registers are on the Hibernation module clock domain and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed.
PAGE 561
Tiva™ TM4C129ENCPDT Microcontroller Table 7-3. Hibernation Module Register Map (continued) Offset Name Type Reset 0x02C HIBIO RW 0x8000.0000 0x0300x06F HIBDATA RW - 0x300 HIBCALCTL RW 0x310 HIBCAL0 0x314 Description See page Hibernation IO Configuration 580 Hibernation Data 582 0x0000.0000 Hibernation Calendar Control 583 RO 0x0000.0000 Hibernation Calendar 0 584 HIBCAL1 RO 0x0000.0000 Hibernation Calendar 1 586 0x320 HIBCALLD0 WO 0x0000.
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Hibernation Module Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 This register is the current 32-bit value of the RTC counter. The RTC counter consists of a 32-bit seconds counter and a 15-bit sub seconds counter. The RTC counters are reset by the Hibernation module reset. The RTC 32-bit seconds counter can be set by the user using the HIBRTCLD register. When the 32-bit seconds counter is set, the 15-bit sub second counter is cleared.
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Tiva™ TM4C129ENCPDT Microcontroller Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 This register is the 32-bit seconds match register for the RTC counter. The 15-bit sub second match value is stored in the reading the RTCSSC field in the HIBRTCSS register and can be used in conjunction with this register for a more precise time match.
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Hibernation Module Register 3: Hibernation RTC Load (HIBRTCLD), offset 0x00C This register is used to load a 32-bit value loaded into the RTC counter. The load occurs immediately upon this register being written. When this register is written, the 15-bit sub seconds counter is also cleared. Note: This register is protected from errant code by using the HIBLOCK register. This register is write-only; any reads to this register read back as zeros.
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Tiva™ TM4C129ENCPDT Microcontroller Register 4: Hibernation Control (HIBCTL), offset 0x010 This register is the control register for the Hibernation module. This register must be written last before a hibernate event is issued. Writes to other registers after the HIBREQ bit is set are not guaranteed to complete before hibernation is entered. Note: Writes to this register have special timing requirements.
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Hibernation Module Bit/Field Name Type Reset 30 RETCLR RW 0 Description GPIO Retention/Clear This bit is used when the VDD3ON bit is set.This bit is must be set when entering the hibernate state when the VDD3ON bit is set. This does not affect behavior when VDD3ON is clear. Note: This bit must be set when enabling VDD3ON mode. Value Description 0 GPIO retention is released when power is reapplied. The GPIOs are initialized to default values. 1 GPIO retention set until software clears this bit.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 15 reserved RO 0 14:13 VBATSEL RW 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Select for Low-Battery Comparator This field selects the battery level that is used when checking the battery status.
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Hibernation Module Bit/Field Name Type Reset 8 VDD3ON RW 0 Description VDD Powered Value Description 0 The internal switches are not used. The HIB signal should be used to control an external switch or regulator. 1 The internal switches control the power to the on-chip modules (VDD3ON mode). Regardless of the status of the VDD3ON bit, the HIB signal is asserted during Hibernate mode. Thus, when VDD3ON is set, the HIB signal should not be connected to the 3.3V regulator, and the 3.
PAGE 569
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3 RTCWEN RW 0 Description RTC Wake-up Enable Value Description 0 An RTC match event has no effect on hibernation. 1 An RTC match event (the value the HIBRTCC register matches the value of the HIBRTCM0 register and the value of the RTCSSC field matches the RTCSSM field in the HIBRTCSS register) takes the microcontroller out of hibernation. 2 reserved RO 0 Software should not rely on the value of a reserved bit.
PAGE 570
Hibernation Module Register 5: Hibernation Interrupt Mask (HIBIM), offset 0x014 This register is the interrupt mask register for the Hibernation module interrupt sources. Each bit in this register masks the corresponding bit in the Hibernation Raw Interrupt Status (HIBRIS) register. If a bit is unmasked, the interrupt is sent to the interrupt controller. If the bit is masked, the interrupt is not sent to the interrupt controller.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 5 PADIOWK RW 0 Description Pad I/O Wake-Up Interrupt Mask Value Description 4 WC RW 0 0 The PADIOWK interrupt is suppressed and not sent to the interrupt controller. 1 An interrupt is sent to the interrupt controller when the PADIOWK bit in the HIBRIS register is set. External Write Complete/Capable Interrupt Mask Value Description 3 EXTW RW 0 0 The WC interrupt is suppressed and not sent to the interrupt controller.
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Hibernation Module Register 6: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 This register is the raw interrupt status for the Hibernation module interrupt sources. Each bit can be masked by clearing the corresponding bit in the HIBIM register. When a bit is masked, the interrupt is not sent to the interrupt controller. Bits in this register are cleared by writing a 1 to the corresponding bit in the Hibernation Interrupt Clear (HIBIC) register or by entering hibernation.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 WC RO 0 Description Write Complete/Capable Raw Interrupt Status Value Description 0 The WRC bit in the HIBCTL has not been set. 1 The WRC bit in the HIBCTL has been set. This bit is cleared by writing a 1 to the WC bit in the HIBIC register. 3 EXTW RO 0 External Wake-Up Raw Interrupt Status Note that a wake signal source must be cleared by the application after the interrupt has been registered.
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Hibernation Module Register 7: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C This register is the masked interrupt status for the Hibernation module interrupt sources. Bits in this register are the AND of the corresponding bits in the HIBRIS and HIBIM registers. When both corresponding bits are set, the bit in this register is set, and the interrupt is sent to the interrupt controller. Hibernation Masked Interrupt Status (HIBMIS) Base 0x400F.C000 Offset 0x01C Type RO, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 WC RO 0 Description Write Complete/Capable Masked Interrupt Status Value Description 0 The WRC bit has not been set or the interrupt is masked. 1 An unmasked interrupt was signaled due to the WRC bit being set. This bit is cleared by writing a 1 to the WC bit in the HIBIC register. 3 EXTW RO 0 External Wake-Up Masked Interrupt Status Value Description 0 An external wake-up interrupt has not occurred or is masked.
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Hibernation Module Register 8: Hibernation Interrupt Clear (HIBIC), offset 0x020 This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources. Writing a 1 to a bit clears the corresponding interrupt in the HIBRIS register. Note: Writes to the RSTWK, PADIOWK and WC bits of this register are immediate and the status may be read from the HIBRIS and HIBMIS registers without monitoring the WRC bit of the HIBCTL register.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 2 LOWBAT RW1C 0 Description Low Battery Voltage Interrupt Clear Writing a 1 to this bit clears the LOWBAT bit in the HIBRIS and HIBMIS registers. Reads return the raw interrupt status. 1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
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Hibernation Module Register 9: Hibernation RTC Trim (HIBRTCT), offset 0x024 This register contains the value that is used to trim the RTC clock predivider. It represents the computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock cycles, where N is the number of clock cycles to add or subtract every 64 seconds in RTC mode or 60 seconds in calendar mode.
PAGE 579
Tiva™ TM4C129ENCPDT Microcontroller Register 10: Hibernation RTC Sub Seconds (HIBRTCSS), offset 0x028 This register contains the RTC sub seconds counter and match values. The RTC value can be read by first reading the HIBRTCC register, reading the RTCSSC field in the HIBRTCSS register, and then rereading the HIBRTCC register. If the two values for HIBRTCC are equal, the read is valid.
PAGE 580
Hibernation Module Register 11: Hibernation IO Configuration (HIBIO), offset 0x02C This register is used to lock and unlock the external wake pin levels and enable the external RST pin and/or GPIO pins, Port K[7:4], as valid external WAKE sources. Note: This register is in the system clock domain and does not require monitoring the WRC bit of the HIBCTL register before issuing a read or write of this register. Writes to this register are immediate.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 0 WUUNLK RW 0 Description I/O Wake Pad Configuration Enable Value Description 0 The I/O WAKE configuration set by the WURSTEN bit or in the GPIO module registers GPIOWAKEPEN and GPIOWAKELVL is ignored. 1 Implement the I/O WAKE configuration, level and enables for the external RST pin and/or GPIO wake-enabled pins. Note: This bit must be cleared before issuing a hibernate request by setting the HIBREQ bit in the HIBCTL register.
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Hibernation Module Register 12: Hibernation Data (HIBDATA), offset 0x030-0x06F This address space is implemented as a 16x32-bit memory (64 bytes). It can be loaded by the system processor in order to store state information and retains its state during a power cut operation as long as a battery is present. HIBDATA registers 0x050 to 0x064 (upper eight words) may only be accessed using the processor privileged mode (default).
PAGE 583
Tiva™ TM4C129ENCPDT Microcontroller Register 13: Hibernation Calendar Control (HIBCALCTL), offset 0x300 The Hibernate calendar is enabled by setting the CALEN bit in the HIBCALCTL register. If the BCD bit is set, the fields are reported in BCD format. Hibernation Calendar Control (HIBCALCTL) Base 0x400F.C000 Offset 0x300 Type RW, reset 0x0000.
PAGE 584
Hibernation Module Register 14: Hibernation Calendar 0 (HIBCAL0), offset 0x310 The Hibernation Calendar 0 (HIBCAL0) register is used when the CALEN bit is set in the HIBCALCTL register. Hibernation Calendar 0 (HIBCAL0) Base 0x400F.C000 Offset 0x310 Type RO, reset 0x0000.
PAGE 585
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 13:8 MIN RO 0 Description Minutes This field holds the minute information in hexadecimal. Bits 13:8 correspond to hex values from 0x0 to 0x3b (0 to 59 minutes). 7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
PAGE 586
Hibernation Module Register 15: Hibernation Calendar 1 (HIBCAL1), offset 0x314 The Hibernation Calendar 1 (HIBCAL1) register is used when the CALEN bit is set in the HIBCALCTL register. Hibernation Calendar 1 (HIBCAL1) Base 0x400F.C000 Offset 0x314 Type RO, reset 0x0000.
PAGE 587
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4:0 DOM RO 0 Description Day of Month This field holds the day of the month value in hexadecimal. Bits 4:0 correspond to hex values from 0x1 to 1F (1 to 31 days). The value 0 is used to show an ignore match.
PAGE 588
Hibernation Module Register 16: Hibernation Calendar Load 0 (HIBCALLD0), offset 0x320 The Hibernation Calendar Load (HIBCALLD0) register is used when the CALEN bit is set in the HIBCALCTL register. Note: This register is write-only; any reads to this register read back as zeros. Errant writes to the HIBCALLD0/1 registers are protected by the Hibernate HIBLOCK register. Hibernation Calendar Load 0 (HIBCALLD0) Base 0x400F.C000 Offset 0x320 Type WO, reset 0x0000.
PAGE 589
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 5:0 SEC WO 0 Description Seconds This field holds the seconds value in hexadecimal. Bits 5:0 correspond to hex values from 0x0 to 0x3B (0 to 59 seconds).
PAGE 590
Hibernation Module Register 17: Hibernation Calendar Load (HIBCALLD1), offset 0x324 The Hibernation Calendar Load 1 (HIBCALLD1) register is used when the CALEN bit is set in the HIBCALCTL register. Note: This register is write-only; any reads to this register read back as zeros. Errant writes to the HIBCALLD0/1 registers are protected by the Hibernate HIBLOCK register. Hibernation Calendar Load (HIBCALLD1) Base 0x400F.C000 Offset 0x324 Type WO, reset 0x0000.
PAGE 591
Tiva™ TM4C129ENCPDT Microcontroller Register 18: Hibernation Calendar Match 0 (HIBCALM0), offset 0x330 The Hibernation Calendar Match 0 (HIBCALM0) register is used when the CALEN bit is set in the HIBCALCTL register. This register is loaded with desired match values for calendar mode. Once the HIBCAL0/1 register values equal the HIBCALM0/1 register values, the RTCALT0 bit is set in the HIBRIS register. Note: The day of week, month and year are not included in the match functionality.
PAGE 592
Hibernation Module Bit/Field Name Type Reset 5:0 SEC RW 0 Description Seconds This field holds the match value for seconds. The value is represented in hexadecimal. Bits 5:0 correspond to hex values from 0x0 to 0x3b (0 to 59 seconds). To ignore the hours match, write this field to all 1s.
PAGE 593
Tiva™ TM4C129ENCPDT Microcontroller Register 19: Hibernation Calendar Match 1 (HIBCALM1), offset 0x334 The Hibernation Calendar Match 1 (HIBCALM1) register is used when the CALEN bit is set in the HIBCALCTL register. This register is loaded with desired match values for calendar mode. Once the HIBCAL0/1 register values equal the HIBCALM0/1 register values, the RTCALT0 bit is set in the HIBRIS register. Note: The day of week, month and year are not included in the match functionality.
PAGE 594
Hibernation Module Register 20: Hibernation Lock (HIBLOCK), offset 0x360 Writing 0xA335.9554 to the HIBLOCK register enables write access to the HIBRTCLD, HIBCALLD0, HIBCALLD1 and Tamper registers. Writing any other value to the HIBLOCK register re-enables the locked state for register writes to all the other registers. Reading the HIBLOCK register returns the lock status rather than the 32-bit value written. Therefore, when write accesses are disabled, reading the HIBLOCK register returns 0x0000.
PAGE 595
Tiva™ TM4C129ENCPDT Microcontroller Register 21: HIB Tamper Control (HIBTPCTL), offset 0x400 The Tamper Control (HIBTPCTL) register provides control of the module. Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module registers are on the Hibernation module clock domain and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed.
PAGE 596
Hibernation Module Bit/Field Name Type Reset Description 7:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 TPCLR W1C 0 Tamper Event Clear Writing a 1 to this bit clears the tamper event. The status of the clear is reflected in the STATE bit field. 3:1 reserved RO 0 Software should not rely on the value of a reserved bit.
PAGE 597
Tiva™ TM4C129ENCPDT Microcontroller Register 22: HIB Tamper Status (HIBTPSTAT), offset 0x404 The HIB Tamper Status (HIBTPCTL) register provides status of the module. Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module registers are on the Hibernation module clock domain and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed.
PAGE 598
Hibernation Module Bit/Field Name Type Reset 0 XOSCFAIL RW1C 0 Description External Oscillator Failure Write a 1 to this bit to clear it. Value Description 0 External oscillator is valid.
PAGE 599
Tiva™ TM4C129ENCPDT Microcontroller Register 23: HIB Tamper I/O Control (HIBTPIO), offset 0x410 The HIB Tamper I/O Control (HIBTPIO) register provides control of the Tamper I/O. Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module registers are on the Hibernation module clock domain and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed.
PAGE 600
Hibernation Module Bit/Field Name Type Reset 25 LEV3 RW 0 Description TMPR3 Trigger Level Value Description 24 EN3 RW 0 0 Trigger on level low 1 Trigger on level high TMPR3 Enable Value Description 0 Detect disabled 1 Detect enabled 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
PAGE 601
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 11 GFLTR1 RW 0 Description TMPR1 Glitch Filtering Value Description 10 PUEN1 RW 0 0 A trigger match level is ignored until the TMPR1 signal is stable for two hibernate clocks. 1 A trigger match level is ignored until the TMPR1 signal is stable for 3,071 Hibernate Clocks (93.7ms using 32.768 kHz).
PAGE 602
Hibernation Module Bit/Field Name Type Reset 1 LEV0 RW 0 Description TMPR0 Trigger Level Value Description 0 EN0 RW 0 0 Trigger on level low 1 Trigger on level high TMPR0 Enable Value Description 0 Detect disabled 1 Detect enabled 602 June 18, 2014 Texas Instruments-Production Data
PAGE 603
Tiva™ TM4C129ENCPDT Microcontroller Register 24: HIB Tamper Log 0 (HIBTPLOG0), offset 0x4E0 Register 25: HIB Tamper Log 2 (HIBTPLOG2), offset 0x4E8 Register 26: HIB Tamper Log 4 (HIBTPLOG4), offset 0x4F0 Register 27: HIB Tamper Log 6 (HIBTPLOG6), offset 0x4F8 The HIB Tamper Log (HIBTPLOG) even registers capture the time information during a tamper event. Up to four tamper logs can be stored. The HIBTPLOG registers are cleared when the TPCLR bit is written in the HIBTPCTL register.
PAGE 604
Hibernation Module Register 28: HIB Tamper Log 1 (HIBTPLOG1), offset 0x4E4 Register 29: HIB Tamper Log 3 (HIBTPLOG3), offset 0x4EC Register 30: HIB Tamper Log 5 (HIBTPLOG5), offset 0x4F4 Register 31: HIB Tamper Log 7 (HIBTPLOG7), offset 0x4FC The HIB Tamper Log (HIBTPLOGn) odd registers capture the trigger information during a tamper event. Up to four tamper logs can be stored. The HIBTPLOG registers are cleared when the TPCLR bit is set to 1 in the HIBTPCTL register.
PAGE 605
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1 TRIG1 RO 0 Description Status of TMPR[1] Trigger Value Description 0 TRIG0 RO 0 0 Default 1 A tamper event has been detected on TMPR[1] Status of TMPR[0] Trigger Value Description 0 Default 1 A tamper event has been detected on TMPR[0] June 18, 2014 605 Texas Instruments-Production Data
PAGE 606
Hibernation Module Register 32: Hibernation Peripheral Properties (HIBPP) , offset 0xFC0 This register describes the features available within the Hibernation Module. Hibernation Peripheral Properties (HIBPP) Base 0x400F.C000 Offset 0xFC0 Type RO, reset 0x0000.
PAGE 607
Tiva™ TM4C129ENCPDT Microcontroller Register 33: Hibernation Clock Control (HIBCC), offset 0xFC8 This register enables alternate clock sources. Note: This register is in the system clock domain. Writes to this register do not require waiting for the WRC bit of the HIBCTL register to be set. Hibernation Clock Control (HIBCC) Base 0x400F.C000 Offset 0xFC8 Type RW, reset 0x0000.
PAGE 608
Internal Memory 8 Internal Memory The TM4C129ENCPDT microcontroller comes with 256 KB of bit-banded SRAM, internal ROM, 1024 KB of Flash memory, and 6KB of EEPROM. The TM4C129ENCPDT microcontroller provides 1024 KB of on-chip Flash memory. The Flash memory is configured as four banks of 16K x 128 bits (4 * 256 KB total) which are two-way interleaved. Memory blocks can be marked as read-only or execute-only, providing different levels of code protection.
PAGE 609
Tiva™ TM4C129ENCPDT Microcontroller Figure 8-1.
PAGE 610
Internal Memory 8.2 Functional Description This section describes the functionality of the SRAM, ROM, Flash, and EEPROM memories. Note: 8.2.1 The μDMA has read-only access to flash (in Run Mode only). SRAM The internal system SRAM of the Tiva™ C Series devices is located at address 0x2000.0000 of the device memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM provides bit-banding technology in the processor.
PAGE 611
Tiva™ TM4C129ENCPDT Microcontroller firmware upgrade mechanism (by calling back to the boot loader). The Peripheral Driver Library APIs in ROM can be called by applications, reducing Flash memory requirements and freeing the Flash memory to be used for other purposes (such as additional features in the application). Advanced Encryption Standard (AES) is a publicly defined encryption standard used by the U.S. Government.
PAGE 612
Internal Memory user interfaces on Tiva™ C Series microcontroller-based boards that have a graphical display (for more information, see the TivaWare™ Graphics Library for C Series User's Guide (literature number SPMU300)). The TivaWare USB Library is a set of data types and functions for creating USB Device, Host or On-The-Go (OTG) applications on Tiva™ C Series microcontroller-based boards (for more information, see the TivaWare™ USB Library for C Series User's Guide (literature number SPMU297)). 8.2.2.
PAGE 613
Tiva™ TM4C129ENCPDT Microcontroller Figure 8-2. Flash Memory Configuration 0x0F.FFFC 0x0F.FFF8 0x0F.FFF4 0x0F.FFF0 0x0F.FFEC 8 KB Sector31-1 Bank 3 0x0F.FFE8 0x0F.FFE4 0x0F.FFE0 8 KB Sector31-1 Bank 2 512 KB High Region 0x08.401C 0x08.4018 0x08.4014 0x08.4010 0x08.400C 0x08.4008 0x08.4004 0x08.4000 0x08.3FFC 0x08.3FF8 0x08.3FF4 0x08.3FF0 0x08.3FEC 0x08.3FE8 0x08.3FE4 0x08.3FE0 0x08.001C 0x08.0018 0x08.0010 0x08.000C 0x08.0008 8 KB Sector 0 Bank 3 0x08.
PAGE 614
Internal Memory Table 8-1. MEMTIM0 Register Configuration versus Frequency (continued) CPU Frequency range (f) Time Period Range (t) in ns in MHz 100< f ≤120 Flash Bank Clock High Time (FBCHT) Flash Bank Clock Edge (FBCE) Flash Wait States (FWS) 0x6 0 0x5 10 > t ≥ 8.33 To update the MEMTIM0 register with the new Flash configuration values, the MEMTIMU bit should be set in the Run and Sleep Mode Configuration Register (RSCLKCFG), System Control offset 0x0B0. Note: 8.2.3.
PAGE 615
Tiva™ TM4C129ENCPDT Microcontroller subsystem to fill the next, least-recently used prefetch buffer. Two memory banks are read in parallel to retrieve 256-bits worth of data. If an auto-fill has been started and a miss occurs, the auto-fill completes before the miss is processed. If an auto-fill occurs that hits the prefetch buffer being processed for the auto-fill, then the ICODE bus is stalled until the auto fill is complete and new entry can be accessed.
PAGE 616
Internal Memory Figure 8-6.
PAGE 617
Tiva™ TM4C129ENCPDT Microcontroller while programming the flash contents. If data needs to be recovered, a hot swap can be done by setting the FMME bit in the FLASHCONF register to ensure the flash banks are idle during the swap. The prefetch buffers must be invalidated during the execution of a hot swap. Next, the address translation logic decodes up to 512 KB from the upper banks to the lower banks. Once the banks are swapped, the mirrored flash image is then used.
PAGE 618
Internal Memory the corresponding block may not be changed. When a block is protected by clearing bits in both FMPPEn and FMPREn registers, execute-only protection can be achieved. ■ Flash Memory Protection Read Enable (FMPREn): If a bit is set in this register, the corresponding block may be executed or read by software or debuggers.
PAGE 619
Tiva™ TM4C129ENCPDT Microcontroller is blocked, and the processor is prevented from loading the constant data and, therefore, inhibiting correct execution. Therefore, using execute-only protection requires that literal data be handled differently. There are three ways to address this: 1. Use a compiler that allows literal data to be collected into a separate section that is put into one or more read-enabled flash blocks.
PAGE 620
Internal Memory ■ Invalid Data Interrupt: Signals when a bit in Flash that was previously programmed as a 0 is now requested to be programmed as a 1. (INVDRIS). ■ ERASE Operation Interrupt: Indicates an ERASE operation failed. (ERRIS). The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller Masked Interrupt Status (FCMIS) register (see page 641) by setting the corresponding MASK bits.
PAGE 621
Tiva™ TM4C129ENCPDT Microcontroller 3. Write the Flash memory write key and the WRITE bit (a value of 0xA442.0001) to the FMC register. The write key may be 0xA442 or the value programmed into the FLPEKEY register depending on the KEY value in the BOOTCFG register. See page 682 and page 648 for more information. 4. Poll the FMC register until the WRITE bit is cleared. To perform an erase of a 16-KB sector 1. Write the 16-KB aligned address to the FMA register. 2.
PAGE 622
Internal Memory memory array and are not affected by an ERASE or MASS ERASE operation. The bits in these registers can be changed from 1 to 0 with a commit operation. The register contents are unaffected by any reset condition except power-on reset, which returns the register contents to 0xFFFF.FFFE for the BOOT Configuration (BOOTCFG) register and 0xFFFF.FFFF for all others.
PAGE 623
Tiva™ TM4C129ENCPDT Microcontroller Table 8-3. User-Programmable Flash Memory Resident Registers (continued) Register to be Committed 8.2.4 FMA Value Data Source FMPRE11 0x0000.0016 FMPRE11 FMPRE12 0x0000.0018 FMPRE12 FMPRE13 0x0000.001A FMPRE13 FMPRE14 0x0000.001C FMPRE14 FMPRE15 0x0000.001E FMPRE15 FMPPE0 0x0000.0001 FMPPE0 FMPPE1 0x0000.0003 FMPPE1 FMPPE2 0x0000.0005 FMPPE2 FMPPE3 0x0000.0007 FMPPE3 FMPPE4 0x0000.0009 FMPPE4 FMPPE5 0x0000.000B FMPPE5 FMPPE6 0x0000.
PAGE 624
Internal Memory 8.2.4.1 Functional Description The EEPROM module provides a well-defined register interface to support accesses to the EEPROM with both a random access style of read and write as well as a rolling or sequential access scheme. A protection mechanism allows locking EEPROM blocks to prevent writes under a set of circumstances as well as reads under the same or different circumstances.
PAGE 625
Tiva™ TM4C129ENCPDT Microcontroller Table 8-4. MEMTIM0 Register Configuration versus Frequency CPU Frequency range (f) Time Period Range (t) in ns EEPROM Bank Clock in MHz High Time (EBCHT) Note: EEPROM Bank Clock Edge (EBCE) EEPROM Wait States (EWS) 16 62.5 0x0 1 0x0 16 < f ≤ 40 62.5 > t ≥ 25 0x2 0 0x1 40 < f ≤60 25 > t ≥ 16.67 0x3 0 0x2 60< f ≤80 16.67 > t ≥ 12.5 0x4 0 0x3 80 < f ≤100 12.5 > t ≥ 10 0x5 0 0x4 100< f ≤120 10 > t ≥ 8.
PAGE 626
Internal Memory ■ PROT = 0x2 – Without password: Readable but not writable. – With password: Readable only when unlocked, not writable under any conditions. Additionally, access protection may be applied based on the processor mode. This configuration allows for supervisor-only access or supervisor and user access, which is the default. Supervisor-only access mode also prevents access by the µDMA and Debugger.
PAGE 627
Tiva™ TM4C129ENCPDT Microcontroller non-targeted memory areas but cannot guarantee that the operation is completed successfully. Refer to “EEPROM” on page 1972 for important timing information on EEPROM protection. The EEPROM mechanism properly tracks all state information to provide complete safety and protection. Although it should not normally be possible, errors during programming can occur in certain circumstances, for example, the voltage rail dropping during programming.
PAGE 628
Internal Memory ■ Software reset (SYSRESREQ) ■ Software peripheral reset ■ Watchdog reset (if configured as a system reset in the RESBEHAVCTL register) ■ MOSC failure reset ■ BOR reset (if configured as a system reset in the RESBEHAVCTL register) ■ External reset (if configured as a system reset in the RESBEHAVCTL register) ■ Writes to the HSSR register The WORKING bit of the EEDONE register can be checked before the reset is asserted to see if an EEPROM program or erase operation is occurring.
PAGE 629
Tiva™ TM4C129ENCPDT Microcontroller 3. Read the PRETRY and ERETRY bits in the EEPROM Support Control and Status (EESUPP) register. If either of the bits are set, return an error, else continue. 4. Reset the EEPROM module using the EEPROM Software Reset (SREEPROM) register at offset 0x558 in the System Control register space. 5. Insert delay (6 cycles plus function call overhead). 6. Poll the WORKING bit in the EEPROM Done Status (EEDONE) register to determine when it is clear. When WORKING=0, continue. 7.
PAGE 630
Internal Memory Table 8-6. Flash Register Map Offset Name Type Reset See page Description Internal Memory Registers (Internal Memory Control Offset) 0x000 FMA RW 0x0000.0000 Flash Memory Address 633 0x004 FMD RW 0x0000.0000 Flash Memory Data 634 0x008 FMC RW 0x0000.0000 Flash Memory Control 635 0x00C FCRIS RO 0x0000.0000 Flash Controller Raw Interrupt Status 638 0x010 FCIM RW 0x0000.0000 Flash Controller Interrupt Mask 641 0x014 FCMISC RW1C 0x0000.
PAGE 631
Tiva™ TM4C129ENCPDT Microcontroller Table 8-6. Flash Register Map (continued) Offset Name 0x050 Description See page Type Reset EEHIDE0 RW 0x0000.0000 EEPROM Block Hide 0 672 0x054 EEHIDE1 RW 0x0000.0000 EEPROM Block Hide 1 673 0x058 EEHIDE2 RW 0x0000.0000 EEPROM Block Hide 2 673 0x080 EEDBGME RW 0x0000.0000 EEPROM Debug Mass Erase 674 0xFC0 EEPROMPP RO 0x0000.01FF EEPROM Peripheral Properties 675 Memory Registers (System Control Offset) 0x0D4 RVP RO 0x0101.
PAGE 632
Internal Memory Table 8-6. Flash Register Map (continued) Offset Name 0x410 Reset FMPPE4 RW 0xFFFF.FFFF Flash Memory Protection Program Enable 4 679 0x414 FMPPE5 RW 0xFFFF.FFFF Flash Memory Protection Program Enable 5 679 0x418 FMPPE6 RW 0xFFFF.FFFF Flash Memory Protection Program Enable 6 679 0x41C FMPPE7 RW 0xFFFF.FFFF Flash Memory Protection Program Enable 7 679 0x420 FMPPE8 RW 0xFFFF.FFFF Flash Memory Protection Program Enable 8 679 0x424 FMPPE9 RW 0xFFFF.
PAGE 633
Tiva™ TM4C129ENCPDT Microcontroller Register 1: Flash Memory Address (FMA), offset 0x000 During a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. During erase operations for flash space that is not user configurable (that is, FMPREn, FMPPEn, USER_REGn, BOOTCFG), this register contains a 16 KB-aligned CPU byte address and specifies which block is erased.
PAGE 634
Internal Memory Register 2: Flash Memory Data (FMD), offset 0x004 This register contains the data to be written during the programming cycle. Note that the contents of this register are undefined for a read access of an execute-only block. This register is not used during erase cycles. Flash Memory Data (FMD) Base 0x400F.D000 Offset 0x004 Type RW, reset 0x0000.
PAGE 635
Tiva™ TM4C129ENCPDT Microcontroller Register 3: Flash Memory Control (FMC), offset 0x008 When this register is written, the Flash memory controller initiates the appropriate access cycle for the location specified by the Flash Memory Address (FMA) register (see page 633). If the access is a write access, the data contained in the Flash Memory Data (FMD) register (see page 634) is written to the specified address.
PAGE 636
Internal Memory Bit/Field Name Type Reset 3 COMT RW 0 Description Commit Register Value This bit is used to commit writes to Flash-memory-resident registers and to monitor the progress of that process. Value Description 0 A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous commit access is complete. 1 Set this bit to commit (write) the register value to a Flash-memory-resident register.
PAGE 637
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 0 WRITE RW 0 Description Write a Word into Flash Memory This bit is used to write a word into Flash memory and to monitor the progress of that process. Value Description 0 A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous write update access is complete. 1 Set this bit to write the data stored in the FMD register into the Flash memory location specified by the contents of the FMA register.
PAGE 638
Internal Memory Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C This register indicates that the Flash memory controller has an interrupt condition. An interrupt is sent to the interrupt controller only if the corresponding FCIM register bit is set. Flash Controller Raw Interrupt Status (FCRIS) Base 0x400F.D000 Offset 0x00C Type RO, reset 0x0000.
PAGE 639
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 10 INVDRIS RO 0 Description Invalid Data Raw Interrupt Status Value Description 0 An interrupt has not occurred. 1 An interrupt is pending because a bit that was previously programmed as a 0 is now being requested to be programmed as a 1. This bit is cleared by writing a 1 to the INVMISC bit in the FCMISC register. 9 VOLTRIS RO 0 Pump Voltage Raw Interrupt Status Value Description 0 An interrupt has not occurred.
PAGE 640
Internal Memory Bit/Field Name Type Reset 0 ARIS RO 0 Description Access Raw Interrupt Status Value Description 0 No access has tried to improperly program or erase the Flash memory. 1 A program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in the FMPPEn registers. This status is sent to the interrupt controller when the AMASK bit in the FCIM register is set.
PAGE 641
Tiva™ TM4C129ENCPDT Microcontroller Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 This register controls whether the Flash memory controller generates interrupts to the controller. Flash Controller Interrupt Mask (FCIM) Base 0x400F.D000 Offset 0x010 Type RW, reset 0x0000.
PAGE 642
Internal Memory Bit/Field Name Type Reset 9 VOLTMASK RW 0 Description Pump Voltage Interrupt Mask Value Description 0 The VOLTRIS interrupt is suppressed and not sent to the interrupt controller. 1 An interrupt is sent to the interrupt controller when the VOLTRIS bit is set. 8:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
PAGE 643
Tiva™ TM4C129ENCPDT Microcontroller Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 This register provides two functions. First, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the interrupt reporting. Flash Controller Masked Interrupt Status and Clear (FCMISC) Base 0x400F.D000 Offset 0x014 Type RW1C, reset 0x0000.
PAGE 644
Internal Memory Bit/Field Name Type Reset 10 INVDMISC RW1C 0 Description Invalid Data Masked Interrupt Status and Clear Value Description 0 When read, a 0 indicates that an interrupt has not occurred. A write of 0 has no effect on the state of this bit. 1 When read, a 1 indicates that an unmasked interrupt was signaled. Writing a 1 to this bit clears INVDMISC and also the INVDRIS bit in the FCRIS register (see page 638).
PAGE 645
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 0 AMISC RW1C 0 Description Access Masked Interrupt Status and Clear Value Description 0 When read, a 0 indicates that no improper accesses have occurred. A write of 0 has no effect on the state of this bit. 1 When read, a 1 indicates that an unmasked interrupt was signaled because a program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in the FMPPEn registers.
PAGE 646
Internal Memory Register 7: Flash Memory Control 2 (FMC2), offset 0x020 When this register is written, the Flash memory controller initiates the appropriate access cycle for the location specified by the Flash Memory Address (FMA) register (see page 633). If the access is a write access, the data contained in the Flash Write Buffer (FWB) registers is written. This register must be the final register written as it initiates the memory operation. Flash Memory Control 2 (FMC2) Base 0x400F.
PAGE 647
Tiva™ TM4C129ENCPDT Microcontroller Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 This register provides a bitwise status of which FWBn registers have been written by the processor since the last write of the Flash memory write buffer. The entries with a 1 are written on the next write of the Flash memory write buffer. This register is cleared after the write operation by hardware. A protection violation on the write operation also clears this status.
PAGE 648
Internal Memory Register 9: Flash Program/Erase Key (FLPEKEY), offset 0x03C This register provides a mechanism for protection from inadvertent writes to flash by supplying a 16-bit key . If the KEY value in the BOOTCFG register is 0, then this value is used as the 16-bit key in place of 0xA442 in the FMC/FMC2 registers for committed flash writes. This can be used for cases where a new image is downloaded and the first word of the new image has the 16-bit key value to be used for that product.
PAGE 649
Tiva™ TM4C129ENCPDT Microcontroller Register 10: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C These 32 registers hold the contents of the data to be written into the Flash memory on a buffered Flash memory write operation. The offset selects one of the 32-bit registers. Only FWBn registers that have been updated since the preceding buffered Flash memory write operation are written into the Flash memory, so it is not necessary to write the entire bank of registers in order to write 1 or 2 words.
PAGE 650
Internal Memory Register 11: Flash Peripheral Properties (FLASHPP), offset 0xFC0 Flash Peripheral Properties (FLASHPP) Base 0x400F.D000 Offset 0xFC0 Type RO, reset 0xF014.
PAGE 651
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 22:19 EESS RO 0x2 Description EEPROM Sector Size of the physical bank Value Description 0x0 1 KB 0x1 2 KB 0x2 4 KB 0x3 8 KB 0x4-0x7 reserved 18:16 MAINSS RO 0x4 Flash Sector Size of the physical bank Value Description 0x0 1 KB 0x1 2 KB 0x2 4 KB 0x3 8 KB 0x4 16 KB 0x5-0x7 reserved 15:0 SIZE RO 0x1FF Flash Size Indicates the size of the on-chip Flash memory Value Description 0x01FF 1024 KB of Flash June 1
PAGE 652
Internal Memory Register 12: SRAM Size (SSIZE), offset 0xFC4 This register indicates the size of the on-chip SRAM. Important: This register should be used to determine the size of the SRAM that is implemented on this microcontroller. SRAM Size (SSIZE) Base 0x400F.D000 Offset 0xFC4 Type RO, reset 0x0000.
PAGE 653
Tiva™ TM4C129ENCPDT Microcontroller Register 13: Flash Configuration Register (FLASHCONF), offset 0xFC8 The FLASHCONF register allows the user to enable or disable various properties of the Flash. The force bits, FBFON and FBFOFF, can be used to test code performance and execution by turning the prefetch buffers on and subsequently forcing them off. Flash Configuration Register (FLASHCONF) Base 0x400F.D000 Offset 0xFC8 Type RW, reset 0x0000.
PAGE 654
Internal Memory Bit/Field Name Type Reset 17 FPFON RW 0 Description Force Prefetch On Value Description 16 FPFOFF RW 0 0 No effect 1 Force prefetch buffers to be enabled. Force Prefetch Off Value Description 15:0 reserved RO 0x0000 0 No effect 1 Force prefetch buffers to be disabled. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
PAGE 655
Tiva™ TM4C129ENCPDT Microcontroller Register 14: ROM Third-Party Software (ROMSWMAP), offset 0xFCC This register indicates the presence of third-party software in the on-chip ROM. ROMSWMAP enables the ROM apertures that are available. ROM Third-Party Software (ROMSWMAP) Base 0x400F.D000 Offset 0xFCC Type RO, reset 0x0000.
PAGE 656
Internal Memory Bit/Field Name Type Reset 7:6 SW3EN RO 0x0 Description ROM SW Region 3 Availability Value Description 0x0 Software region not available to the core. 0x1 Region available to core 0x2-0x3 reserved 5:4 SW2EN RO 0x0 ROM SW Region 2 Availability Value Description 0x0 Software region not available to the core. 0x1 Region available to core 0x2-0x3 reserved 3:2 SW1EN RO 0x0 ROM SW Region 1 Availability Value Description 0x0 Software region not available to the core.
PAGE 657
Tiva™ TM4C129ENCPDT Microcontroller Register 15: Flash DMA Address Size (FLASHDMASZ), offset 0xFD0 The FLASHDMASZ register contains the area of Flash that the µDMA can access. Note: The µDMA can access Flash in Run Mode only (not available in low power modes). Flash DMA Address Size (FLASHDMASZ) Base 0x400F.D000 Offset 0xFD0 Type RW, reset 0x0000.
PAGE 658
Internal Memory Register 16: Flash DMA Starting Address (FLASHDMAST), offset 0xFD4 The starting address for the Flash region accessible by the µDMA is programmed in the FLASHDMAST register. Note: The µDMA can access Flash in Run Mode only (not available in low power modes). Flash DMA Starting Address (FLASHDMAST) Base 0x400F.D000 Offset 0xFD4 Type RW, reset 0x0000.
PAGE 659
Tiva™ TM4C129ENCPDT Microcontroller Register 17: EEPROM Size Information (EESIZE), offset 0x000 The EESIZE register indicates the number of 16-word blocks and 32-bit words in the EEPROM. EEPROM Size Information (EESIZE) Base 0x400A.F000 Offset 0x000 Type RO, reset 0x0060.
PAGE 660
Internal Memory Register 18: EEPROM Current Block (EEBLOCK), offset 0x004 The EEBLOCK register is used to select the EEPROM block for subsequent reads, writes, and protection control. The value is a page offset into the EEPROM, such that the first block is 0, then second block is 1, etc. Each block contains 16 words. Attempts to set an invalid block causes the BLOCK field to be configured to 0. To verify that the intended block is being accessed, software can read the BLOCK field after it has been written.
PAGE 661
Tiva™ TM4C129ENCPDT Microcontroller Register 19: EEPROM Current Offset (EEOFFSET), offset 0x008 The EEOFFSET register is used to select the EEPROM word to read or write within the block selected by the EEBLOCK register. The value is a word offset into the block. Because accesses to the EERDWRINC register change the offset, software can read the contents of this register to determine the current offset. EEPROM Current Offset (EEOFFSET) Base 0x400A.F000 Offset 0x008 Type RW, reset 0x0000.
PAGE 662
Internal Memory Register 20: EEPROM Read-Write (EERDWR), offset 0x010 The EERDWR register is used to read or write the EEPROM word at the address pointed to by the EEBLOCK and EEOFFSET registers. If the protection or access rules do not permit access, the operation is handled as follows: if reading is not allowed, the value 0xFFFF.FFFF is returned in all cases; if writing is not allowed, the EEDONE register is configured to indicate an error.
PAGE 663
Tiva™ TM4C129ENCPDT Microcontroller Register 21: EEPROM Read-Write with Increment (EERDWRINC), offset 0x014 The EERDWRINC register is used to read or write the EEPROM word at the address pointed to by the EEBLOCK and EEOFFSET registers, and then increment the OFFSET field in the EEOFFSET register. If the protection or access rules do not permit access, the operation is handled as follows: if reading is not allowed, the value 0xFFFF.
PAGE 664
Internal Memory Register 22: EEPROM Done Status (EEDONE), offset 0x018 The EEDONE register indicates completion status of a write to the following registers: ■ EERDWR or EERDWRINC register (for writes to the EEPROM memory) ■ EEPROT register (for setting read and protection of the current block) ■ EEPASSn registers (for configuring a password for a block) ■ EEDBGME register (for mass erase of an EEPROM block) This register can indicate if the write ended in an error or not.
PAGE 665
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 NOPERM RO 0 Description Write Without Permission Value Description 3 WKCOPY RO 0 0 No error 1 An attempt was made to write without permission. This error can result because the block is locked, the write violates the programmed access protection, or when an attempt is made to write a password when the password has already been written. Working on a Copy Value Description 2 WKERASE RO 0 0 The EEPROM is not copying.
PAGE 666
Internal Memory Register 23: EEPROM Support Control and Status (EESUPP), offset 0x01C The EESUPP register indicates if internal operations are required because an internal copy buffer must be erased or a programming failure has occurred and the operation must be completed. These conditions are explained below as well as in more detail in the section called “Error During Programming” on page 627.
PAGE 667
Tiva™ TM4C129ENCPDT Microcontroller Register 24: EEPROM Unlock (EEUNLOCK), offset 0x020 The EEUNLOCK register can be used to unlock the whole EEPROM or a single block using a password. Unlocking is only required if a password is registered using the EEPASSn registers for the block that is selected by the EEBLOCK register. If block 0 has a password, it locks the remaining blocks from any type of access, but uses its own protection mechanism, for example readable, but not writable when locked.
PAGE 668
Internal Memory Register 25: EEPROM Protection (EEPROT), offset 0x030 The EEPROT register is used to set or read the protection for the current block, as selected by the EEBLOCK register. Protection and access control is used to determine when a block's contents can be read or written. Note: A read of the EEPROT register during the EEPROM initialization sequence is only valid when the WORKING bit is 0 in EEDONE register: EEPROM Protection (EEPROT) Base 0x400A.F000 Offset 0x030 Type RW, reset 0x0000.
PAGE 669
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 2:0 PROT RW 0x0 Description Protection Control The Protection bits control what context is needed for reading and writing the block selected by the EEBLOCK register, or if block 0 is selected, all blocks. The following values are allowed: Value Description 0x0 This setting is the default. Without password: the block is not protected and is readable and writable at any time.
PAGE 670
Internal Memory Register 26: EEPROM Password (EEPASS0), offset 0x034 Register 27: EEPROM Password (EEPASS1), offset 0x038 Register 28: EEPROM Password (EEPASS2), offset 0x03C The EEPASSn registers are used to configure a password for a block. A password may only be set once and cannot be changed. The password may be 32-bits, 64-bits, or 96-bits. Each word of the password can be any 32-bit value other than 0xFFFF.FFFF (all 1s).
PAGE 671
Tiva™ TM4C129ENCPDT Microcontroller Register 29: EEPROM Interrupt (EEINT), offset 0x040 The EEINT register is used to control whether an interrupt should be generated when a write to EEPROM completes as indicated by the EEDONE register value changing from 0x1 to any other value.
PAGE 672
Internal Memory Register 30: EEPROM Block Hide 0 (EEHIDE0), offset 0x050 The EEHIDE0 register is used to hide one or more blocks other than EEPROM block 0. Bits 1 through 31 of this register correspond to EEPROM blocks 1 through 31. Once hidden, the block is not accessible until the next reset. This model allows initialization code to have access to data which is not visible to the rest of the application.
PAGE 673
Tiva™ TM4C129ENCPDT Microcontroller Register 31: EEPROM Block Hide 1 (EEHIDE1), offset 0x054 Register 32: EEPROM Block Hide 2 (EEHIDE2), offset 0x058 The EEHIDE register is used to hide one or more blocks. Bits 0 through 31 of the EEHIDE1 register correspond to EEPROM blocks 32 through 63. Bits 0 through 31 of the EEHIDE2 register correspond to EEPROM blocks 64 through 95. Once hidden, the block is not accessible until the next reset.
PAGE 674
Internal Memory Register 33: EEPROM Debug Mass Erase (EEDBGME), offset 0x080 The EEDBGME register is used to mass erase the EEPROM block back to its default state from the factory. This register is intended to be used only for debug and test purposes, not in production environments. The erase takes place in such a way as to be secure. It first erases all data and then erases the protection mechanism.
PAGE 675
Tiva™ TM4C129ENCPDT Microcontroller Register 34: EEPROM Peripheral Properties (EEPROMPP), offset 0xFC0 The EEPROMPP register indicates the size of the EEPROM for this part. EEPROM Peripheral Properties (EEPROMPP) Base 0x400A.F000 Offset 0xFC0 Type RO, reset 0x0000.
PAGE 676
Internal Memory Register 35: Reset Vector Pointer (RVP), offset 0x0D4 The Reset Vector Pointer (RVP) register contains the address of the reset vector of the software module that is to be executed after boot loader execution. The RVP register is initialized by a power-on reset. Reset Vector Pointer (RVP) Base 0x400F.E000 Offset 0x0D4 Type RO, reset 0x0101.
PAGE 677
Tiva™ TM4C129ENCPDT Microcontroller Register 36: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x200 Register 37: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 Register 38: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 Register 39: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C Register 40: Flash Memory Protection Read Enable 4 (FMPRE4), offset 0x210 Register 41: Flash Memory Protection Read Enable 5 (FMPRE5), offset 0x214 Register 42: Flash Memory Prote
PAGE 678
Internal Memory ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ FMPRE0: 0 to 64 KB FMPRE1: 65 to 128 KB FMPRE2: 129 to 192 KB FMPRE3: 193 to 256 KB FMPRE4: 257 to 320 KB FMPRE5: 321 to 384 KB FMPRE6: 385 to 448 KB FMPRE7: 449 to 512 KB FMPRE8: 513 to 576 KB FMPRE9: 577 to 640 KB FMPRE10: 641 to 704 KB FMPRE11: 705 to 768 KB FMPRE12: 769 to 832 KB FMPRE13: 833 to 896 KB FMPRE14: 897 to 960 KB FMPRE15: 961 to 1024 KB Flash Memory Protection Read Enable n (FMPREn) Base 0x400F.E000 Offset 0x200 Type RW, reset 0xFFFF.
PAGE 679
Tiva™ TM4C129ENCPDT Microcontroller Register 52: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x400 Register 53: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 Register 54: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 Register 55: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C Register 56: Flash Memory Protection Program Enable 4 (FMPPE4), offset 0x410 Register 57: Flash Memory Protection Program Enable 5 (FMPPE5), offset 0x414 Register 58:
PAGE 680
Internal Memory is supported. Note that the Flash Memory Protection Read (FMPREn) registers do allow read-protection of a block as small as 2 KB, unlike the FMPPEn registers. Thus, in order to execute-only protect a 16-KB block, a user must program the entire eight bits of the byte to the same value. For example, to protect the first 16-KB block, bits [7:0] of the FMPPE0 register need to be cleared to all 0s. This register is loaded during the power-on reset sequence.
PAGE 681
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type 31:0 PROG_ENABLE RW Reset Description 0xFFFF.FFFF Flash Programming Enable Every eighth bit programs an 16-KB flash sector to be execute only. The policies may be combined as shown in Table 8-2 on page 618.
PAGE 682
Internal Memory Register 68: Boot Configuration (BOOTCFG), offset 0x1D0 Note: Offset is relative to System Control base address of 0x400F.E000. Note: The Boot Configuration (BOOTCFG) register requires a POR before the committed changes take effect. This register is not written directly, but instead uses the FMD register as explained in “Non-Volatile Register Programming-- Flash Memory Resident Registers” on page 621.
PAGE 683
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset Description 31 NW RO 1 Not Written When set, this bit indicates that the values in this register can be changed from 1 to 0. When clear, this bit specifies that the contents of this register cannot be changed. 30:16 reserved RO 0xFFFF 15:13 PORT RO 0x7 Software should not rely on the value of a reserved bit.
PAGE 684
Internal Memory Bit/Field Name Type Reset 8 EN RO 1 Description Boot GPIO Enable Clearing this bit enables the use of a GPIO pin to enable the ROM Boot Loader at reset. When this bit is set, the contents of address 0x0000.0004 are checked to see if the Flash memory has been programmed. If the contents are not 0xFFFF.FFFF, the core executes out of Flash memory. If the Flash has not been programmed, the core executes out of ROM.
PAGE 685
Tiva™ TM4C129ENCPDT Microcontroller Register 69: User Register 0 (USER_REG0), offset 0x1E0 Register 70: User Register 1 (USER_REG1), offset 0x1E4 Register 71: User Register 2 (USER_REG2), offset 0x1E8 Register 72: User Register 3 (USER_REG3), offset 0x1EC Note: Offset is relative to System Control base address of 0x400F.E000. These registers each provide 32 bits of user-defined data that is non-volatile. Bits can only be changed from 1 to 0.
PAGE 686
Micro Direct Memory Access (μDMA) 9 Micro Direct Memory Access (μDMA) The TM4C129ENCPDT microcontroller includes a Direct Memory Access (DMA) controller, known as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the Cortex™-M4F processor, allowing for more efficient use of the processor and the available bus bandwidth. The μDMA controller can perform transfers between memory and peripherals.
PAGE 687
Tiva™ TM4C129ENCPDT Microcontroller ■ Maskable peripheral requests ■ Interrupt on transfer completion, with a separate interrupt per channel 9.1 Block Diagram Figure 9-1.
PAGE 688
Micro Direct Memory Access (μDMA) the arbitration size, it is possible to control exactly how many items are transferred to or from a peripheral each time it makes a μDMA service request. 9.2.1 Channel Assignments Each DMA channel has up to nine possible assignments which are selected using the DMA Channel Map Select n (DMACHMAPn) registers with 4-bit assignment fields for each µDMA channel. Table 9-1 on page 688 shows the µDMA channel mapping. The Enc.
PAGE 689
Tiva™ TM4C129ENCPDT Microcontroller Table 9-1.
PAGE 690
Micro Direct Memory Access (μDMA) levels of priority: default priority and high priority. If the priority level bit is set, then that channel has higher priority than all other channels at default priority. If multiple channels are set for high priority, then the channel number is used to determine relative priority among all the high priority channels.
PAGE 691
Tiva™ TM4C129ENCPDT Microcontroller Table 9-2.
PAGE 692
Micro Direct Memory Access (μDMA) transfer is complete. In this case, the alternate control structures are not used and therefore only the first half of the table must be allocated in memory; the second half of the control table is not necessary, and that memory can be used for something else. If a more complex transfer mode is used such as ping-pong or scatter-gather, then the alternate control structure is also used and memory space should be allocated for the entire table.
PAGE 693
Tiva™ TM4C129ENCPDT Microcontroller mode indicates "stopped." Because the control word is modified by the μDMA controller, it must be reconfigured before each new transfer. The source and destination end pointers are not modified, so they can be left unchanged if the source or destination addresses remain the same. Prior to starting a transfer, a μDMA channel must be enabled by setting the appropriate bit in the DMA Channel Enable Set (DMAENASET) register.
PAGE 694
Micro Direct Memory Access (μDMA) alternate control structures to switch back and forth between buffers as the data flows to or from the peripheral. Refer to Figure 9-2 on page 694 for an example showing operation in Ping-Pong mode. Figure 9-2.
PAGE 695
Tiva™ TM4C129ENCPDT Microcontroller 9.2.6.5 Memory Scatter-Gather Memory Scatter-Gather mode is a complex mode used when data must be transferred to or from varied locations in memory instead of a set of contiguous locations in a memory buffer. For example, a gather μDMA operation could be used to selectively read the payload of several stored packets of a communication protocol and store them together in sequence in a memory buffer.
PAGE 696
Micro Direct Memory Access (μDMA) Figure 9-3.
PAGE 697
Tiva™ TM4C129ENCPDT Microcontroller Figure 9-4. Memory Scatter-Gather, μDMA Copy Sequence Task List in Memory Buffers in Memory µDMA Control Table in Memory SRC A SRC SRC B PRI COPIED DST TASK A TASK B SRC SRC C ALT COPIED DST TASK C DEST A DEST B DEST C Then, using the channel’s alternate control structure, the µDMA controller copies data from the source buffer A to the destination buffer.
PAGE 698
Micro Direct Memory Access (μDMA) 9.2.6.6 Peripheral Scatter-Gather Peripheral Scatter-Gather mode is very similar to Memory Scatter-Gather, except that the transfers are controlled by a peripheral making a μDMA request. Upon detecting a request from the peripheral, the μDMA controller uses the primary control structure to copy one entry from the list to the alternate control structure and then performs the transfer.
PAGE 699
Tiva™ TM4C129ENCPDT Microcontroller Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration 1 2 3 Source Buffer in Memory Task List in Memory Channel Control Table in Memory 4 WORDS (SRC A) SRC A DST ITEMS=4 16 WORDS (SRC B) SRC DST SRC ITEMS=12 DST B “TASK” A Unused ITEMS=16 Channel Primary Control Structure “TASK” B Unused SRC DST ITEMS=1 “TASK” C Unused SRC DST Channel Alternate Control Structure ITEMS=n 1 WORD (SRC C) C Peripheral Data Register DEST NOTES: 1.
PAGE 700
Micro Direct Memory Access (μDMA) Figure 9-6. Peripheral Scatter-Gather, μDMA Copy Sequence Task List in Memory Buffers in Memory µDMA Control Table in Memory SRC A SRC SRC B PRI COPIED DST TASK A TASK B SRC SRC C ALT COPIED DST TASK C Then, using the channel’s alternate control structure, the µDMA controller copies data from the source buffer A to the peripheral data register.
PAGE 701
Tiva™ TM4C129ENCPDT Microcontroller 9.2.7 Transfer Size and Increment The μDMA controller supports transfer data sizes of 8, 16, or 32 bits. The source and destination data size must be the same for any given transfer. The source and destination address can be auto-incremented by bytes, half-words, or words, or can be set to no increment.
PAGE 702
Micro Direct Memory Access (μDMA) If the trigger peripheral generates another uDMA request while the prior one is being serviced and that particular channel is the highest priority asserted channel, the second request will be processed as soon as the handling of the first is complete. If two additional trigger peripheral uDMA requests are generated prior to the completion of the first, the third request is lost. 9.2.
PAGE 703
Tiva™ TM4C129ENCPDT Microcontroller 2. Enable the μDMA controller by setting the MASTEREN bit of the DMA Configuration (DMACFG) register. 3. Program the location of the channel control table by writing the base address of the table to the DMA Channel Control Base Pointer (DMACTLBASE) register. The base address must be aligned on a 1024-byte boundary. 9.3.2 Configuring a Memory-to-Memory Transfer μDMA channel 30 is dedicated for software-initiated transfers.
PAGE 704
Micro Direct Memory Access (μDMA) Table 9-8.
PAGE 705
Tiva™ TM4C129ENCPDT Microcontroller 2. Set bit 7 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the primary channel control structure for this transfer. 3. Set bit 7 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the μDMA controller to respond to single and burst requests. 4. Set bit 7 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow the μDMA controller to recognize requests for this channel. 9.3.3.
PAGE 706
Micro Direct Memory Access (μDMA) Note: 9.3.3.3 In this example, it is not important if the peripheral makes a single request or a burst request. Because the peripheral has a FIFO that triggers at a level of 4, the arbitration size is set to 4. If the peripheral does make a burst request, then 4 bytes are transferred, which is what the FIFO can accommodate. If the peripheral makes a single request (if there is any space in the FIFO), then one byte is transferred at a time.
PAGE 707
Tiva™ TM4C129ENCPDT Microcontroller alternate channel control structure is at offset 0x280. The channel control structures for channel 8 are located at the offsets shown in Table 9-11. Table 9-11.
PAGE 708
Micro Direct Memory Access (μDMA) Table 9-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive Example (continued) Field in DMACHCTL Bits Value XFERSIZE 13:4 63 Transfer 64 items 3 0 N/A for this transfer type 2:0 3 Use Ping-Pong transfer mode NXTUSEBURST XFERMODE Note: 9.3.4.3 Description In this example, it is not important if the peripheral makes a single request or a burst request.
PAGE 709
Tiva™ TM4C129ENCPDT Microcontroller a. Process the newly received data in buffer B or signal the buffer processing code that buffer B has data available. b. Reprogram the alternate channel control word at offset 0x288 according to Table 9-12 on page 707. 9.3.5 Configuring Channel Assignments Channel assignments for each μDMA channel can be changed using the DMACHMAPn registers. Each 4-bit field represents a μDMA channel. Refer to Table 9-1 on page 688 for channel assignments.
PAGE 710
Micro Direct Memory Access (μDMA) Table 9-13. μDMA Register Map (continued) Offset Name Type Reset 0x018 DMAUSEBURSTSET RW 0x0000.0000 0x01C DMAUSEBURSTCLR WO - 0x020 DMAREQMASKSET RW 0x0000.0000 0x024 DMAREQMASKCLR WO - 0x028 DMAENASET RW 0x0000.0000 0x02C DMAENACLR WO - 0x030 DMAALTSET RW 0x0000.0000 0x034 DMAALTCLR WO - 0x038 DMAPRIOSET RW 0x0000.
PAGE 711
Tiva™ TM4C129ENCPDT Microcontroller Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 DMA Channel Source Address End Pointer (DMASRCENDP) is part of the Channel Control Structure and is used to specify the source address for a μDMA transfer. Note: The offset specified is from the base address of the control structure in system memory, not the μDMA module base address.
PAGE 712
Micro Direct Memory Access (μDMA) Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 DMA Channel Destination Address End Pointer (DMADSTENDP) is part of the Channel Control Structure and is used to specify the destination address for a μDMA transfer. Note: The offset specified is from the base address of the control structure in system memory, not the μDMA module base address.
PAGE 713
Tiva™ TM4C129ENCPDT Microcontroller Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008 DMA Channel Control Word (DMACHCTL) is part of the Channel Control Structure and is used to specify parameters of a μDMA transfer. Note: The offset specified is from the base address of the control structure in system memory, not the μDMA module base address.
PAGE 714
Micro Direct Memory Access (μDMA) Bit/Field Name Type Reset 29:28 DSTSIZE RW - Description Destination Data Size This field configures the destination item data size. Note: DSTSIZE must be the same as SRCSIZE. Value Description 0x0 Byte 8-bit data size 0x1 Half-word 16-bit data size 0x2 Word 32-bit data size 0x3 27:26 SRCINC RW - Reserved Source Address Increment This field configures the source address increment.
PAGE 715
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 21 DSTPROT0 RW 0 Description Destination Privilege Access This bit controls the privilege access protection for destination data writes. Note: For AES,DES, or SHA accesses, this bit must be set to 1. Value Description 0 The access is non-privileged. 1 The access is privileged. 20:19 reserved RO - Software should not rely on the value of a reserved bit.
PAGE 716
Micro Direct Memory Access (μDMA) Bit/Field Name Type Reset 13:4 XFERSIZE RW - Description Transfer Size (minus 1) This field configures the total number of items to transfer. The value of this field is 1 less than the number to transfer (value 0 means transfer 1 item). The maximum value for this 10-bit field is 1023 which represents a transfer size of 1024 items. The transfer size is the number of items, not the number of bytes.
PAGE 717
Tiva™ TM4C129ENCPDT Microcontroller Ping-Pong This mode uses both the primary and alternate control structures for this channel. When the number of transfers specified by the XFERSIZE field have completed for the current control structure (primary or alternate), the µDMA controller switches to the other one. These switches continue until one of the control structures is not set to ping-pong mode. At that point, the µDMA controller stops.
PAGE 718
Micro Direct Memory Access (μDMA) Register 4: DMA Status (DMASTAT), offset 0x000 The DMA Status (DMASTAT) register returns the status of the μDMA controller. You cannot read this register when the μDMA controller is in the reset state. DMA Status (DMASTAT) Base 0x400F.F000 Offset 0x000 Type RO, reset 0x001F.
PAGE 719
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 0 MASTEN RO 0 Description Master Enable Status Value Description 0 The μDMA controller is disabled. 1 The μDMA controller is enabled.
PAGE 720
Micro Direct Memory Access (μDMA) Register 5: DMA Configuration (DMACFG), offset 0x004 The DMACFG register controls the configuration of the μDMA controller. DMA Configuration (DMACFG) Base 0x400F.
PAGE 721
Tiva™ TM4C129ENCPDT Microcontroller Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 The DMACTLBASE register must be configured so that the base pointer points to a location in system memory. The amount of system memory that must be assigned to the μDMA controller depends on the number of μDMA channels used and whether the alternate channel control data structure is used. See “Channel Configuration” on page 691 for details about the Channel Control Table.
PAGE 722
Micro Direct Memory Access (μDMA) Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C The DMAALTBASE register returns the base address of the alternate channel control data. This register removes the necessity for application software to calculate the base address of the alternate channel control structures. This register cannot be read when the μDMA controller is in the reset state. DMA Alternate Channel Control Base Pointer (DMAALTBASE) Base 0x400F.
PAGE 723
Tiva™ TM4C129ENCPDT Microcontroller Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 This read-only register indicates that the μDMA channel is waiting on a request. A peripheral can hold off the μDMA from performing a single request until the peripheral is ready for a burst request to enhance the μDMA performance. The use of this feature is dependent on the design of the peripheral and is not controllable by software in any way.
PAGE 724
Micro Direct Memory Access (μDMA) Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014 Each bit of the DMASWREQ register represents the corresponding μDMA channel. Setting a bit generates a request for the specified μDMA channel. DMA Channel Software Request (DMASWREQ) Base 0x400F.
PAGE 725
Tiva™ TM4C129ENCPDT Microcontroller Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 Each bit of the DMAUSEBURSTSET register represents the corresponding μDMA channel. Setting a bit disables the channel's single request input from generating requests, configuring the channel to only accept burst requests. Reading the register returns the status of USEBURST.
PAGE 726
Micro Direct Memory Access (μDMA) Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C Each bit of the DMAUSEBURSTCLR register represents the corresponding μDMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAUSEBURSTSET register. DMA Channel Useburst Clear (DMAUSEBURSTCLR) Base 0x400F.
PAGE 727
Tiva™ TM4C129ENCPDT Microcontroller Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 Each bit of the DMAREQMASKSET register represents the corresponding μDMA channel. Setting a bit disables μDMA requests for the channel. Reading the register returns the request mask status. When a μDMA channel's request is masked, that means the peripheral can no longer request μDMA transfers. The channel can then be used for software-initiated transfers.
PAGE 728
Micro Direct Memory Access (μDMA) Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 Each bit of the DMAREQMASKCLR register represents the corresponding μDMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAREQMASKSET register. DMA Channel Request Mask Clear (DMAREQMASKCLR) Base 0x400F.
PAGE 729
Tiva™ TM4C129ENCPDT Microcontroller Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028 Each bit of the DMAENASET register represents the corresponding µDMA channel. Setting a bit enables the corresponding µDMA channel. Reading the register returns the enable status of the channels. If a channel is enabled but the request mask is set (DMAREQMASKSET), then the channel can be used for software-initiated transfers. DMA Channel Enable Set (DMAENASET) Base 0x400F.
PAGE 730
Micro Direct Memory Access (μDMA) Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C Each bit of the DMAENACLR register represents the corresponding µDMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAENASET register. DMA Channel Enable Clear (DMAENACLR) Base 0x400F.
PAGE 731
Tiva™ TM4C129ENCPDT Microcontroller Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 Each bit of the DMAALTSET register represents the corresponding µDMA channel. Setting a bit configures the µDMA channel to use the alternate control data structure. Reading the register returns the status of which control data structure is in use for the corresponding µDMA channel. DMA Channel Primary Alternate Set (DMAALTSET) Base 0x400F.F000 Offset 0x030 Type RW, reset 0x0000.
PAGE 732
Micro Direct Memory Access (μDMA) Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 Each bit of the DMAALTCLR register represents the corresponding μDMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAALTSET register. DMA Channel Primary Alternate Clear (DMAALTCLR) Base 0x400F.
PAGE 733
Tiva™ TM4C129ENCPDT Microcontroller Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038 Each bit of the DMAPRIOSET register represents the corresponding µDMA channel. Setting a bit configures the µDMA channel to have a high priority level. Reading the register returns the status of the channel priority mask. DMA Channel Priority Set (DMAPRIOSET) Base 0x400F.F000 Offset 0x038 Type RW, reset 0x0000.
PAGE 734
Micro Direct Memory Access (μDMA) Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C Each bit of the DMAPRIOCLR register represents the corresponding µDMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAPRIOSET register. DMA Channel Priority Clear (DMAPRIOCLR) Base 0x400F.
PAGE 735
Tiva™ TM4C129ENCPDT Microcontroller Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C The DMAERRCLR register is used to read and clear the µDMA bus error status. The error status is set if the μDMA controller encountered a bus error while performing a transfer. If a bus error occurs on a channel, that channel is automatically disabled by the μDMA controller. The other channels are unaffected. DMA Bus Error Clear (DMAERRCLR) Base 0x400F.F000 Offset 0x04C Type RW, reset 0x0000.
PAGE 736
Micro Direct Memory Access (μDMA) Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500 Each bit of the DMACHASGN register represents the corresponding µDMA channel. Setting a bit selects the secondary channel assignment as specified in Table 9-1 on page 688. Note: This register is provided to support legacy software. New software should use the DMACHMAPn registers. If a bit is clear in this register, the corresponding field in the DMACHMAPn registers is configured to 0x0.
PAGE 737
Tiva™ TM4C129ENCPDT Microcontroller Register 22: DMA Channel Map Select 0 (DMACHMAP0), offset 0x510 Each 4-bit field of the DMACHMAP0 register configures the μDMA channel assignment as specified in Table 9-1 on page 688. Note: To support legacy software which uses the DMA Channel Assignment (DMACHASGN) register, a value of 0x0 is equivalent to a DMACHASGN bit being clear, and a value of 0x1 is equivalent to a DMACHASGN bit being set. DMA Channel Map Select 0 (DMACHMAP0) Base 0x400F.
PAGE 738
Micro Direct Memory Access (μDMA) Register 23: DMA Channel Map Select 1 (DMACHMAP1), offset 0x514 Each 4-bit field of the DMACHMAP1 register configures the μDMA channel assignment as specified in Table 9-1 on page 688. Note: To support legacy software which uses the DMA Channel Assignment (DMACHASGN) register, a value of 0x0 is equivalent to a DMACHASGN bit being clear, and a value of 0x1 is equivalent to a DMACHASGN bit being set. DMA Channel Map Select 1 (DMACHMAP1) Base 0x400F.
PAGE 739
Tiva™ TM4C129ENCPDT Microcontroller Register 24: DMA Channel Map Select 2 (DMACHMAP2), offset 0x518 Each 4-bit field of the DMACHMAP2 register configures the μDMA channel assignment as specified in Table 9-1 on page 688. Note: To support legacy software which uses the DMA Channel Assignment (DMACHASGN) register, a value of 0x0 is equivalent to a DMACHASGN bit being clear, and a value of 0x1 is equivalent to a DMACHASGN bit being set. DMA Channel Map Select 2 (DMACHMAP2) Base 0x400F.
PAGE 740
Micro Direct Memory Access (μDMA) Register 25: DMA Channel Map Select 3 (DMACHMAP3), offset 0x51C Each 4-bit field of the DMACHMAP3 register configures the μDMA channel assignment as specified in Table 9-1 on page 688. Note: To support legacy software which uses the DMA Channel Assignment (DMACHASGN) register, a value of 0x0 is equivalent to a DMACHASGN bit being clear, and a value of 0x1 is equivalent to a DMACHASGN bit being set. DMA Channel Map Select 3 (DMACHMAP3) Base 0x400F.
PAGE 741
Tiva™ TM4C129ENCPDT Microcontroller Register 26: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA Peripheral Identification 0 (DMAPeriphID0) Base 0x400F.F000 Offset 0xFE0 Type RO, reset 0x0000.
PAGE 742
Micro Direct Memory Access (μDMA) Register 27: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA Peripheral Identification 1 (DMAPeriphID1) Base 0x400F.F000 Offset 0xFE4 Type RO, reset 0x0000.
PAGE 743
Tiva™ TM4C129ENCPDT Microcontroller Register 28: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA Peripheral Identification 2 (DMAPeriphID2) Base 0x400F.F000 Offset 0xFE8 Type RO, reset 0x0000.
PAGE 744
Micro Direct Memory Access (μDMA) Register 29: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC The DMAPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. DMA Peripheral Identification 3 (DMAPeriphID3) Base 0x400F.F000 Offset 0xFEC Type RO, reset 0x0000.
PAGE 745
Tiva™ TM4C129ENCPDT Microcontroller Register 30: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA Peripheral Identification 4 (DMAPeriphID4) Base 0x400F.F000 Offset 0xFD0 Type RO, reset 0x0000.
PAGE 746
Micro Direct Memory Access (μDMA) Register 31: DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA PrimeCell Identification 0 (DMAPCellID0) Base 0x400F.F000 Offset 0xFF0 Type RO, reset 0x0000.
PAGE 747
Tiva™ TM4C129ENCPDT Microcontroller Register 32: DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA PrimeCell Identification 1 (DMAPCellID1) Base 0x400F.F000 Offset 0xFF4 Type RO, reset 0x0000.
PAGE 748
Micro Direct Memory Access (μDMA) Register 33: DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA PrimeCell Identification 2 (DMAPCellID2) Base 0x400F.F000 Offset 0xFF8 Type RO, reset 0x0000.
PAGE 749
Tiva™ TM4C129ENCPDT Microcontroller Register 34: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA PrimeCell Identification 3 (DMAPCellID3) Base 0x400F.F000 Offset 0xFFC Type RO, reset 0x0000.
PAGE 750
General-Purpose Input/Outputs (GPIOs) 10 General-Purpose Input/Outputs (GPIOs) The GPIO module is composed of 15 physical GPIO blocks, each corresponding to an individual GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G, Port H, Port J, Port K, Port L, Port M, Port N, Port P, Port Q). The GPIO module supports up to 90 programmable input/output pins, depending on the peripherals being used.
PAGE 751
Tiva™ TM4C129ENCPDT Microcontroller 10.1 Signal Description GPIO signals have alternate hardware functions. The following table lists the GPIO pins and their analog and digital alternate functions. The digital alternate hardware functions are enabled by setting the appropriate bit in the GPIO Alternate Function Select (GPIOAFSEL) and GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control (GPIOPCTL) register to the numeric encoding shown in the table below.
PAGE 752
General-Purpose Input/Outputs (GPIOs) Table 10-2.
PAGE 753
Tiva™ TM4C129ENCPDT Microcontroller Table 10-2.
PAGE 754
General-Purpose Input/Outputs (GPIOs) Table 10-2.
PAGE 755
Tiva™ TM4C129ENCPDT Microcontroller Note: 10.3 Port pins PM[7:4] operate as Fast GPIO pads but support only 2-, 4-, 6-, and 8-mA drive capability. 10- and 12-mA drive are not supported. All standard GPIO register controls, except for the GPIODR12R register, apply to these port pins. Functional Description Each GPIO port is a separate hardware instantiation of the same physical block (see Figure 10-1 on page 755 and Figure 10-2 on page 756).
PAGE 756
General-Purpose Input/Outputs (GPIOs) Figure 10-2.
PAGE 757
Tiva™ TM4C129ENCPDT Microcontroller 10.3.1.1 Data Direction Operation The GPIO Direction (GPIODIR) register (see page 768) is used to configure each individual pin as an input or output. When the data direction bit is cleared, the GPIO is configured as an input, and the corresponding data register bit captures and stores the value on the GPIO port. When the data direction bit is set, the GPIO is configured as an output, and the corresponding data register bit is driven out on the GPIO port. 10.3.1.
PAGE 758
General-Purpose Input/Outputs (GPIOs) 10.3.2 Interrupt Control The interrupt capabilities of each GPIO port are controlled by a set of seven registers. These registers are used to select the source of the interrupt, its polarity, and the edge properties. When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt to enable any further interrupts.
PAGE 759
Tiva™ TM4C129ENCPDT Microcontroller an ADC conversion is initiated. See page 1215. Note that whether the GPIO is configured to trigger on edge events or level events, a single-clock ADC trigger pulse is created in either event. Thus, when a level event is selected, the ADC sample sequence will run only one time and multiple sample sequences will not be executed if the level remains the same. It is recommended that edge events be used as ADC trigger source.
PAGE 760
General-Purpose Input/Outputs (GPIOs) 10.3.4 Commit Control The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for the GPIO pins that can be used as the four JTAG/SWD pins and the NMI pin (see “Signal Tables” on page 1896 for pin numbers).
PAGE 761
Tiva™ TM4C129ENCPDT Microcontroller Table 10-3. GPIO Drive Strength Options EDE (GPIOPP) X 1 1 1 10.3.
PAGE 762
General-Purpose Input/Outputs (GPIOs) 8. Program each pad in the port to have either pull-up, pull-down, or open drain functionality through the GPIOPUR, GPIOPDR, GPIOODR register. Slew rate may also be programmed, if needed, through the GPIOSLR register. 9. To enable GPIO pins as digital I/Os, set the appropriate DEN bit in the GPIODEN register. To enable GPIO pins to their analog function (if available), set the GPIOAMSEL bit in the GPIOAMSEL register. 10.
PAGE 763
Tiva™ TM4C129ENCPDT Microcontroller Table 10-4. GPIO Pad Configuration Examples (continued) a Configuration GPIO Register Bit Value ODR DEN PUR PDR Digital Input/Output (SSI) AFSEL 1 DIR X 0 1 ? ? DR2R ? DR4R ? DR8R ? DR12R ? SLR ? Digital Input/Output (UART) 1 X 0 1 ? ? ? ? ? ? ? Analog Input (Comparator) 0 0 0 0 0 0 X X X X X Digital Output (Comparator) 1 X 0 1 ? ? ? ? ? ? ? a.
PAGE 764
General-Purpose Input/Outputs (GPIOs) ■ ■ ■ ■ ■ ■ ■ GPIO Port J (AHB): 0x4006.0000 GPIO Port K (AHB): 0x4006.1000 GPIO Port L (AHB): 0x4006.2000 GPIO Port M (AHB): 0x4006.3000 GPIO Port N (AHB): 0x4006.4000 GPIO Port P (AHB): 0x4006.5000 GPIO Port Q (AHB): 0x4006.6000 Note that each GPIO module clock must be enabled before the registers can be programmed (see page 389). There must be a delay of 3 system clocks after the GPIO module clock is enabled before any GPIO module registers are accessed.
PAGE 765
Tiva™ TM4C129ENCPDT Microcontroller Table 10-7. GPIO Register Map Offset Name 0x000 Description See page Type Reset GPIODATA RW 0x0000.0000 GPIO Data 767 0x400 GPIODIR RW 0x0000.0000 GPIO Direction 768 0x404 GPIOIS RW 0x0000.0000 GPIO Interrupt Sense 769 0x408 GPIOIBE RW 0x0000.0000 GPIO Interrupt Both Edges 770 0x40C GPIOIEV RW 0x0000.0000 GPIO Interrupt Event 771 0x410 GPIOIM RW 0x0000.0000 GPIO Interrupt Mask 772 0x414 GPIORIS RO 0x0000.
PAGE 766
General-Purpose Input/Outputs (GPIOs) Table 10-7. GPIO Register Map (continued) Offset Name 0xFD4 Reset GPIOPeriphID5 RO 0x0000.0000 GPIO Peripheral Identification 5 812 0xFD8 GPIOPeriphID6 RO 0x0000.0000 GPIO Peripheral Identification 6 813 0xFDC GPIOPeriphID7 RO 0x0000.0000 GPIO Peripheral Identification 7 814 0xFE0 GPIOPeriphID0 RO 0x0000.0061 GPIO Peripheral Identification 0 815 0xFE4 GPIOPeriphID1 RO 0x0000.
PAGE 767
Tiva™ TM4C129ENCPDT Microcontroller Register 1: GPIO Data (GPIODATA), offset 0x000 The GPIODATA register is the data register. In software control mode, values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been configured as outputs through the GPIO Direction (GPIODIR) register (see page 768). In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus bits [9:2], must be set.
PAGE 768
General-Purpose Input/Outputs (GPIOs) Register 2: GPIO Direction (GPIODIR), offset 0x400 The GPIODIR register is the data direction register. Setting a bit in the GPIODIR register configures the corresponding pin to be an output, while clearing a bit configures the corresponding pin to be an input. All bits are cleared by a reset, meaning all GPIO pins are inputs by default. GPIO Direction (GPIODIR) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.
PAGE 769
Tiva™ TM4C129ENCPDT Microcontroller Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 The GPIOIS register is the interrupt sense register. Setting a bit in the GPIOIS register configures the corresponding pin to detect levels, while clearing a bit configures the corresponding pin to detect edges. All bits are cleared by a reset. Note: To prevent false interrupts, the following steps should be taken when re-configuring GPIO edge and interrupt sense registers: 1.
PAGE 770
General-Purpose Input/Outputs (GPIOs) Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 The GPIOIBE register allows both edges to cause interrupts. When the corresponding bit in the GPIO Interrupt Sense (GPIOIS) register (see page 769) is set to detect edges, setting a bit in the GPIOIBE register configures the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 771).
PAGE 771
Tiva™ TM4C129ENCPDT Microcontroller Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C The GPIOIEV register is the interrupt event register. Setting a bit in the GPIOIEV register configures the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register (see page 769). Clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in the GPIOIS register.
PAGE 772
General-Purpose Input/Outputs (GPIOs) Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 The GPIOIM register is the interrupt mask register. Setting a bit in the GPIOIM register allows interrupts that are generated by the corresponding pin to be sent to the interrupt controller on the combined interrupt signal. Clearing a bit prevents an interrupt on the corresponding pin from being sent to the interrupt controller. All bits are cleared by a reset.
PAGE 773
Tiva™ TM4C129ENCPDT Microcontroller Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 The GPIORIS register is the raw interrupt status register. A bit in this register is set when an interrupt condition occurs on the corresponding GPIO pin or if a µDMA done interrupt occurs. If the corresponding bit in the GPIO Interrupt Mask (GPIOIM) register (see page 772) is set, the interrupt is sent to the interrupt controller.
PAGE 774
General-Purpose Input/Outputs (GPIOs) Bit/Field Name Type Reset Description 7:0 RIS RO 0x00 GPIO Interrupt Raw Status Value Description 0 An interrupt condition has not occurred on the corresponding pin. 1 An interrupt condition has occurred on the corresponding pin. For edge-detect interrupts, this bit is cleared by writing a 1 to the corresponding bit in the GPIOICR register. For a GPIO level-detect interrupt, the bit is cleared when the level is deasserted.
PAGE 775
Tiva™ TM4C129ENCPDT Microcontroller Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 The GPIOMIS register is the masked interrupt status register. If a bit is set in this register, the corresponding interrupt has triggered an interrupt to the interrupt controller. If a bit is clear, either no interrupt has been generated, or the interrupt is masked. Note that if the Port B GPIOADCCTL register is cleared, PB4 can still be used as an external trigger for the ADC.
PAGE 776
General-Purpose Input/Outputs (GPIOs) Bit/Field Name Type Reset Description 7:0 MIS RO 0x00 GPIO Masked Interrupt Status Value Description 0 An interrupt condition on the corresponding pin is masked or has not occurred. 1 An interrupt condition on the corresponding pin has triggered an interrupt to the interrupt controller. For edge-detect interrupts, this bit is cleared by writing a 1 to the corresponding bit in the GPIOICR register.
PAGE 777
Tiva™ TM4C129ENCPDT Microcontroller Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C The GPIOICR register is the interrupt clear register. Writing a 1 to the DMAIC bit in this register clears the corresponding interrupt bit in the GPIORIS and GPIOMIS registers. For edge-detect interrupts, writing a 1 to the IC bit in the GPIOICR register clears the corresponding bit in the GPIORIS and GPIOMIS registers. If the interrupt is a level-detect, the IC bit in this register has no effect.
PAGE 778
General-Purpose Input/Outputs (GPIOs) Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 Note: Tamper pins enabled in the Hibernate Tamper IO Control and Status (HIBTPIO) register override the AFSEL configuration. The GPIOAFSEL register is the mode control select register. If a bit is clear, the pin is used as a GPIO and is controlled by the GPIO registers. Setting a bit in this register configures the corresponding GPIO line to be controlled by an associated peripheral.
PAGE 779
Tiva™ TM4C129ENCPDT Microcontroller Pull Up Select (GPIOPUR) register (see page 784), GPIO Pull-Down Select (GPIOPDR) register (see page 786), and GPIO Digital Enable (GPIODEN) register (see page 789) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 791) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 792) have been set.
PAGE 780
General-Purpose Input/Outputs (GPIOs) Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 The GPIODR2R register is the 2-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV2 bit for a GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and DRV8 bit in the GPIODR8R register are automatically cleared by hardware. By default, all GPIO pins have 2-mA drive.
PAGE 781
Tiva™ TM4C129ENCPDT Microcontroller Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 The GPIODR4R register is the 4-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV4 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and DRV8 bit in the GPIODR8R register are automatically cleared by hardware. Note: This register has no effect on port pins PL6 and PL7.
PAGE 782
General-Purpose Input/Outputs (GPIOs) Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 The GPIODR8R register is the 8-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV8 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and DRV4 bit in the GPIODR4R register are automatically cleared by hardware. The 8-mA setting is also used for high-current operation.
PAGE 783
Tiva™ TM4C129ENCPDT Microcontroller Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C The GPIOODR register is the open drain control register. Setting a bit in this register enables the open-drain configuration of the corresponding GPIO pad. When open-drain mode is enabled, the corresponding bit should also be set in the GPIO Digital Enable (GPIODEN) register (see page 789).
PAGE 784
General-Purpose Input/Outputs (GPIOs) Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 The GPIOPUR register is the pull-up control register. When a bit is set, a weak pull-up resistor on the corresponding GPIO signal is enabled. Setting a bit in GPIOPUR automatically clears the corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 786). Write access to this register is protected with the GPIOCR register.
PAGE 785
Tiva™ TM4C129ENCPDT Microcontroller GPIO Pull-Up Select (GPIOPUR) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (AHB) base: 0x4006.0000 GPIO Port K (AHB) base: 0x4006.1000 GPIO Port L (AHB) base: 0x4006.2000 GPIO Port M (AHB) base: 0x4006.
PAGE 786
General-Purpose Input/Outputs (GPIOs) Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 The GPIOPDR register is the pull-down control register. When a bit is set, a weak pull-down resistor on the corresponding GPIO signal is enabled. Setting a bit in GPIOPDR automatically clears the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 784). Important: The table below shows special consideration GPIO pins.
PAGE 787
Tiva™ TM4C129ENCPDT Microcontroller GPIO Pull-Down Select (GPIOPDR) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (AHB) base: 0x4006.0000 GPIO Port K (AHB) base: 0x4006.1000 GPIO Port L (AHB) base: 0x4006.2000 GPIO Port M (AHB) base: 0x4006.
PAGE 788
General-Purpose Input/Outputs (GPIOs) Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 The GPIOSLR register is the slew rate control register. Slew rate control is only available when using the 8-mA, 10-mA or 12-mA drive strength option. The selection of drive strength is done through the GPIO Drive Select (GPIODRnR registers and the GPIO Peripheral Configuration (GPIOPC) register. Note: This register has no effect on port pins PL6 and PL7.
PAGE 789
Tiva™ TM4C129ENCPDT Microcontroller Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C Note: Pins configured as digital inputs are Schmitt-triggered. The GPIODEN register is the digital enable register. By default, all GPIO signals except those listed below are configured out of reset to be undriven (tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver.
PAGE 790
General-Purpose Input/Outputs (GPIOs) GPIO Digital Enable (GPIODEN) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (AHB) base: 0x4006.0000 GPIO Port K (AHB) base: 0x4006.1000 GPIO Port L (AHB) base: 0x4006.2000 GPIO Port M (AHB) base: 0x4006.
PAGE 791
Tiva™ TM4C129ENCPDT Microcontroller Register 19: GPIO Lock (GPIOLOCK), offset 0x520 The GPIOLOCK register enables write access to the GPIOCR register (see page 792). Writing 0x4C4F.434B to the GPIOLOCK register unlocks the GPIOCR register. Writing any other value to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns the lock status rather than the 32-bit value that was previously written.
PAGE 792
General-Purpose Input/Outputs (GPIOs) Register 20: GPIO Commit (GPIOCR), offset 0x524 The GPIOCR register is the commit register. The value of the GPIOCR register determines which bits of the GPIOAFSEL, GPIOPUR, GPIOPDR, and GPIODEN registers are committed when a write to these registers is performed. If a bit in the GPIOCR register is cleared, the data being written to the corresponding bit in the GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN registers cannot be committed and retains its previous value.
PAGE 793
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 7:0 CR - - Description GPIO Commit Value Description 0 The corresponding GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN bits cannot be written. 1 The corresponding GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN bits can be written. Note: The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the NMI pin and the four JTAG/SWD pins (see “Signal Tables” on page 1896 for pin numbers).
PAGE 794
General-Purpose Input/Outputs (GPIOs) Register 21: GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 Important: This register is only valid for ports and pins that can be used as ADC AINx inputs. If any pin is to be used as an ADC input, the appropriate bit in GPIOAMSEL must be set to disable the analog isolation circuit. The GPIOAMSEL register controls isolation circuits to the analog side of a unified I/O pad. Because the GPIOs may be driven by a 3.
PAGE 795
Tiva™ TM4C129ENCPDT Microcontroller Register 22: GPIO Port Control (GPIOPCTL), offset 0x52C The GPIOPCTL register is used in conjunction with the GPIOAFSEL register and selects the specific peripheral signal for each GPIO pin when using the alternate function mode. Most bits in the GPIOAFSEL register are cleared on reset, therefore most GPIO pins are configured as GPIOs by default. When a bit is set in the GPIOAFSEL register, the corresponding GPIO signal is controlled by an associated peripheral.
PAGE 796
General-Purpose Input/Outputs (GPIOs) GPIO Port Control (GPIOPCTL) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (AHB) base: 0x4006.0000 GPIO Port K (AHB) base: 0x4006.1000 GPIO Port L (AHB) base: 0x4006.2000 GPIO Port M (AHB) base: 0x4006.
PAGE 797
Tiva™ TM4C129ENCPDT Microcontroller Register 23: GPIO ADC Control (GPIOADCCTL), offset 0x530 This register is used to configure a GPIO pin as a source for the ADC trigger. Note that if the Port B GPIOADCCTL register is cleared, PB4 can still be used as an external trigger for the ADC. This is a legacy mode which allows code written for previous devices to operate on this microcontroller. GPIO ADC Control (GPIOADCCTL) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.
PAGE 798
General-Purpose Input/Outputs (GPIOs) Register 24: GPIO DMA Control (GPIODMACTL), offset 0x534 This register is used to configure a GPIO pin as a source for the μDMA trigger. GPIO DMA Control (GPIODMACTL) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (AHB) base: 0x4005.
PAGE 799
Tiva™ TM4C129ENCPDT Microcontroller Register 25: GPIO Select Interrupt (GPIOSI), offset 0x538 This register is used to enable individual interrupts for each pin. Note: This register is only available on Port P and Port Q. GPIO Select Interrupt (GPIOSI) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (AHB) base: 0x4005.
PAGE 800
General-Purpose Input/Outputs (GPIOs) Register 26: GPIO 12-mA Drive Select (GPIODR12R), offset 0x53C The GPIODR12R register is the 12-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. Note: This register has no effect on port pins PL6 and PL7 or PM[7:4]. GPIO 12-mA Drive Select (GPIODR12R) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (AHB) base: 0x4005.
PAGE 801
Tiva™ TM4C129ENCPDT Microcontroller Register 27: GPIO Wake Pin Enable (GPIOWAKEPEN), offset 0x540 This register is used to configure K[7:4] as a wake enable source for the hibernation module. The wake level must be programmed in the GPIOWAKELVL register at offset 0x544. In order for this register configuration to become implemented, the WUUNLK bit needs to be set in the HIBIO register at offset 0x02C in the hibernation module. Note: This register is only available on Port K.
PAGE 802
General-Purpose Input/Outputs (GPIOs) Bit/Field Name Type Reset 5 WAKEP5 RW 0 Description K[5] Wake Enable Value Description 4 WAKEP4 RW 0 0 Wake-on level is not enabled. 1 Wake-on level is enabled. K[4] Wake Enable Value Description 3:0 reserved RO 0 0 Wake-on level is not enabled. 1 Wake-on level is enabled. Software should not rely on the value of a reserved bit.
PAGE 803
Tiva™ TM4C129ENCPDT Microcontroller Register 28: GPIO Wake Level (GPIOWAKELVL), offset 0x544 This register is used to configure the wake level for K[7:4] in the hibernation module. The wake source must be enabled in the GPIOWAKEPEN register at offset 0x540. In order for this register configuration to become implemented, the WUUNLK bit needs to be set in the HIBIO register at offset 0x02C in the hibernation module. Note: This register is only available on Port K.
PAGE 804
General-Purpose Input/Outputs (GPIOs) Bit/Field Name Type Reset 5 WAKELVL5 RW 0 Description K[5] Wake Level Value Description 4 WAKELVL4 RW 0 0 Wake level low 1 Wake level high K[4] Wake Level Value Description 3:0 reserved RO 0 0 Wake level low 1 Wake level high Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
PAGE 805
Tiva™ TM4C129ENCPDT Microcontroller Register 29: GPIO Wake Status (GPIOWAKESTAT), offset 0x548 This register indicates the GPIO wake event status. If a register bit has been set for K[7:4] , a wake event signal has been sent to the Hibernate module. Note: This register is only available on Port K. GPIO Wake Status (GPIOWAKESTAT) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (AHB) base: 0x4005.
PAGE 806
General-Purpose Input/Outputs (GPIOs) Bit/Field Name Type Reset 5 STAT5 RO 0 Description K[5] Wake Status This is for future use. Value Description 4 STAT4 RO 0 0 Pin is not wake up source 1 Pin wake event asserted to hibernate module K[4] Wake Status Value Description 3:0 reserved RO 0 0 Pin is not wake up source 1 Pin wake event asserted to hibernate module Software should not rely on the value of a reserved bit.
PAGE 807
Tiva™ TM4C129ENCPDT Microcontroller Register 30: GPIO Peripheral Property (GPIOPP), offset 0xFC0 The GPIOPP register provides information regarding the GPIO properties. GPIO Peripheral Property (GPIOPP) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (AHB) base: 0x4005.
PAGE 808
General-Purpose Input/Outputs (GPIOs) Register 31: GPIO Peripheral Configuration (GPIOPC), offset 0xFC4 This GPIOPC register controls the extended drive modes of the GPIO and must be configured before the GPIODRnR registers in order for extended drive mode to take effect. When the EDE bit in GPIOPP register is set and the EDMn bit field is non-zero, the GPIODRnR registers do not drive their default value, but instead output an incremental drive strength, which has an additive effect.
PAGE 809
Tiva™ TM4C129ENCPDT Microcontroller GPIO Peripheral Configuration (GPIOPC) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (AHB) base: 0x4006.0000 GPIO Port K (AHB) base: 0x4006.1000 GPIO Port L (AHB) base: 0x4006.2000 GPIO Port M (AHB) base: 0x4006.
PAGE 810
General-Purpose Input/Outputs (GPIOs) Bit/Field Name Type Reset 1:0 EDM0 RW 0 Description Extended Drive Mode Bit 0 This field controls extended drive modes of bit 0 of the GPIO port. Note that depending on the encoding used the GPIO drive strength control registers may change their decoding. Moreover, the write one, clear other register behavior may be disabled. Value Description 0x0 Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal.
PAGE 811
Tiva™ TM4C129ENCPDT Microcontroller Register 32: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 4 (GPIOPeriphID4) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.
PAGE 812
General-Purpose Input/Outputs (GPIOs) Register 33: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 5 (GPIOPeriphID5) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.
PAGE 813
Tiva™ TM4C129ENCPDT Microcontroller Register 34: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 6 (GPIOPeriphID6) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.
PAGE 814
General-Purpose Input/Outputs (GPIOs) Register 35: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 7 (GPIOPeriphID7) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.
PAGE 815
Tiva™ TM4C129ENCPDT Microcontroller Register 36: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 0 (GPIOPeriphID0) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.
PAGE 816
General-Purpose Input/Outputs (GPIOs) Register 37: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 1 (GPIOPeriphID1) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.
PAGE 817
Tiva™ TM4C129ENCPDT Microcontroller Register 38: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 2 (GPIOPeriphID2) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.
PAGE 818
General-Purpose Input/Outputs (GPIOs) Register 39: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 3 (GPIOPeriphID3) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.
PAGE 819
Tiva™ TM4C129ENCPDT Microcontroller Register 40: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 0 (GPIOPCellID0) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.
PAGE 820
General-Purpose Input/Outputs (GPIOs) Register 41: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 1 (GPIOPCellID1) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.
PAGE 821
Tiva™ TM4C129ENCPDT Microcontroller Register 42: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 2 (GPIOPCellID2) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.
PAGE 822
General-Purpose Input/Outputs (GPIOs) Register 43: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 3 (GPIOPCellID3) GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (AHB) base: 0x4005.
PAGE 823
Tiva™ TM4C129ENCPDT Microcontroller 11 External Peripheral Interface (EPI) The External Peripheral Interface is a high-speed parallel bus for external peripherals or memory. It has several modes of operation to interface gluelessly to many types of external devices. The External Peripheral Interface is similar to a standard microprocessor address/data bus, except that it must typically be connected to just one type of external device.
PAGE 824
External Peripheral Interface (EPI) – Support for up to 512 Mb PSRAM in quad chip select mode, with dedicated configuration register read and write enable.
PAGE 825
Tiva™ TM4C129ENCPDT Microcontroller Figure 11-1. EPI Block Diagram General Parallel GPIO NBRFIFO 8 x 32 bits WFIFO SDRAM 4 x 32 bits AHB Bus Interface With DMA AHB EPI 31:0 Host Bus Baud Rate Control (Clock) Wide Parallel Interface 11.2 Signal Description The following table lists the external signals of the EPI controller and describes the function of each. The EPI controller signals are alternate functions for GPIO signals and default to be GPIO signals at reset.
PAGE 826
External Peripheral Interface (EPI) Table 11-1. External Peripheral Interface Signals (128TQFP) (continued) Pin Name 11.3 Pin Number Pin Mux / Pin Assignment EPI0S8 40 Pin Type Buffer Type Description PA6 (15) I/O TTL EPI module 0 signal 8. EPI0S9 41 PA7 (15) I/O TTL EPI module 0 signal 9. EPI0S10 50 PG1 (15) I/O TTL EPI module 0 signal 10. EPI0S11 49 PG0 (15) I/O TTL EPI module 0 signal 11. EPI0S12 75 PM3 (15) I/O TTL EPI module 0 signal 12.
PAGE 827
Tiva™ TM4C129ENCPDT Microcontroller to continue operation. In addition, write data can also be stored in the WFIFO to allow multiple writes with no stalls. Note: Both the WTAV bit field in the EPIWFIFOCNT register and the WBUSY bit in the EPISTAT register must be polled to determine if there is a current write transaction from the WFIFO. If both of these bits are clear, then a new bus access may begin. Main read and write operations can be performed in subsets of the range 0x6000.0000 to 0xDFFF.FFFF.
PAGE 828
External Peripheral Interface (EPI) To ensure that the cancel is complete, the following algorithm is used (using the EPIRPSTD0 register for example): EPIRPSTD0 = 0; while ((EPISTAT & 0x11) == 0x10) ; // we are active and busy // if here, then other one is active or interface no longer busy cnt = (EPIRADDR0 – original_address) / EPIRSIZE0; // count of values read cnt -= values_read_so_far; // cnt is now number left in FIFO while (cnt--) value = EPIREADFIFO; // drain The above algorithm can be optimized in
PAGE 829
Tiva™ TM4C129ENCPDT Microcontroller The size of the FIFOs must be taken into consideration when configuring the µDMA to transfer data to and from the EPI. The arbitration size should be 4 or less when writing to EPI address space and 8 or less when reading from EPI address space. 11.4 Initialization and Configuration To enable and initialize the EPI controller, the following steps are necessary: 1. Enable the EPI module using the RCGCEPI register. See page 393. 2.
PAGE 830
External Peripheral Interface (EPI) 11.4.1 EPI Interface Options There are a variety of memories and peripherals that can interface to the EPI module. Table 11-2 on page 830 shows the various configurations with their maximum performance. Table 11-2. EPI Interface Options Interface 11.4.
PAGE 831
Tiva™ TM4C129ENCPDT Microcontroller See “External Peripheral Interface (EPI)” on page 1977 for timing details for the SDRAM mode. 11.4.2.1 External Signal Connections Table 11-3 on page 831 defines how EPI module signals should be connected to SDRAMs. The table applies when using a x16 SDRAM up to 512 megabits. Note that the EPI signals must use 8-mA drive when interfacing to SDRAM, see page 782. Any unused EPI controller signals can be used as GPIOs or another alternate function. Table 11-3.
PAGE 832
External Peripheral Interface (EPI) expressed in MHz. So, 50 MHz is 1000/50=20 ns, or 0.02 μs. A typical SDRAM is 4096 rows per bank if the system clock is running at 50 MHz with an EPIBAUD register value of 0: RFSH = (64000/4096) / 0.02 = 15.625 μs / 0.02 μs = 781.25 The default value in the RFSH field is 750 decimal or 0x2EE to allow for a margin of safety and providing 15 μs per refresh. It is important to note that this number should always be smaller or equal to what is required by the above equation.
PAGE 833
Tiva™ TM4C129ENCPDT Microcontroller 11.4.2.5 Normal Read Cycle Figure 11-3 on page 833 shows a normal read cycle of n halfwords; n can be 1 or 2. The cycle begins with the Activate command and the row address on the EPI0S[15:0] signals. With the programmed CAS latency of 2, the Read command with the column address on the EPI0S[15:0] signals follows after 2 clock cycles. Following one more NOP cycle, data is read in on the EPI0S[15:0] signals on every rising clock edge.
PAGE 834
External Peripheral Interface (EPI) Figure 11-4. SDRAM Write Cycle CLK (EPI0S31) CKE (EPI0S30) CSn (EPI0S29) WEn (EPI0S28) RASn (EPI0S19) CASn (EPI0S18) DQMH, DQML (EPI0S [17:16]) AD [15:0] (EPI0S [15:0]) Row Column-1 Activate NOP Data 0 Data 1 ... Data n Burst Term Write AD [15:0] driven out AD [15:0] driven out 11.4.3 Host Bus Mode Host Bus supports the traditional 8-bit and 16-bit interfaces popularized by the 8051 devices and SRAM devices, as well as PSRAM and NOR Flash memory.
PAGE 835
Tiva™ TM4C129ENCPDT Microcontroller register, the CSCFG field and the CSCFGEXT bit in the EPIHBnCFGn register, and the BSEL bit in the EPIHB16CFG register. The CSCFGEXT bit extends the chip select configuration possibilities by providing the most significant bit of the CSCFG field. Refer to Table 11-4 on page 835 for the possible ALE and chip select options that can be programmed by the combination of the CSCFGEXT and CSCFG bits. Note that CSCFGEXT is the most significant bit. Table 11-4.
PAGE 836
External Peripheral Interface (EPI) In quad chip select mode (CSCFGEXT is 0x1 and CSCFG is 0x1 or 0x2 in the EPIHBnCFG2 register), both the peripheral and the memory space must be enabled. In the EPIADDRMAP register, the EPADR field is 0x3, the ERADR field is 0x3, and the ECADR field is 0x0. With this configuration, CS0n asserts for the address range beginning at 0x6000.0000, CS1n asserts for 0x8000.0000, CS2n for 0xA000.0000, and CS3n for 0xC000.0000.
PAGE 837
Tiva™ TM4C129ENCPDT Microcontroller Table 11-6. Chip Select Configuration Register Assignment a Configuration Register Corresponding Chip Select EPIHBnCFG CS0n EPIHBnCFG2 CS1n EPIHBnCFG3 CS2n EPIHBnCFG4 CS3n a. If the CSBAUD bit in the EPIHBnCFG2 register is clear and multiple chip selects are enabled, then all chip selects are configured by the MODE bit field in the EPIHBnCFG register. Note that multiple chip select modes do not allow the intermixing of Host-Bus 8 and Host-Bus16 modes.
PAGE 838
External Peripheral Interface (EPI) Table 11-7.
PAGE 839
Tiva™ TM4C129ENCPDT Microcontroller field in the EPIHB8CFGn register and on the chip select configuration selected by the CSCFG and CSCFGEXT field in the EPIHB8CFG2 register. Although the EPI0S31 signal can be configured for the EPI clock signal in Host-Bus mode, it is not required and should be configured as a GPIO to reduce EMI in the system. Any unused EPI controller signals can be used as GPIOs or another alternate function. Table 11-8.
PAGE 840
External Peripheral Interface (EPI) Table 11-8. EPI Host-Bus 8 Signal Connections (continued) EPI Signal CSCFG HB8 Signal (MODE =ADMUX) HB8 Signal (MODE =ADNOMUX (Cont.
PAGE 841
Tiva™ TM4C129ENCPDT Microcontroller Table 11-8. EPI Host-Bus 8 Signal Connections (continued) EPI Signal EPI0S35 CSCFG HB8 Signal (MODE =ADMUX) 0x0 X X X 0x1 X X X 0x2 X X X 0x3 X X X 0x4 X X X CRE CRE 0x5 0x6 HB8 Signal (MODE =ADNOMUX (Cont. Read)) HB8 Signal (MODE =XFIFO) X X a. "X" indicates the state of this field is a don't care. b. When an entry straddles several row, the signal configuration is the same for all rows. c. The clock signal is not required for this mode.
PAGE 842
External Peripheral Interface (EPI) Table 11-9. EPI Host-Bus 16 Signal Connections (continued) EPI Signal CSCFG BSEL HB16 Signal (MODE =ADMUX) HB16 Signal (MODE =ADNOMUX (Cont.
PAGE 843
Tiva™ TM4C129ENCPDT Microcontroller Table 11-9.
PAGE 844
External Peripheral Interface (EPI) The RDYEN in the EPIHBnCFG enables the monitoring of the external iRDY pin to stall accesses. On the rising edge of EPI clock, if iRDY is low, access is stalled. The IRDYDLY can program the number of EPI clock cycles in advance to the stall (1,2 or 3) as shown in Figure 11-5 on page 844. This is a conceptual timing diagram of how the iRDY signal works with different IRDYDLY configurations.
PAGE 845
Tiva™ TM4C129ENCPDT Microcontroller non-blocking read activity during the CRE read or write-enable transfer. During a write to the PSRAM's CR, the configuration data is written out on data pins [20:0] of the EPI bus. For a PSRAM configuration read access, the RDCRE bit in the EPIHB16CFG register is set to signal that the next access is a read of the PSRAM configuration register (CR). The address for the CR is written to bits CR[19:18] of the EPIHBPSRAM register.
PAGE 846
External Peripheral Interface (EPI) 7. Set the WRCRE bit in the EPIHB16CFGn register to initiate a write from the EPIHBPSRAM register to PSRAM's CR register. Note: If the PSRAM's CR register must be reprogrammed after initialization, the application should allow the previous transfer to complete before beginning configuration to ensure proper PSRAM functionality. Table 11-10.
PAGE 847
Tiva™ TM4C129ENCPDT Microcontroller Figure 11-7. PSRAM Burst Read EPICLK EPI0S31 EPI0S[19:0] ADDRESS ALE Latency (3 clocks) CSn RDn WRn EPI0S29 iRDY EPI0S32 EPI0S[15:0] DATA0 DATA1 DATA2 DATA3 BSELn Figure 11-8.
PAGE 848
External Peripheral Interface (EPI) Note that if a read or write transfer attempts to begin during a refresh event, the transfer is held off by the assertion of the iRDY pin by the memory to the EPI module. Figure 11-9 on page 848 and Figure 11-10 on page 849 depict the delay in data transfer during a refresh collision. Figure 11-9.
PAGE 849
Tiva™ TM4C129ENCPDT Microcontroller Figure 11-10. Write Delay During Refresh Event EPICLK EPI0S31 EPI0S[19:0] ADDRESS ALE CSn OEn EPI0S28 WRn EPI0S29 BSELn iRDY EPI0S32 EPI0S[15:0] DATA0 DATA1 DATA2 DATA3 One wait state 11.4.3.3 Host Bus 16-bit Muxed Interface Figure 11-11 on page 850 shows how to connect the EPI signals to a 16-bit SRAM and a 16-bit Flash memory with muxed address and memory using byte selects and dual chip selects with ALE.
PAGE 850
External Peripheral Interface (EPI) Figure 11-11. Example Schematic for Muxed Host-Bus 16 Mode EPI_16_BUS A[0:15] U1 EPI0 EPI1 EPI2 EPI3 EPI4 EPI5 EPI6 EPI7 47 46 44 43 41 40 38 37 EPI8 EPI9 EPI10 EPI11 EPI12 EPI13 EPI14 EPI15 36 35 33 32 30 29 27 26 EPI30 25 2LE 48 1LE 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 1 1OE 24 2OE +3.
PAGE 851
Tiva™ TM4C129ENCPDT Microcontroller controls the baud rate of CS2n and the COUNT1 bit field is programmed to control the baud rate of CS3n. Additionally, the Host-Bus mode provides read and write wait states for the data portion to support different classes of device. These wait states stretch the data period (hold the rising edge of data strobe) and may be used in all four sub-modes. The wait states are set using the WRWS and RDWS bits in the EPI Host-Bus n Configuration (EPIHBnCFGn) register.
PAGE 852
External Peripheral Interface (EPI) 2. Address and data are separate with 8 or 16 bits of data and up to 20 bits of address (1 MB). This scheme is used by more modern 8051 devices, as well as some PIC and ATmega parts. This mode is generally used with SRAMs in continuous read modes, many EEPROMs, and many NOR Flash memory devices. Note that there is no hardware command write support for Flash memory devices; this mode should only be used for Flash memory devices programmed at manufacturing time.
PAGE 853
Tiva™ TM4C129ENCPDT Microcontroller Figure 11-12. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 ALE (EPI0S30) CSn (EPI0S30) WRn (EPI0S29) RDn/OEn (EPI0S28) BSEL0n/ BSEL1na Address Data a Data BSEL0n and BSEL1n are available in Host-Bus 16 mode only. Figure 11-13. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 ALE (EPI0S30) CSn (EPI0S30) WRn (EPI0S29) RDn/OEn (EPI0S28) BSEL0n/ BSEL1na Address Data a Data BSEL0n and BSEL1n are available in Host-Bus 16 mode only.
PAGE 854
External Peripheral Interface (EPI) Figure 11-14. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH = 0, RDHIGH = 0 ALE (EPI0S30) CSn (EPI0S30) WRn (EPI0S29) RDn/OEn (EPI0S28) BSEL0n/ BSEL1na Address (high order, non muxed) Muxed Address/Data a Address Data BSEL0n and BSEL1n are available in Host-Bus 16 mode only.
PAGE 855
Tiva™ TM4C129ENCPDT Microcontroller FIFO mode accesses are the same as normal read and write accesses, except that the ALE signal and address pins are not present. Two input signals can be used to indicate when the XFIFO is full or empty to gate transactions and avoid overruns and underruns. The FFULL and FEMPTY signals are synchronized and must be recognized as asserted by the microcontroller for 2 system clocks before they affect transaction status.
PAGE 856
External Peripheral Interface (EPI) – Reading 20 sensors at fixed time periods by configuring 20 pins to be inputs, configuring the COUNT0 field in the EPIBAUD register to some divider, and then using non-blocking reads. – Implementing a very wide ganged PWM/PCM with fixed frequency for driving actuators, LEDs, etc. ■ General custom interfaces of any speed.
PAGE 857
Tiva™ TM4C129ENCPDT Microcontroller used as GPIOs or for other functions. For example, when using a 4-bit address with an 8-bit data, the pins assigned to EPIS0[23:8] can be assigned to other functions. ■ Data may be 8 bits, 16 bits, 24 bits, or 32 bits (controlled by the DSIZE field in the EPIGPCFG register).
PAGE 858
External Peripheral Interface (EPI) Table 11-12.
PAGE 859
Tiva™ TM4C129ENCPDT Microcontroller Figure 11-20. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, WR2CYC=1 CLOCK (EPI0S31) FRAME (EPI0S30) RD (EPI0S29) WR (EPI0S28) Address Data Data Data Read Write Figure 11-21. Read Accesses, FRM50=0, FRMCNT=0 CLOCK (EPI0S31) FRAME (EPI0S30) RD (EPI0S29) WR (EPI0S28) Addr1 Address Addr2 Data1 Data Addr3 Data2 Data3 FRAME Signal Operation The operation of the FRAME signal is controlled by the FRMCNT and FRM50 bits.
PAGE 860
External Peripheral Interface (EPI) Figure 11-22. FRAME Signal Operation, FRM50=0 and FRMCNT=0 Clock (EPI0S31) WR (EPI0S28) RD (EPI0S29) Frame (EPI0S30) If the FRMCNT field is 0x1, then the FRAME signal pulses high during every other read or write access, see Figure 11-23 on page 860. Figure 11-23.
PAGE 861
Tiva™ TM4C129ENCPDT Microcontroller Figure 11-26. FRAME Signal Operation, FRM50=1 and FRMCNT=1 Clock (EPI0S31) WR (EPI0S28) RD (EPI0S29) Frame (EPI0S30) When FRMCNT=2, the FRAME signal transitions the rising edge of the WR or RD strobes for every third access, and so on for every value of FRMCNT, see Figure 11-27 on page 861. Figure 11-27.
PAGE 862
External Peripheral Interface (EPI) Figure 11-29. EPI Clock Operation, CLKGATE=1, WR2CYC=1 Clock (EPI0S31) WR (EPI0S28) Address Data 11.5 Register Map Table 11-13 on page 862 lists the EPI registers. The offset listed is a hexadecimal increment to the register's address, relative to the base address of 0x400D.0000. Note that the EPI controller clock must be enabled before the registers can be programmed (see page 393).
PAGE 863
Tiva™ TM4C129ENCPDT Microcontroller Table 11-13. External Peripheral Interface (EPI) Register Map (continued) Offset Name 0x034 Description See page Type Reset EPIRADDR1 RW 0x0000.0000 EPI Read Address 1 904 0x038 EPIRPSTD1 RW 0x0000.0000 EPI Non-Blocking Read Data 1 905 0x060 EPISTAT RO 0x0000.
PAGE 864
External Peripheral Interface (EPI) 11.6 Register Descriptions This section lists and describes the EPI registers, in numerical order by address offset.
PAGE 865
Tiva™ TM4C129ENCPDT Microcontroller Register 1: EPI Configuration (EPICFG), offset 0x000 Important: The MODE field determines which configuration register is accessed for offsets 0x010 and 0x014. Any write to the EPICFG register resets the register contents at offsets 0x010 and 0x014. The configuration register is used to enable the block, select a mode, and select the basic pin use (based on the mode).
PAGE 866
External Peripheral Interface (EPI) Bit/Field Name Type Reset Description 3:0 MODE RW 0x0 Mode Select Value Description 0x0 General Purpose General-Purpose mode. Control, address, and data pins are configured using the EPIGPCFG and EPIGPCFG2 registers. 0x1 SDRAM Supports SDR SDRAM. Control, address, and data pins are configured using the EPISDRAMCFG register. 0x2 8-Bit Host-Bus (HB8) Host-bus 8-bit interface (also known as the MCU interface).
PAGE 867
Tiva™ TM4C129ENCPDT Microcontroller Register 2: EPI Main Baud Rate (EPIBAUD), offset 0x004 The system clock is used internally to the EPI Controller. The baud rate counter can be used to divide the system clock down to control the speed on the external interface. If the mode selected emits an external EPI clock, this register defines the EPI clock emitted. If the mode selected does not use an EPI clock, this register controls the speed of changes on the external interface.
PAGE 868
External Peripheral Interface (EPI) Bit/Field Name Type Reset 31:16 COUNT1 RW 0x0000 Description Baud Rate Counter 1 This bit field is only valid with multiple chip selects which are enabled when the CSCFG field is 0x2 or 0x3 or the CSCFGEXT field is set to 1, with CSCFG field as 0x1 or 0x2 and the CSBAUD bit is set in the EPIHBnCFG2 register. This bit field contains a counter used to divide the system clock by the count. A count of 0 means the system clock is used as is.
PAGE 869
Tiva™ TM4C129ENCPDT Microcontroller Register 3: EPI Main Baud Rate (EPIBAUD2), offset 0x008 The system clock is used internally to the EPI Controller. The baud rate counter can be used to divide the system clock down to control the speed on the external interface. If the mode selected emits an external EPI clock, this register defines the EPI clock emitted. If the mode selected does not use an EPI clock, this register controls the speed of changes on the external interface.
PAGE 870
External Peripheral Interface (EPI) Bit/Field Name Type Reset 15:0 COUNT0 RW 0x0000 Description CS2n Baud Rate Counter 0 This bit field contains a counter used to divide the system clock by the count. A count of 0 means the system clock is unchanged. This bit field is only valid when quad chip selects are enabled by setting the CSCFGEXT to 1 and the CSCFG field to 0x1 or 0x2. In addition, the CSBAUD bit must be set in the EPIHBnCFG2 register.
PAGE 871
Tiva™ TM4C129ENCPDT Microcontroller Register 4: EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 Important: The MODE field in the EPICFG register determines which configuration register is accessed for offsets 0x010 and 0x014. To access EPISDRAMCFG, the MODE field must be 0x1. The SDRAM Configuration register is used to specify several parameters for the SDRAM controller. Note that this register is reset when the MODE field in the EPICFG register is changed.
PAGE 872
External Peripheral Interface (EPI) Bit/Field Name Type Reset 15:10 reserved RO 0x0 9 SLEEP RW 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sleep Mode Value Description 8:2 reserved RO 0 1:0 SIZE RW 0x0 0 No effect. 1 The SDRAM is put into low power state, but is self-refreshed.
PAGE 873
Tiva™ TM4C129ENCPDT Microcontroller Register 5: EPI Host-Bus 8 Configuration (EPIHB8CFG), offset 0x010 Important: The MODE field in the EPICFG register determines which configuration register is accessed for offsets 0x010 and 0x014. To access EPIHB8CFG, the MODE field must be 0x2. The Host Bus 8 Configuration register is activated when the HB8 mode is selected. The HB8 mode supports muxed address/data (overlay of lower 8 address and all 8 data pins), separate address/data, and address-less FIFO mode.
PAGE 874
External Peripheral Interface (EPI) Bit/Field Name Type Reset Description 31 CLKGATE RW 0 Clock Gated Value Description 0 The EPI clock is free running. 1 The EPI clock is held low. Note: 30 CLKGATEI RW 0 A software application should only set the CLKGATE bit when there are no pending transfers or no EPI register access has been issued. Clock Gated when Idle Value Description 0 The EPI clock is free running.
PAGE 875
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 23 XFFEN RW 0 Description External FIFO FULL Enable Value Description 22 XFEEN RW 0 0 No effect. 1 An external FIFO full signal can be used to control write cycles. If this bit is set and the FFULL full signal is high, XFIFO writes are stalled. External FIFO EMPTY Enable Value Description 21 WRHIGH RW 0 0 No effect. 1 An external FIFO empty signal can be used to control read cycles.
PAGE 876
External Peripheral Interface (EPI) Bit/Field Name Type Reset 7:6 WRWS RW 0x0 Description Write Wait States This field adds wait states to the data phase of CS0n (the address phase is not affected). The effect is to delay the rising edge of WRn (or the falling edge of WR). Each wait state adds 2 EPI clock cycles to the access time. The WRWSM bit in the EPIHB8TIME register can decrease the number of wait states by 1 EPI clock cycle for greater granularity. This field is not applicable in BURST mode.
PAGE 877
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1:0 MODE RW 0x0 Description Host Bus Sub-Mode This field determines which of four Host Bus 8 sub-modes to use. Sub-mode use is determined by the connected external peripheral. See Table 11-8 on page 839 for information on how this bit field affects the operation of the EPI signals. When used with multiple chip select option and the CSBAUD bit is set to 1 in the EPIHB8CFG2 register, this configuration is for CS0n.
PAGE 878
External Peripheral Interface (EPI) Register 6: EPI Host-Bus 16 Configuration (EPIHB16CFG), offset 0x010 Important: The MODE field in the EPICFG register determines which configuration register is accessed for offsets 0x010 and 0x014. To access EPIHB16CFG, the MODE field must be 0x3. The Host Bus 16 sub-configuration register is activated when the HB16 mode is selected.
PAGE 879
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset Description 31 CLKGATE RW 0 Clock Gated Value Description 0 The EPI clock is free running. 1 The EPI clock is held low. Note: 30 CLKGATEI RW 0 A software application should only set the CLKGATE bit when there are no pending transfers or no EPI register access has been issued. Clock Gated Idle Value Description 0 The EPI clock is free running.
PAGE 880
External Peripheral Interface (EPI) Bit/Field Name Type Reset 23 XFFEN RW 0 Description External FIFO FULL Enable Value Description 22 XFEEN RW 0 0 No effect. 1 An external FIFO full signal can be used to control write cycles. If this bit is set and the FFULL signal is high, XFIFO writes are stalled. External FIFO EMPTY Enable Value Description 21 WRHIGH RW 0 0 No effect. 1 An external FIFO empty signal can be used to control read cycles.
PAGE 881
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 17 RDCRE RW 0 Description PSRAM Configuration Register Read Enables read of PSRAM configuration registers. With the RDCRE set, the next access is a read of the PSRAM's Configuration Register (CR). This bit self clears once the read-enabled CRE access is complete. The address for the CRE access is located at EPIHBPSRAM[19:18]. The read data is returned on EPIHBPSRAM[15:0]. Value Description 16 BURST RW 0 0 No Action.
PAGE 882
External Peripheral Interface (EPI) Bit/Field Name Type Reset 5:4 RDWS RW 0x0 Description Read Wait States This field adds wait states to the data phase of CS0n (the address phase is not affected). The effect is to delay the rising edge of RDn/Oen (or the falling edge of RD). Each wait state adds 2 EPI clock cycles to the access time. The RDWSM bit in the EPIHB16TIME register can decrease the number of wait states by 1 EPI clock cycle for greater granularity.
PAGE 883
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1:0 MODE RW 0x0 Description Host Bus Sub-Mode This field determines which of three Host Bus 16 sub-modes to use. Sub-mode use is determined by the connected external peripheral. See Table 11-9 on page 841 for information on how this bit field affects the operation of the EPI signals. When used with multiple chip select option and the CSBAUD bit is set to 1 in the EPIHB16CFG2 register, this configuration is for CS0n.
PAGE 884
External Peripheral Interface (EPI) Register 7: EPI General-Purpose Configuration (EPIGPCFG), offset 0x010 Important: The MODE field in the EPICFG register determines which configuration register is accessed for offsets 0x010 and 0x014. To access EPIGPCFG, the MODE field must be 0x0. The General-Purpose configuration register is used to configure the control, data, and address pins. This mode can be used for custom interfaces with FPGAs, CPLDs, and for digital data acquisition and actuator control.
PAGE 885
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset Description 30 CLKGATE RW 0 Clock Gated Value Description 0 The EPI clock is free running. 1 The EPI clock is output only when there is data to write or read (current transaction); otherwise the EPI clock is held low. CLKGATE is ignored if CLKPIN is 0 or if the COUNT0 field in the EPIBAUD register is cleared. 29:27 reserved RO 0 Software should not rely on the value of a reserved bit.
PAGE 886
External Peripheral Interface (EPI) Bit/Field Name Type Reset 18:6 reserved RO 0 5:4 ASIZE RW 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Address Bus Size This field defines the size of the address bus.
PAGE 887
Tiva™ TM4C129ENCPDT Microcontroller Register 8: EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2), offset 0x014 Important: The MODE field in the EPICFG register determines which configuration register is accessed for offsets 0x010 and 0x014. To access EPIHB8CFG2, the MODE field of the EPICFG register must be 0x2. This register is used to configure operation while in Host-Bus 8 mode. Note that this register is reset when the MODE field in the EPICFG register is changed.
PAGE 888
External Peripheral Interface (EPI) Bit/Field Name Type Reset 27 CSCFGEXT RW 0 Description Chip Select Extended Configuration This field is used in conjunction with CSCFG, to extend the chip select options, and ALE format. The values 0x0 through 0x3 are from the CSCFG field. The CSCFGEXT bit extends the values to 0x7. Value Description 0 CSCFG bit field is used in chip select configuration. 1 The CSCFG bit field is extended with CSCFGEXT representing the MSB.
PAGE 889
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 26 CSBAUD RW 0 Description Chip Select Baud Rate and Multiple Sub-Mode Configuration enable This bit is only valid when the CSCFGEXT + CSCFG field is programmed to 0x2 or 0x3, 0x5 or 0x6. This bit configures the baud rate settings for CS0n, CS1n, CS2n, and CS3n. This bit must also be set to allow different sub-mode configurations on chip-selects.
PAGE 890
External Peripheral Interface (EPI) Bit/Field Name Type Reset 25:24 CSCFG RW 0x0 Description Chip Select Configuration This field controls the chip select options, including an ALE format, a single chip select, two chip selects, and an ALE combined with two chip selects. These bits are also used in combination with the CSCFGEXT bit for further configurations, including quad- chip select. Value Description 0x0 ALE Configuration EPI0S30 is used as an address latch (ALE).
PAGE 891
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 20 RDHIGH RW 0 Description CS1n READ Strobe Polarity This field is used if the CSBAUD bit in the EPIHB8CFG2 register is enabled. Value Description 19 ALEHIGH RW 1 0 The READ strobe for CS1n accesses is RDn (active Low). 1 The READ strobe for CS1n accesses is RD (active High). CS1n ALE Strobe Polarity This field is used if the CSBAUD bit in the EPIHB8CFG2 register is enabled.
PAGE 892
External Peripheral Interface (EPI) Bit/Field Name Type Reset 5:4 RDWS RW 0x0 Description CS1n Read Wait States This field adds wait states to the data phase of CS1n accesses (the address phase is not affected). The effect is to delay the rising edge of RDn/Oen (or the falling edge of RD). Each wait state encoding adds 2 EPI clock cycles to the access time. The RDWSM bit in the EPIHB8TIME2 register can decrease the number of states by 1 EPI clock cycle for greater granularity.
PAGE 893
Tiva™ TM4C129ENCPDT Microcontroller Register 9: EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2), offset 0x014 Important: The MODE field in the EPICFG register determines which configuration register is accessed for offsets 0x010 and 0x014. To access EPIHB16CFG2, the MODE field must be 0x3. This register is used to configure operation while in Host-Bus 16 mode. Note that this register is reset when the MODE field in the EPICFG register is changed.
PAGE 894
External Peripheral Interface (EPI) Bit/Field Name Type Reset 27 CSCFGEXT RW 0 Description Chip Select Extended Configuration This field is used in conjunction with CSCFG, to extend the chip select options, and ALE format. The values 0x0 through 0x3 are from the CSCFG field. The CSCFGEXT bit extends the values to 0x7. Value Description 0 CSCFG bit field is used in chip select configuration. 1 The CSCFG bit field is extended with CSCFGEXT representing the MSB.
PAGE 895
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 26 CSBAUD RW 0 Description Chip Select Baud Rate and Multiple Sub-Mode Configuration enable This bit is only valid when the CSCFGEXT + CSCFG field is programmed to 0x2 or 0x3, 0x5 or 0x6. This bit configures the baud rate settings for CS0n, CS1n, CS2n, and CS3n. This bit must also be set to allow different sub-mode configurations on chip-selects.
PAGE 896
External Peripheral Interface (EPI) Bit/Field Name Type Reset 25:24 CSCFG RW 0x0 Description Chip Select Configuration This field controls the chip select options, including an ALE format, a single chip select, two chip selects, and an ALE combined with two chip selects. These bits are also used in combination with the CSCFGEXT bit for further configurations, including quad- chip select. Value Description 0x0 ALE Configuration EPI0S30 is used as an address latch (ALE).
PAGE 897
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 19 ALEHIGH RW 1 Description CS1n ALE Strobe Polarity This field is used if CSBAUD bit of the EPIHB16CFG2 register is enabled. Value Description 18 WRCRE RW 0 0 The address latch strobe for CS1n accesses is ALEn (active Low). 1 The address latch strobe for CS1n accesses is ALE (active High). CS1n PSRAM Configuration Register Write Used for the PSRAM configuration registers (CR).
PAGE 898
External Peripheral Interface (EPI) Bit/Field Name Type Reset 7:6 WRWS RW 0x0 Description CS1n Write Wait States This field adds wait states to the data phase of CS1n accesses (the address phase is not affected). The effect is to delay the rising edge of WRn (or the falling edge of WR). Each wait state encoding adds 2 EPI clock cycles to the access time. The WRWSM bit in the EPIHB16TIME2 register can decrease the number of wait states by 1 EPI clock cycle for greater granularity.
PAGE 899
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1:0 MODE RW 0x0 Description CS1n Host Bus Sub-Mode This field determines which Host Bus 16 sub-mode to use for CS1n. Sub-mode use is determined by the connected external peripheral. See Table 11-9 on page 841 for information on how this bit field affects the operation of the EPI signals. When used with multiple chip select option this configuration is for CS1n. Note: The CSBAUD bit must be set to enable this CS1n MODE field.
PAGE 900
External Peripheral Interface (EPI) Register 10: EPI Address Map (EPIADDRMAP), offset 0x01C This register enables address mapping. The EPI controller can directly address memory and peripherals. In addition, the EPI controller supports address mapping to allow indirect accesses in the External RAM and External Peripheral areas. If the external device is a peripheral, including a FIFO or a directly addressable device, the EPSZ and EPADR bit fields should be configured for the address space.
PAGE 901
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11:10 ECSZ RW 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. External Code Size This field selects the size of the external code. If the size of the external code is larger, a bus fault occurs.
PAGE 902
External Peripheral Interface (EPI) Bit/Field Name Type Reset 5:4 EPADR RW 0x0 Description External Peripheral Address This field selects address mapping for the external peripheral area. Value Description 3:2 ERSZ RW 0x0 0x0 Not mapped 0x1 At 0xA000.0000 0x2 At 0xC000.0000 0x3 Only to be used with Host Bus quad chip select. In quad chip select mode, CS2n maps to 0xA000.0000 and CS3n maps to 0xC000.0000. External RAM Size This field selects the size of mapped RAM.
PAGE 903
Tiva™ TM4C129ENCPDT Microcontroller Register 11: EPI Read Size 0 (EPIRSIZE0), offset 0x020 Register 12: EPI Read Size 1 (EPIRSIZE1), offset 0x030 This register selects the size of transactions when performing non-blocking reads with the EPIRPSTDn registers. This size affects how the external address is incremented. The SIZE field must match the external data width as configured in the EPIHBnCFG or EPIGPCFG register. SDRAM mode uses a 16-bit data interface.
PAGE 904
External Peripheral Interface (EPI) Register 13: EPI Read Address 0 (EPIRADDR0), offset 0x024 Register 14: EPI Read Address 1 (EPIRADDR1), offset 0x034 This register holds the current address value. When performing non-blocking reads via the EPIRPSTDn registers, this register's value forms the address (when used by the mode). That is, when an EPIRPSTDn register is written with a non-0 value, this register is used as the first address.
PAGE 905
Tiva™ TM4C129ENCPDT Microcontroller Register 15: EPI Non-Blocking Read Data 0 (EPIRPSTD0), offset 0x028 Register 16: EPI Non-Blocking Read Data 1 (EPIRPSTD1), offset 0x038 This register sets up a non-blocking read via the external interface. A non-blocking read is started by writing to this register with the count (other than 0). Clearing this register terminates an active non-blocking read as well as cancelling any that are pending.
PAGE 906
External Peripheral Interface (EPI) Bit/Field Name Type Reset Description 12:0 POSTCNT RW 0x000 Post Count A write of a non-zero value starts a read operation for that count. Note that it is the software's responsibility to handle address wrap-around. Reading this register provides the current count. A write of 0 cancels a non-blocking read (whether active now or pending). Prior to writing a non-zero value, this register must first be cleared.
PAGE 907
Tiva™ TM4C129ENCPDT Microcontroller Register 17: EPI Status (EPISTAT), offset 0x060 This register indicates which non-blocking read register is currently active; it also indicates whether the external interface is busy performing a write or non-blocking read (it cannot be performing a blocking read, as the bus would be blocked and as a result, this register could not be accessed).
PAGE 908
External Peripheral Interface (EPI) Bit/Field Name Type Reset 6 INITSEQ RO 0 Description Initialization Sequence Value Description 0 The SDRAM interface is not in the wakeup period. 1 The SDRAM interface is running through the wakeup period (greater than 100 μs). If an attempt is made to read or write the SDRAM during this period, the access is held off until the wakeup period is complete.
PAGE 909
Tiva™ TM4C129ENCPDT Microcontroller Register 18: EPI Read FIFO Count (EPIRFIFOCNT), offset 0x06C This register returns the number of values in the NBRFIFO (the data in the NBRFIFO can be read via the EPIREADFIFO register). A race is possible, but that only means that more values may come in after this register has been read. EPI Read FIFO Count (EPIRFIFOCNT) Base 0x400D.
PAGE 910
External Peripheral Interface (EPI) Register 19: EPI Read FIFO (EPIREADFIFO0), offset 0x070 Register 20: EPI Read FIFO Alias 1 (EPIREADFIFO1), offset 0x074 Register 21: EPI Read FIFO Alias 2 (EPIREADFIFO2), offset 0x078 Register 22: EPI Read FIFO Alias 3 (EPIREADFIFO3), offset 0x07C Register 23: EPI Read FIFO Alias 4 (EPIREADFIFO4), offset 0x080 Register 24: EPI Read FIFO Alias 5 (EPIREADFIFO5), offset 0x084 Register 25: EPI Read FIFO Alias 6 (EPIREADFIFO6), offset 0x088 Register 26: EPI Read FIFO Alias 7
PAGE 911
Tiva™ TM4C129ENCPDT Microcontroller Register 27: EPI FIFO Level Selects (EPIFIFOLVL), offset 0x200 This register allows selection of the FIFO levels which trigger an interrupt to the interrupt controller or, more efficiently, a DMA request to the μDMA. The NBRFIFO select triggers on fullness such that it triggers on match or above (more full) in order for the processor or the μDMA to extract the read data.
PAGE 912
External Peripheral Interface (EPI) Bit/Field Name Type Reset 16 RSERR RW 0 Description Read Stall Error Value Description 0 The Read Stalled error interrupt is disabled. Reads behave as normal and are stalled until any preceding writes have completed and the read has returned a result. 1 This bit enables the Read Stalled error interrupt (RSTALL in the EPIEISC register) to be generated when a read is attempted and the WFIFO is not empty.
PAGE 913
Tiva™ TM4C129ENCPDT Microcontroller Register 28: EPI Write FIFO Count (EPIWFIFOCNT), offset 0x204 This register contains the number of slots currently available in the WFIFO. This register may be used for polled writes to avoid stalling and for blocking reads to avoid excess stalling (due to undrained writes).
PAGE 914
External Peripheral Interface (EPI) Register 29: EPI DMA Transmit Count (EPIDMATXCNT), offset 0x208 This register is used to program the total number of transfers (byte, halfword or word) by the µDMA to WRFIFO. As each transfer is processed by the EPI, the TXCNT bit field value is decreased by 1. When TXCNT = 0, the EPI's uDMA request signal is deasserted. EPI DMA Transmit Count (EPIDMATXCNT) Base 0x400D.0000 Offset 0x208 Type RW, reset 0x0000.
PAGE 915
Tiva™ TM4C129ENCPDT Microcontroller Register 30: EPI Interrupt Mask (EPIIM), offset 0x210 This register is the interrupt mask set or clear register. For each interrupt source (read, write, and error), a mask value of 1 allows the interrupt source to trigger an interrupt to the interrupt controller; a mask value of 0 prevents the interrupt source from triggering an interrupt. EPI Interrupt Mask (EPIIM) Base 0x400D.0000 Offset 0x210 Type RW, reset 0x0000.
PAGE 916
External Peripheral Interface (EPI) Bit/Field Name Type Reset 1 RDIM RW 0 Description Read FIFO Full Interrupt Mask Value Description 0 ERRIM RW 0 0 RDRIS in the EPIRIS register is masked and does not cause an interrupt. 1 RDRIS in the EPIRIS register is not masked and can trigger an interrupt to the interrupt controller. Error Interrupt Mask Value Description 0 ERRIS in the EPIRIS register is masked and does not cause an interrupt.
PAGE 917
Tiva™ TM4C129ENCPDT Microcontroller Register 31: EPI Raw Interrupt Status (EPIRIS), offset 0x214 This register is the raw interrupt status register. On a read, it gives the current state of each interrupt source. A write has no effect. Note that raw status for read and write is set or cleared based on FIFO fullness as controlled by EPIFIFOLVL. Raw status for error is held until the error is cleared by writing to the EPIEISC register. EPI Raw Interrupt Status (EPIRIS) Base 0x400D.
PAGE 918
External Peripheral Interface (EPI) Bit/Field Name Type Reset 2 WRRIS RO 1 Description Write Raw Interrupt Status Value Description 0 The number of available entries in the WFIFO is above the range specified by the WRFIFO field in the EPIFIFOLVL register. 1 The number of available entries in the WFIFO is within the trigger range specified by the WRFIFO field in the EPIFIFOLVL register. This bit is cleared when the level in the WFIFO is above the trigger point programmed by the WRFIFO field.
PAGE 919
Tiva™ TM4C129ENCPDT Microcontroller Register 32: EPI Masked Interrupt Status (EPIMIS), offset 0x218 This register is the masked interrupt status register. On read, it gives the current state of each interrupt source (read, write, and error) after being masked via the EPIIM register. A write has no effect. The values returned are the ANDing of the EPIIM and EPIRIS registers. If a bit is set in this register, the interrupt is sent to the interrupt controller. EPI Masked Interrupt Status (EPIMIS) Base 0x400D.
PAGE 920
External Peripheral Interface (EPI) Bit/Field Name Type Reset 2 WRMIS RO 0 Description Write Masked Interrupt Status Value Description 1 RDMIS RO 0 0 The number of available entries in the WFIFO is above the range specified by the trigger level or the interrupt is masked.
PAGE 921
Tiva™ TM4C129ENCPDT Microcontroller Register 33: EPI Error and Interrupt Status and Clear (EPIEISC), offset 0x21C This register is used to clear a pending error interrupt. Clearing any defined bit in the EPIEISC has no effect; setting a bit clears the error source and the raw error returns to 0.
PAGE 922
External Peripheral Interface (EPI) Bit/Field Name Type Reset 0 TOUT RW1C 0 Description Timeout Error This bit is the timeout error source. The timeout error occurs when the XFIFO not-ready signals hold a transaction for more than the count in the MAXWAIT field (when not 0). Value Description 0 No timeout error has occurred. 1 A timeout error has occurred. Writing a 1 to this bit clears it, as well as the ERRRIS and ERIM bits.
PAGE 923
Tiva™ TM4C129ENCPDT Microcontroller Register 34: EPI Host-Bus 8 Configuration 3 (EPIHB8CFG3), offset 0x308 Important: The MODE field in the EPICFG register configures whether EPI Host Bus mode is enabled. For EPIHB8CFG3 to be valid, the MODE field must be 0x2. EPI Host-Bus 8 Configuration 3 (EPIHB8CFG3) Base 0x400D.0000 Offset 0x308 Type RW, reset 0x0008.
PAGE 924
External Peripheral Interface (EPI) Bit/Field Name Type Reset 7:6 WRWS RW 0x0 Description CS2n Write Wait States This field adds wait states to the data phase of CS2n accesses (the address phase is not affected). The effect is to delay the rising edge of WRn (or the falling edge of WR). Each wait state adds 2 EPI clock cycles to the access time. The WRWSM bit in the EPIHB8TIME3 register can decrease the number of wait states by 1 EPI clock cycle for greater granularity.
PAGE 925
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1:0 MODE RW 0x0 Description CS2n Host Bus Sub-Mode This field determines which Host Bus 8 sub-mode to use for CS2n in multiple chip-select mode. Sub-mode use is determined by the connected external peripheral. See Table 11-8 on page 839 for information on how this bit field affects the operation of the EPI signals. Note: The CSBAUD bit must be set to enable this CS2n MODE field.
PAGE 926
External Peripheral Interface (EPI) Register 35: EPI Host-Bus 16 Configuration 3 (EPIHB16CFG3), offset 0x308 Important: The MODE field in the EPICFG register determines which configuration is enabled. For EPIHB16CFG3 to be valid, the MODE field must be 0x3. EPI Host-Bus 16 Configuration 3 (EPIHB16CFG3) Base 0x400D.0000 Offset 0x308 Type RW, reset 0x0008.
PAGE 927
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 18 WRCRE RW 0 Description CS2n PSRAM Configuration Register Write Used for PSRAM configuration registers. With WRCRE set, the next transaction by the EPI is a write of the CR bit field in the EPIHBPSRAM register to the configuration register (CR) of the PSRAM. The WRCRE bit self clears once the write-enabled CRE access is complete. Value Description 17 RDCRE RW 0 0 No Action. 1 Start CRE write transaction for CS2n.
PAGE 928
External Peripheral Interface (EPI) Bit/Field Name Type Reset 7:6 WRWS RW 0x0 Description CS2n Write Wait States This field adds wait states to the data phase of CS2n accesses (the address phase is not affected). The effect is to delay the rising edge of WRn (or the falling edge of WR). Each wait state adds 2 EPI clock cycles to the access time. The WRWSM bit in the EPIHB16TIME3 register can decrease the number of wait states by 1 EPI clock cycle for greater granularity.
PAGE 929
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1:0 MODE RW 0x0 Description CS2n Host Bus Sub-Mode This field determines which Host Bus 16 sub-mode to use for CS2n in multiple chip select mode. Sub-mode use is determined by the connected external peripheral. See Table 11-9 on page 841 for information on how this bit field affects the operation of the EPI signals. Note: The CSBAUD bit must be set to enable this CS2n MODE field.
PAGE 930
External Peripheral Interface (EPI) Register 36: EPI Host-Bus 8 Configuration 4 (EPIHB8CFG4), offset 0x30C Important: The MODE field in the EPICFG register determines which configuration is enabled. For EPIHB8CFG4 to be valid, the MODE field must be 0x2. EPI Host-Bus 8 Configuration 4 (EPIHB8CFG4) Base 0x400D.0000 Offset 0x30C Type RW, reset 0x0008.
PAGE 931
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 7:6 WRWS RW 0x0 Description CS3n Write Wait States This field adds wait states to the data phase of CS3n accesses (the address phase is not affected). The effect is to delay the rising edge of WRn (or the falling edge of WR). Each wait state adds 2 EPI clock cycles to the access time. The WRWSM bit in the EPIHB8TIME4 register can decrease the number of wait states by 1 EPI clock cycle for greater granularity.
PAGE 932
External Peripheral Interface (EPI) Bit/Field Name Type Reset 1:0 MODE RW 0x0 Description CS3n Host Bus Sub-Mode This field determines which Host Bus 8 sub-mode to use for CS3n in multiple chip select mode. Sub-mode use is determined by the connected external peripheral. See Table 11-8 on page 839 for information on how this bit field affects the operation of the EPI signals. Note: The CSBAUD bit must be set to enable this CS3n MODE field.
PAGE 933
Tiva™ TM4C129ENCPDT Microcontroller Register 37: EPI Host-Bus 16 Configuration 4 (EPIHB16CFG4), offset 0x30C Important: The MODE field in the EPICFG register determines which configuration is enabled. For EPIHB16CFG4 to be valid, the MODE field must be 0x3. EPI Host-Bus 16 Configuration 4 (EPIHB16CFG4) Base 0x400D.0000 Offset 0x30C Type RW, reset 0x0008.
PAGE 934
External Peripheral Interface (EPI) Bit/Field Name Type Reset 18 WRCRE RW 0 Description CS3n PSRAM Configuration Register Write Used for PSRAM configuration registers. With WRCRE set, the next transaction by the EPI will be a write of the CR bit field in the EPIHBPSRAM register to the configuration register (CR) of the PSRAM. The WRCRE bit will self clear once the write-enabled CRE access is complete. Value Description 17 RDCRE RW 0 0 No Action. 1 Start CRE write transaction for CS3n.
PAGE 935
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 7:6 WRWS RW 0x0 Description CS3n Write Wait States This field adds wait states to the data phase of CS2n accesses (the address phase is not affected). The effect is to delay the rising edge of WRn (or the falling edge of WR). Each wait state adds 2 EPI clock cycles to the access time. The WRWSM bit in the EPIHB16TIME4 register can decrease the number of wait states by 1 EPI clock cycle for greater granularity.
PAGE 936
External Peripheral Interface (EPI) Bit/Field Name Type Reset 1:0 MODE RW 0x0 Description CS3n Host Bus Sub-Mode This field determines which Host Bus 16 sub-mode to use for CS3n in multiple chip select mode. Sub-mode use is determined by the connected external peripheral. See Table 11-9 on page 841 for information on how this bit field affects the operation of the EPI signals. Note: The CSBAUD bit must be set to enable this CS3n MODE field.
PAGE 937
Tiva™ TM4C129ENCPDT Microcontroller Register 38: EPI Host-Bus 8 Timing Extension (EPIHB8TIME), offset 0x310 Important: The MODE field in the EPICFG register determines which configuration is enabled. For EPIHB8TIME to be valid, the MODE field must be 0x2. EPI Host-Bus 8 Timing Extension (EPIHB8TIME) Base 0x400D.0000 Offset 0x310 Type RW, reset 0x0002.
PAGE 938
External Peripheral Interface (EPI) Bit/Field Name Type Reset 4 WRWSM RW 0 Description Write Wait State Minus One This bit is used with the WRWS field in EPIHB8CFG. This field is not applicable in BURST mode. Value Description 0 No change in the number of wait state clock cycles programmed in the in WRWS field in EPIHB8CFG register. 1 Wait state value is now: WRWS - 1 WRWS field is programmed in EPIHB8CFG.
PAGE 939
Tiva™ TM4C129ENCPDT Microcontroller Register 39: EPI Host-Bus 16 Timing Extension (EPIHB16TIME), offset 0x310 Important: The MODE field in the EPICFG register determines which configuration is enabled. For EPIHB16TIME to be valid, the MODE field must be 0x3. EPI Host-Bus 16 Timing Extension (EPIHB16TIME) Base 0x400D.0000 Offset 0x310 Type RW, reset 0x0002.
PAGE 940
External Peripheral Interface (EPI) Bit/Field Name Type Reset Description 15:14 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13:12 CAPWIDTH RW 0x2 CS0n Inter-transfer Capture Width Controls the delay between Host-Bus transfers. Value Description 11:5 reserved RO 0x0 4 WRWSM RW 0 0x0 Reserved 0x1 1 EPI clock.
PAGE 941
Tiva™ TM4C129ENCPDT Microcontroller Register 40: EPI Host-Bus 8 Timing Extension (EPIHB8TIME2), offset 0x314 Important: The MODE field in the EPICFG register determines which configuration is enabled. For EPIHB8TIME2 to be valid, the MODE field must be 0x2. EPI Host-Bus 8 Timing Extension (EPIHB8TIME2) Base 0x400D.0000 Offset 0x314 Type RW, reset 0x0002.
PAGE 942
External Peripheral Interface (EPI) Bit/Field Name Type Reset 4 WRWSM RW 0 Description CS1n Write Wait State Minus One This bit is used with the WRWS field in EPIHB8CFG2. This field is not applicable in BURST mode. Value Description 0 No change in the number of wait state clock cycles programmed in the in WRWS field in EPIHB8CFG2 register. 1 Wait state value is now: WRWS - 1 WRWS field is programmed in EPIHB8CFG2.
PAGE 943
Tiva™ TM4C129ENCPDT Microcontroller Register 41: EPI Host-Bus 16 Timing Extension (EPIHB16TIME2), offset 0x314 Important: The MODE field in the EPICFG register determines which configuration is enabled. For EPIHB16TIME2 to be valid, the MODE field must be 0x3. EPI Host-Bus 16 Timing Extension (EPIHB16TIME2) Base 0x400D.0000 Offset 0x314 Type RW, reset 0x0002.
PAGE 944
External Peripheral Interface (EPI) Bit/Field Name Type Reset Description 15:14 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13:12 CAPWIDTH RW 0x2 CS1n Inter-transfer Capture Width Controls the delay between Host-Bus transfers. Value Description 11:5 reserved RO 0x00 4 WRWSM RW 0 0x0 Reserved 0x1 1 EPI clock.
PAGE 945
Tiva™ TM4C129ENCPDT Microcontroller Register 42: EPI Host-Bus 8 Timing Extension (EPIHB8TIME3), offset 0x318 Important: The MODE field in the EPICFG register determines which configuration is enabled. For EPIHB8TIME3 to be valid, the MODE field must be 0x2. EPI Host-Bus 8 Timing Extension (EPIHB8TIME3) Base 0x400D.0000 Offset 0x318 Type RW, reset 0x0002.
PAGE 946
External Peripheral Interface (EPI) Bit/Field Name Type Reset 4 WRWSM RW 0 Description CS2n Write Wait State Minus One This bit is used with the WRWS field in EPIHB8CFG3. This field is not applicable in BURST mode. Value Description 0 No change in the number of wait state clock cycles programmed in the in WRWS field in EPIHB8CFG3 register. 1 Wait state value is now: WRWS - 1 WRWS field is programmed in EPIHB8CFG3.
PAGE 947
Tiva™ TM4C129ENCPDT Microcontroller Register 43: EPI Host-Bus 16 Timing Extension (EPIHB16TIME3), offset 0x318 Important: The MODE field in the EPICFG register determines which configuration is enabled. For EPIHB16TIME3 to be valid, the MODE field must be 0x3. EPI Host-Bus 16 Timing Extension (EPIHB16TIME3) Base 0x400D.0000 Offset 0x318 Type RW, reset 0x0002.
PAGE 948
External Peripheral Interface (EPI) Bit/Field Name Type Reset Description 15:14 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13:12 CAPWIDTH RW 0x2 CS2n Inter-transfer Capture Width Controls the delay between Host-Bus transfers. Value Description 11:5 reserved RO 0x00 4 WRWSM RW 0 0x0 Reserved 0x1 1 EPI clock.
PAGE 949
Tiva™ TM4C129ENCPDT Microcontroller Register 44: EPI Host-Bus 8 Timing Extension (EPIHB8TIME4), offset 0x31C Important: The MODE field in the EPICFG register determines which configuration is enabled. For EPIHB8TIME4 to be valid, the MODE field must be 0x2. EPI Host-Bus 8 Timing Extension (EPIHB8TIME4) Base 0x400D.0000 Offset 0x31C Type RW, reset 0x0002.
PAGE 950
External Peripheral Interface (EPI) Bit/Field Name Type Reset Description 11:5 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 WRWSM RW 0 CS3n Write Wait State Minus One This bit is used with the WRWS field in EPIHB8CFG4. This field is not applicable in BURST mode.
PAGE 951
Tiva™ TM4C129ENCPDT Microcontroller Register 45: EPI Host-Bus 16 Timing Extension (EPIHB16TIME4), offset 0x31C Important: The MODE field in the EPICFG register determines which configuration is enabled. For EPIHB16TIME4 to be valid, the MODE field must be 0x3. EPI Host-Bus 16 Timing Extension (EPIHB16TIME4) Base 0x400D.0000 Offset 0x31C Type RW, reset 0x0002.
PAGE 952
External Peripheral Interface (EPI) Bit/Field Name Type Reset Description 15:14 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13:12 CAPWIDTH RW 0x2 CS3n Inter-transfer Capture Width Controls the delay between Host-Bus transfers. Value Description 11:5 reserved RO 0x00 4 WRWSM RW 0 0x0 Reserved 0x1 1 EPI clock.
PAGE 953
Tiva™ TM4C129ENCPDT Microcontroller Register 46: EPI Host-Bus PSRAM (EPIHBPSRAM), offset 0x360 This register holds the PSRAM configuration register value. When the WRCRE bit in the EPIHB16CFGn register is set, all 21 bits of the EPIHBPSRAM register's CR value are written to the PSRAM's configuration register. When the RDCRE bit is set in the EPIHB16CFGn register, a read of the PSRAM's configuration register takes place and the value is written to bits[15:0] of the EPIHBPSRAM.
PAGE 954
Cyclical Redundancy Check (CRC) 12 Cyclical Redundancy Check (CRC) The Cyclical Redundancy Check (CRC) computation module can be used for message transfer and safety system checks, as well as in conjunction with the AES and DES modules. The following features are supported: ■ Support four major CRC forms: – CRC16-CCITT as used by CCITT/ITU X.25 – CRC16-IBM as used by USB and ANSI – CRC32-IEEE as used by IEEE802.3 and MPEG2 – CRC32C as used by G.
PAGE 955
Tiva™ TM4C129ENCPDT Microcontroller ■ A unique context value written to the CRCSEED register (INIT=0x0) ■ All 0s (INIT=0x2) ■ All 1s (INIT=0x3) Once the operation is done, software should read the result from the CRC Post Processing Result (CRCRSLTPP) register, offset 0x418, and a software channel μDMA interrupt should be used to identify completion. 12.1.1.2 Data Size The CRC module supports data being fed 32-bit words and 8 bits at a time and can dynamically switch back and forth.
PAGE 956
Cyclical Redundancy Check (CRC) Table 12-2. Endian Configuration with Bit Reversal (continued) ENDIAN Encoding 0x1 Initial Endian Configuration Bytes are swapped in half-words but half-words are not swapped Configuration with Bit Reversal (BR = 1) B2[16:23],B3[24:31],B0[0:7],B1[8:15] {B2[23:16], B3[31:24], B0[7:0], B1[15:8]} 0x2 Half-words are swapped but bytes are not swapped in half-word.
PAGE 957
Tiva™ TM4C129ENCPDT Microcontroller 2. {00, 00, 00, D1} 3. {00, 00, 00, D2} 4. {00, 00, 00, D3} 5. {00, 00, 00, D4} 6. {00, 00, 00, D5} 7. {00, 00, 00, D6} 8. ...... 9. ..... ■ If operating in word mode, the CRCDIN register should be written in the following order: 1. {D3, D2, D1, D0} 2. {D7, D6, D5, D4} 3. {D11, D10, D9, D8} 4. ...... 5. ...... 12.3 Register Map Table 12-3 on page 957 lists the CRC Module registers.
PAGE 958
Cyclical Redundancy Check (CRC) Register 1: CRC Control (CRCCTRL), offset 0x400 The CRC Control (CRCCTRL) register is used to configure control of the CRC. CRC Control (CRCCTRL) Base 0x4403.0000 Offset 0x400 Type RW, reset 0x0000.
PAGE 959
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 8 OBR RW 0 Description Output Reverse Enable Refer to Table 12-2 on page 955 for more information regarding bit reversal. Value Description 7 BR RW 0 0 No change to result. 1 Bit reverse the output result byte before storing to CRCRSLTPP register. The reversal is applied to all bytes in a word. Bit reverse enable Refer to Table 12-2 on page 955 for more information regarding bit reversal.
PAGE 960
Cyclical Redundancy Check (CRC) Register 2: CRC SEED/Context (CRCSEED), offset 0x410 The CRC SEED/Context (CRCSEED) register is initially written with one of the following three values depending on the encoding of the INIT field in the CRCCTRL register: ■ The context value written to the CRCSEED register. This encoding is for SEED values from a previous CRC calculation or a specific protocol. (INIT=0x0) ■ 0x0000.0000 (INIT=0x2) ■ 0x1111.1111 (INIT=0x3) CRC SEED/Context (CRCSEED) Base 0x4403.
PAGE 961
Tiva™ TM4C129ENCPDT Microcontroller Register 3: CRC Data Input (CRCDIN), offset 0x414 The application or µDMA writes the CRC Data Input (CRCDIN) register with the next byte or word to compute. CRC Data Input (CRCDIN) Base 0x4403.0000 Offset 0x414 Type RW, reset 0x0000.
PAGE 962
Cyclical Redundancy Check (CRC) Register 4: CRC Post Processing Result (CRCRSLTPP), offset 0x418 This register contains the post-processed CRC result as configured by the CRCCTRL register. CRC Post Processing Result (CRCRSLTPP) Base 0x4403.0000 Offset 0x418 Type RO, reset 0x0000.
PAGE 963
Tiva™ TM4C129ENCPDT Microcontroller 13 Advance Encryption Standard Accelerator (AES) This section describes the Advanced Encryption Standard (AES) cryptographic hardware-accelerated module. 13.1 AES Overview This section introduces the AES and describes the AES main functions and connections in the device. The advanced encryption standard (AES) security modules provide hardware-accelerated data encryption and decryption operations based on a binary key.
PAGE 964
Advance Encryption Standard Accelerator (AES) 13.2.1 AES Block Diagram Figure 13-1 on page 964 shows the AES block diagram. A single-core/dual-interface architecture is used. Figure 13-1.
PAGE 965
Tiva™ TM4C129ENCPDT Microcontroller ■ Feedback modes: The logic that implements the various feedback modes supported by AES.
PAGE 966
Advance Encryption Standard Accelerator (AES) AES Key Scheduler The AES key scheduler generates the round keys. During each round, a new subkey is generated from the input key to be XORed with the data. Round keys are generated on-the-fly and parallel to data processing to minimize register requirements. For encryption operations, the key sequencer transfers the initial key data to the AES core.
PAGE 967
Tiva™ TM4C129ENCPDT Microcontroller 13.2.2 AES Algorithm The AES algorithm generates block ciphers. The AES block size is 16 bytes. The AES key(s) can be coded on 128, 192, or 256 bits. The larger key sizes provide a higher level of security, but at the cost of a moderate decrease in throughput. For the AES algorithm: ■ The length of the input and output blocks is 128 bits, which is represented by Nb = 4, which reflects the number of 32-bit words.
PAGE 968
Advance Encryption Standard Accelerator (AES) 13.2.3 AES Operating Modes 13.2.3.1 Supported Modes of Operation ECB Feedback Mode Figure 13-2 on page 968 shows the basic ECB feedback mode of operation, where the input data is passed directly to the basic cryptographic core and the output is passed directly to the output buffer. For decryption, the cryptographic core operates in reverse: the decryption data path is used for data processing, whereas encryption uses the encryption data path. Figure 13-2.
PAGE 969
Tiva™ TM4C129ENCPDT Microcontroller Figure 13-3.
PAGE 970
Advance Encryption Standard Accelerator (AES) Note: The value for n can be 1, 2, 3, or 4 for CTR mode and is ½ for ICM mode. CFB Mode Figure 13-5 on page 970 shows the full block (128 bits) CFB mode of operation for encryption and decryption. The input for the cryptographic core is the IV; the result is XORed with the data. The result is fed back through the IV register as the next input for the cryptographic core.
PAGE 971
Tiva™ TM4C129ENCPDT Microcontroller Figure 13-6. AES - F8 Mode 1 63 IV register + 63 0 Zeroes 0 Counter 64 64 64 128 data_in Key in Input buffer (plain/cipher text) AES core (encrypt) Key register 256 128 128 AES data out buffer data_out 128 128 Temporary register Output buffer (cipher/plain text) Encryption/Decryption XTS Operation Figure 13-7 on page 971 shows the XTS mode of operation for encryption and decryption.
PAGE 972
Advance Encryption Standard Accelerator (AES) Note: The IV is created with an initial encryption, followed by an LFSR operation for each new block. F9 Operation Figure 13-8 on page 972 shows the F9 authentication mode of operation, where the input to the cryptographic core is XORed with the IV, and the output is XORed with the previous result to create the next result. The cryptographic core output is fed back as IV for the next block.
PAGE 973
Tiva™ TM4C129ENCPDT Microcontroller Figure 13-9. AES - CBC-MAC Authentication Mode Input buffer (plain text) 128 IV register 128 128 Key in Key register 256 128 128 Temporary buffer data_in AES core (encrypt) data_out 128 Authentication result (TAG) GCM Operation Figure 13-10 on page 974 shows one round of a GCM operation for encryption and decryption. A 32-bit counter is used as IV (as it is for CTR mode).
PAGE 974
Advance Encryption Standard Accelerator (AES) Figure 13-10.
PAGE 975
Tiva™ TM4C129ENCPDT Microcontroller Figure 13-11.
PAGE 976
Advance Encryption Standard Accelerator (AES) decryption). The final authentication result must be encrypted using the output of the encryption of the IV block A0. This block contains the IV (consisting of flags and nonce) concatenated with the counter, which is zero for A0. 13.2.4 AES Software Reset To perform a software reset of the AES module, write a 1 to the SOFTRESET bit in the AES System Configuration (AES_SYSCONFIG) register.
PAGE 977
Tiva™ TM4C129ENCPDT Microcontroller 13.3 AES Performance Information Table 13-3 on page 977 lists the performance for all supported key sizes and modes of operations. It assumes that the engine is kept fully utilized (that is, the host is supplying input blocks and retrieving output blocks in such a way that the engine never has to wait for input), and that the previous output has been retrieved before the next output is ready. Table 13-3.
PAGE 978
Advance Encryption Standard Accelerator (AES) Table 13-3. AES Module Performance (Input/Output Block Size = 128) (continued) Key Size Mode of Operation Cycles per a Block Throughput (bits/cycle) 44 2.91 45 2.84 90 1.42 45 2.84 ECB-encrypt / decrypt CBC-decrypt CTR/ICM-encrypt / decrypt CFB128-decrypt CBC-encrypt OFB-encrypt / decrypt 256 f8-encrypt / decrypt CFB128-encrypt XTS-encrypt / decrypt GCM-outbound inbound CCM-encrypt / decrypt b CBC-MAC b f9 a. Standard Block Size (128 bits) b.
PAGE 979
Tiva™ TM4C129ENCPDT Microcontroller Table 13-4. AES Module Packet Mode Switch Overhead (continued) New Context Cycles needed for first block/and to finish the last block inbound CCM, AES key size is 256 45 / 45 b Total 90 a. Numbers for regular GCM mode (H is precalculated and Y0-encrypted need to be calculated internally using the new IV). If H needs to be calculated by the core (complete GCM mode), this number needs to be doubled.
PAGE 980
Advance Encryption Standard Accelerator (AES) 13.4.1.2 Initialization Subsequence The following sections list the initialization subsequences for the available encryption/decryption modes: Subsequence: Initialize CCM AES Core Mode The CCM mode initialization is as follows: 1. Define the width of the length field and the length of the authentication field by programming the CCM_L and CCM_M bit fields in the AES_CTRL register at offset 0x050. 2.
PAGE 981
Tiva™ TM4C129ENCPDT Microcontroller 1. Enable F8 Mode by setting the F8 bit in the AES_CTRL register. 2. Select the counter width by programming the CTR_WIDTH field in the AES_CTRL register. 3. Set the key size to 128 bits by setting the KEY_SIZE field to 0x1 in the AES_CTRL register. 4. Load the AES Initialization Vector Input n (AES_IV_IN_n) registers at offset 0x040 to 0x04C. Subsequence: Initialize XTS AES Core Mode The steps for XTS mode configuration are as follows: 1.
PAGE 982
Advance Encryption Standard Accelerator (AES) 13.4.1.3 Operational Modes Configuration AES Polling Mode Main Sequence: AES Polling Mode Figure 13-12 on page 982 shows AES polling mode. The registers used in AES polling mode are: ■ AES Data RW Plaintext/Ciphertext 0 (AES_DATA_IN_0) registers, offset 0x060 to 0x06C ■ AES Control (AES_CTRL) register, offset 0x050 ■ AES Hash Tag Out 0 (AES_TAG_OUT_0), offset 0x070 Figure 13-12.
PAGE 983
Tiva™ TM4C129ENCPDT Microcontroller 1. Once the device has been initialized, following the initialization sequences described in “Global Initialization” on page 979 and “Initialization Subsequence” on page 980, the application can enable the AES module interrupts through the AES Interrupt Enable (AES_IRQENABLE) register, offset 0x090. If all four interrupts must be enabled, the application can write 0x0000.000F to the AES_IRQENABLE register. 2. Load the input buffers, AES_DATA_IN_n, with data.
PAGE 984
Advance Encryption Standard Accelerator (AES) Figure 13-13.
PAGE 985
Tiva™ TM4C129ENCPDT Microcontroller Table 13-5. AES Register Map (continued) Type Reset Description See page AES_KEY2_5 RW 0x0000.0000 AES Key 2_5 987 0x010 AES_KEY2_2 RW 0x0000.0000 AES Key 2_2 987 0x014 AES_KEY2_3 RW 0x0000.0000 AES Key 2_3 987 0x018 AES_KEY2_0 RW 0x0000.0000 AES Key 2_0 987 0x01C AES_KEY2_1 RW 0x0000.0000 AES Key 2_1 987 0x020 AES_KEY1_6 RW 0x0000.0000 AES Key 1_6 987 0x024 AES_KEY1_7 RW 0x0000.
PAGE 986
Advance Encryption Standard Accelerator (AES) Table 13-5. AES Register Map (continued) Offset Name 0x08C Description See page 0x0000.0000 AES Interrupt Status 1004 RW 0x0000.0000 AES Interrupt Enable 1006 RW1C 0x0000.0000 AES Dirty Bits 1008 Type Reset AES_IRQSTATUS RO 0x090 AES_IRQENABLE 0x094 AES_DIRTYBITS AES µDMA Interrupt Registers (CRC and Cryptographic Modules (CCM) Offset) 0x020 AES_DMAIM RW 0x0000.0000 AES DMA Interrupt Mask 1009 0x024 AES_DMARIS RO 0x0000.
PAGE 987
Tiva™ TM4C129ENCPDT Microcontroller Register 1: AES Key 2_6 (AES_KEY2_6), offset 0x000 Register 2: AES Key 2_7 (AES_KEY2_7), offset 0x004 Register 3: AES Key 2_4 (AES_KEY2_4), offset 0x008 Register 4: AES Key 2_5 (AES_KEY2_5), offset 0x00C Register 5: AES Key 2_2 (AES_KEY2_2), offset 0x010 Register 6: AES Key 2_3 (AES_KEY2_3), offset 0x014 Register 7: AES Key 2_0 (AES_KEY2_0), offset 0x018 Register 8: AES Key 2_1 (AES_KEY2_1), offset 0x01C Register 9: AES Key 1_6 (AES_KEY1_6), offset 0x020 Register 10: AES
PAGE 988
Advance Encryption Standard Accelerator (AES) Table 13-6. AES Key Register Descriptions (continued) Register Name Address Offset Description AES_KEY1_2 0x030 Secure Key AES_KEY1_3 0x034 Secure Key (MSW for 128-bit key) AES_KEY1_0 0x038 Secure Key (LSW for 128-bit key) AES_KEY1_1 0x03C Secure Key AES Key (AES_KEYn_n) Base 0x4403.6000 Offset 0x000 Type RW, reset 0x0000.
PAGE 989
Tiva™ TM4C129ENCPDT Microcontroller Register 17: AES Initialization Vector Input 0 (AES_IV_IN_0), offset 0x040 Register 18: AES Initialization Vector Input 1 (AES_IV_IN_1), offset 0x044 Register 19: AES Initialization Vector Input 2 (AES_IV_IN_2), offset 0x048 Register 20: AES Initialization Vector Input 3 (AES_IV_IN_3), offset 0x04C This register contains the initialization vector input. AES Initialization Vector Input (AES_IV_IN_n) Base 0x4403.6000 Offset 0x040 Type RW, reset 0x0000.
PAGE 990
Advance Encryption Standard Accelerator (AES) Register 21: AES Control (AES_CTRL), offset 0x050 This register determines the mode of operation of the AES Engine.
PAGE 991
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset Description 28:25 reserved R 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 24:22 CCM_M RW 0 Counter with CBC-MAC (CCM) Defines M which indicates the length of the authentication field for CCM operations; the authentication field length equals two times the sum of CCM-M plus one.
PAGE 992
Advance Encryption Standard Accelerator (AES) Bit/Field Name Type Reset 15 CBCMAC RW 0 Description AES-CBC MAC Enable The DIRECTION bit must be set to 1 for this mode. Value Description 14 F9 RW 0 0 AES-CBC MAC mode is not enabled. 1 AES-CBC MAC mode enabled. AES f9 Mode Enable The AES key size must be set to 128-bit for this mode. Value Description 13 F8 RW 0 0 f9 mode is not enabled 1 f9 mode is enabled. AES f8 Mode Enable The KEY_SIZE must be set to 128-bit for this mode.
PAGE 993
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 8:7 CTR_WIDTH RW 0 Description AES-CTR Mode Counter Width Value Description 6 CTR RW 0 0x0 Counter is 32 bits 0x1 Counter is 64 bits 0x2 Counter is 96 bits 0x3 Counter is 128 bits Counter Mode This bit must also be set for GCM and CCM mode, when encryption/decryption is required. Value Description 5 MODE RW 0 0 Counter mode is not enabled. 1 Counter mode is enabled.
PAGE 994
Advance Encryption Standard Accelerator (AES) Bit/Field Name Type Reset 0 OUTPUT_READY RO 0 Description Output Ready Status Value Description 0 No AES output block is available. 1 An AES output block is available for the host to retrieve.
PAGE 995
Tiva™ TM4C129ENCPDT Microcontroller Register 22: AES Crypto Data Length 0 (AES_C_LENGTH_0), offset 0x054 Register 23: AES Crypto Data Length 1 (AES_C_LENGTH_1), offset 0x058 AES Crypto Data Length n (AES_C_LENGTH_n) registers (LSW and MSW) store the cryptographic data length in bytes for all modes. The AES_C_LENGTH_0 register stores the most significant word and the AES_C_LENGTH_1 register stores the least significant word. Once processing with this context is started, this length decrements to zero.
PAGE 996
Advance Encryption Standard Accelerator (AES) Register 24: AES Authentication Data Length (AES_AUTH_LENGTH), offset 0x05C The AES Authentication Data Length (AES_AUTH_LENGTH) register stores the authentication data length in bytes for combined modes only (GCM or CCM). Supported AUTH lengths for CCM are from 0 to (216 - 28) bytes. For GCM any value up to (232 - 1) bytes can be used. Once processing with this context is started, this length decrements to zero.
PAGE 997
Tiva™ TM4C129ENCPDT Microcontroller Register 25: AES Data RW Plaintext/Ciphertext 0 (AES_DATA_IN_0), offset 0x060 Register 26: AES Data RW Plaintext/Ciphertext 1 (AES_DATA_IN_1), offset 0x064 Register 27: AES Data RW Plaintext/Ciphertext 2 (AES_DATA_IN_2), offset 0x068 Register 28: AES Data RW Plaintext/Ciphertext 3 (AES_DATA_IN_3), offset 0x06C The AES Data RW Plaintext/Ciphertext n (AES_DATA_IN_n) registers are used to read and write plaintext/ciphertext.
PAGE 998
Advance Encryption Standard Accelerator (AES) Register 29: AES Hash Tag Out 0 (AES_TAG_OUT_0), offset 0x070 Register 30: AES Hash Tag Out 1 (AES_TAG_OUT_1), offset 0x074 Register 31: AES Hash Tag Out 2 (AES_TAG_OUT_2), offset 0x078 Register 32: AES Hash Tag Out 3 (AES_TAG_OUT_3), offset 0x07C This register displays the Hash result. The AES_TAG_OUT_0 register is the most significant word of the Hash and the AES_TAG_OUT_3 register is the least significant word. AES Hash Tag Out (AES_TAG_OUT_n) Base 0x4403.
PAGE 999
Tiva™ TM4C129ENCPDT Microcontroller Register 33: AES IP Revision Identifier (AES_REVISION), offset 0x080 This register contains the IP revision number of the AES. AES IP Revision Identifier (AES_REVISION) Base 0x4403.
PAGE 1000
Advance Encryption Standard Accelerator (AES) Register 34: AES System Configuration (AES_SYSCONFIG), offset 0x084 This register controls the IDLE and reset logic. Note: After one operation has completed, the AES_SYSCONFIG register must be cleared and re-configured for the next operation to ensure proper DMA and data operation functionality. AES System Configuration (AES_SYSCONFIG) Base 0x4403.6000 Offset 0x084 Type RW, reset 0x0000.
PAGE 1001
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset Description 10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9 MAP_CONTEXT_OUT_ ON_DATA_OUT RW 0 Map Context Out on Data Out Enable Value Description 8 DMA_REQ_CONTEXT_ OUT_EN RW 0 0 Original context out bit values are used.
PAGE 1002
Advance Encryption Standard Accelerator (AES) Bit/Field Name Type Reset Description 4:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 SOFTRESET RW 0 Soft reset Value Description 0 reserved RO 1 0 No operation 1 Start soft reset sequence Software should not rely on the value of a reserved bit.
PAGE 1003
Tiva™ TM4C129ENCPDT Microcontroller Register 35: AES System Status (AES_SYSSTATUS), offset 0x088 This register indicates if reset has completed. AES System Status (AES_SYSSTATUS) Base 0x4403.6000 Offset 0x088 Type RO, reset 0x0000.
PAGE 1004
Advance Encryption Standard Accelerator (AES) Register 36: AES Interrupt Status (AES_IRQSTATUS), offset 0x08C This register indicates the interrupt status. If one of the interrupt bits is set, the interrupt output is asserted. AES Interrupt Status (AES_IRQSTATUS) 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 CONTEXT_OUT Base 0x4403.
PAGE 1005
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 0 CONTEXT_IN RO 0 Description Context In Interrupt Status Value Description 0 The context in interrupt is not active. 1 The context in interrupt is active and the interrupt output has been triggered.
PAGE 1006
Advance Encryption Standard Accelerator (AES) Register 37: AES Interrupt Enable (AES_IRQENABLE), offset 0x090 This register contains an enable bit for each unique interrupt generated by the module. It matches the layout of AES_IRQSTATUS register. An interrupt is enabled when the bit in this register is set to 1. An interrupt that is enabled is propagated to the NVIC controller. All AES software interrupts need to be enabled explicitly by writing this register.
PAGE 1007
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 0 CONTEXT_IN RW 0 Description Context In Interrupt Enable Value Description 0 The context in interrupt is disabled. 1 The context in interrupt is enabled.
PAGE 1008
Advance Encryption Standard Accelerator (AES) Register 38: AES Dirty Bits (AES_DIRTYBITS), offset 0x094 This register can be used to identify if AES registers have been read or written to. AES Dirty Bits (AES_DIRTYBITS) Base 0x4403.6000 Offset 0x094 Type RW1C, reset 0x0000.
PAGE 1009
Tiva™ TM4C129ENCPDT Microcontroller Register 39: AES DMA Interrupt Mask (AES_DMAIM), offset 0x020 The AES DMA Interrupt Mask (AES_DMAIM) register controls interrupt behavior and is used to program which interrupts are suppressed. AES DMA Interrupt Mask (AES_DMAIM) Base 0x4403.0000 Offset 0x020 Type RW, reset 0x0000.
PAGE 1010
Advance Encryption Standard Accelerator (AES) Bit/Field Name Type Reset 0 CIN RW 0 Description Context In DMA Done Interrupt Mask If this bit is unmasked, an interrupt is generated when the µDMA completes a context write to the internal register. Value Description 0 The CIN interrupt is suppressed and not sent to the interrupt controller. 1 The CIN interrupt is sent to the interrupt controller.
PAGE 1011
Tiva™ TM4C129ENCPDT Microcontroller Register 40: AES DMA Raw Interrupt Status (AES_DMARIS), offset 0x024 The AES DMA Raw Interrupt Status (AES_DMARIS) register contains the raw interrupt status. If any of these bits read 1, the processor is interrupted if the corresponding masked interrupt status bit is set to '1.' AES DMA Raw Interrupt Status (AES_DMARIS) Base 0x4403.0000 Offset 0x024 Type RO, reset 0x0000.
PAGE 1012
Advance Encryption Standard Accelerator (AES) Bit/Field Name Type Reset 0 CIN RW 0 Description Context In DMA Done Raw Interrupt Status Value Description 0 No interrupt. 1 The µDMA has completed a context write to the internal register and an interrupt has been triggered and is pending.
PAGE 1013
Tiva™ TM4C129ENCPDT Microcontroller Register 41: AES DMA Masked Interrupt Status (AES_DMAMIS), offset 0x028 The AES DMA Masked Interrupt Status (AES_DMAMIS) register displays the raw interrupts that are unmasked in the AES DMA Raw Interrupt Status (AES_DMARIS) register. AES DMA Masked Interrupt Status (AES_DMAMIS) Base 0x4403.0000 Offset 0x028 Type RO, reset 0x0000.
PAGE 1014
Advance Encryption Standard Accelerator (AES) Register 42: AES DMA Interrupt Clear (AES_DMAIC), offset 0x02C The AES DMA Interrupt Clear (AES_DMAIC) register is used to clear the AES_DMARIS and AES_DMAMIS registers by writing a 1 to each register bit. Note: This registers always reads as zero. AES DMA Interrupt Clear (AES_DMAIC) Base 0x4403.0000 Offset 0x02C Type W1C, reset 0x0000.
PAGE 1015
Tiva™ TM4C129ENCPDT Microcontroller 14 Data Encryption Standard Accelerator (DES) The DES module provides hardware accelerated data encryption and decryption functions. The module runs either the single DES or the triple DES (3DES) algorithm in compliance with the FIPS 46-3 standard and supports electronic codebook (ECB), cipher block chaining (CBC), and cipher feedback (CFB) modes of operation. It does not support the output feedback (OFB) mode of operation in hardware.
PAGE 1016
Data Encryption Standard Accelerator (DES) The first option provides highest level of security; the last option is compatible with single DES. See Table 14-1 on page 1016 for key use. Table 14-1. Key Repartition Mode Key1_L Key1_H Key2_L Key2_H Key3_L Key3_H 64-bit (DES) √ √ X X X X 192-bit (3DES) √ √ √ √ √ √ ECB, CBC, and CFB modes can be used with DES and 3DES modes. 14.2 DES Block Diagram The module architecture consists of primary blocks, as shown in Figure 14-1 on page 1016.
PAGE 1017
Tiva™ TM4C129ENCPDT Microcontroller ■ DMA context in - Request a new context (DES0 Cin) ■ DMA data in - Request input data (DES0 Din) ■ DMA data out - Request output data read (DES0 Dout) 14.2.2 Interrupt Control There is one interrupt for the DES that is sent to the interrupt controller. This interrupt is an OR of the enabled interrupt bits in the DES Interrupt Status (DES_IRQSTATUS) register. These bits are enabled through the DES Interrupt Enable (DES_IRQENABLE) register.
PAGE 1018
Data Encryption Standard Accelerator (DES) of a 3x reduction in throughput. The DES buffered engine implements a 3DES logic wrapper around the 2-round DES core, enabling seamless 3DES encryption. 14.2.4.3 DES Cipher Core The DES cipher core implements the DES algorithm as specified in the FIPS 46-3. The core operates on the input block and performs the required substitution, shift, and mix operations. The core also applies the correct key-scheduling.
PAGE 1019
Tiva™ TM4C129ENCPDT Microcontroller Figure 14-2. DES - ECB Feedback Mode Input buffer (plain text) 64 Key in Key register Input buffer (cipher text) Data_in 64 Key in DES core (encrypt) DES core (decrypt) Key register 192 192 64 Data_out 64 Output buffer (cipher text) Data_out Output buffer (plain text) Encryption 14.4.1.
PAGE 1020
Data Encryption Standard Accelerator (DES) Figure 14-4. DES3DES-CFB Feedback Mode Input buffer (plain text) Input buffer (cipher text) 64 64 IV register 64 IV register data_in Key in DES core (encrypt) Key register 192 64 data_in Key in Key register 128 192 data_out 64 64 64 DES core (encrypt) 64 Temporary register 64 Output buffer (cipher text) 64 data_out Temporary register 64 Output buffer (plain text) Encryption Decryption 14.
PAGE 1021
Tiva™ TM4C129ENCPDT Microcontroller Table 14-4. DES Algorithm Type Configuration 14.5.1.3 Step Register/Bit Field/Programming Model Value Load key 1 LSW. DES_KEY1_L[31:0] KEY1_L - Load key 1 MSW. DES_KEY1_H[31:0] KEY1_H - Select DES algorithm. DES_CTRL[3] TDES 0x0 Subsequence - Configure the 3DES Algorithm Type This subsequence details the 3DES algorithm type settings. Table 14-5. 3DES Algorithm Type Configuration Step Register/Bit Field/Programming Model Value Load key 1 LSW.
PAGE 1022
Data Encryption Standard Accelerator (DES) Figure 14-5.
PAGE 1023
Tiva™ TM4C129ENCPDT Microcontroller Table 14-7. DES DMA Mode (continued) Step Register/Bit Field/Programming Model Value Load the input buffer data HSW register. DES_DATA_H[31:0] DATA_H - 14.5.3 DES Events Servicing 14.5.3.1 Interrupt Servicing This section describes the event servicing of the module. Figure 14-6 on page 1023 shows the DES interrupt service. The registers used during event servicing are: DES_IRQSTATUS, DES_DATA_L, and DES_DATA_H. Figure 14-6.
PAGE 1024
Data Encryption Standard Accelerator (DES) Figure 14-7.
PAGE 1025
Tiva™ TM4C129ENCPDT Microcontroller Table 14-8. DES Register Map (continued) Description See page 0x0000.0000 DES Key 2 MSW for 128-Bit Key 1026 RW 0x0000.0000 DES Key 1 LSW for 64-Bit Key 1026 DES_KEY1_H RW 0x0000.0000 DES Key 1 MSW for 64-Bit Key 1026 0x018 DES_IV_L RW 0x0000.0000 DES Initialization Vector 1027 0x01C DES_IV_H RW 0x0000.0000 DES Initialization Vector 1028 0x020 DES_CTRL RW 0x8000.0000 DES Control 1029 0x024 DES_LENGTH RW 0x0000.
PAGE 1026
Data Encryption Standard Accelerator (DES) Register 1: DES Key 3 LSW for 192-Bit Key (DES_KEY3_L), offset 0x000 Register 2: DES Key 3 MSW for 192-Bit Key (DES_KEY3_H), offset 0x004 Register 3: DES Key 2 LSW for 128-Bit Key (DES_KEY2_L), offset 0x008 Register 4: DES Key 2 MSW for 128-Bit Key (DES_KEY2_H), offset 0x00C Register 5: DES Key 1 LSW for 64-Bit Key (DES_KEY1_L), offset 0x010 Register 6: DES Key 1 MSW for 64-Bit Key (DES_KEY1_H), offset 0x014 The function of each of these registers is described in
PAGE 1027
Tiva™ TM4C129ENCPDT Microcontroller Register 7: DES Initialization Vector (DES_IV_L), offset 0x018 Least significant word of the initialization vector. DES Initialization Vector (DES_IV_L) Base 0x4403.8000 Offset 0x018 Type RW, reset 0x0000.
PAGE 1028
Data Encryption Standard Accelerator (DES) Register 8: DES Initialization Vector (DES_IV_H), offset 0x01C Most significant word of the initialization vector. DES Initialization Vector (DES_IV_H) Base 0x4403.8000 Offset 0x01C Type RW, reset 0x0000.
PAGE 1029
Tiva™ TM4C129ENCPDT Microcontroller Register 9: DES Control (DES_CTRL), offset 0x020 DES Control (DES_CTRL) Base 0x4403.8000 Offset 0x020 Type RW, reset 0x8000.
PAGE 1030
Data Encryption Standard Accelerator (DES) Register 10: DES Cryptographic Data Length (DES_LENGTH), offset 0x024 Indicates the cryptographic data length in bytes for all modes. Once processing is started with this context, this length decrements to zero. Data lengths up to (232 - 1) bytes are allowed. A write to this register triggers the engine to start using this context. Note: A read of this register returns all zeros. DES Cryptographic Data Length (DES_LENGTH) Base 0x4403.
PAGE 1031
Tiva™ TM4C129ENCPDT Microcontroller Register 11: DES LSW Data RW (DES_DATA_L), offset 0x028 Data register (LSW) to read/write encrypted/decrypted data. DES LSW Data RW (DES_DATA_L) Base 0x4403.8000 Offset 0x028 Type RW, reset 0x0000.
PAGE 1032
Data Encryption Standard Accelerator (DES) Register 12: DES MSW Data RW (DES_DATA_H), offset 0x02C Data register (MSW) to read/write encrypted/decrypted data. DES MSW Data RW (DES_DATA_H) Base 0x4403.8000 Offset 0x02C Type RW, reset 0x0000.
PAGE 1033
Tiva™ TM4C129ENCPDT Microcontroller Register 13: DES Revision Number (DES_REVISION), offset 0x030 Revision Number DES Revision Number (DES_REVISION) Base 0x4403.8000 Offset 0x030 Type RO, reset 0x0000.
PAGE 1034
Data Encryption Standard Accelerator (DES) Register 14: DES System Configuration (DES_SYSCONFIG), offset 0x034 System Configuration of DES module Note: After one operation has completed, the DES_SYSCONFIG register must be cleared and re-configured for the next operation to ensure proper DMA and data operation functionality. DES System Configuration (DES_SYSCONFIG) Base 0x4403.8000 Offset 0x034 Type RW, reset 0x0000.
PAGE 1035
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 reserved RO 0 3:2 SIDLE RW 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
PAGE 1036
Data Encryption Standard Accelerator (DES) Register 15: DES System Status (DES_SYSSTATUS), offset 0x038 System Status Register DES System Status (DES_SYSSTATUS) Base 0x4403.8000 Offset 0x038 Type RO, reset 0x0000.
PAGE 1037
Tiva™ TM4C129ENCPDT Microcontroller Register 16: DES Interrupt Status (DES_IRQSTATUS), offset 0x03C This register indicates the interrupt status. If one of the interrupt bits is set the interrupt output will be asserted. DES Interrupt Status (DES_IRQSTATUS) Base 0x4403.8000 Offset 0x03C Type RO, reset 0x0000.
PAGE 1038
Data Encryption Standard Accelerator (DES) Register 17: DES Interrupt Enable (DES_IRQENABLE), offset 0x040 This register contains an enable bit for each unique interrupt generated by the module. It matches the layout of DES_IRQSTATUS register. An interrupt is enabled when the bit in this register is set to 1. DES Interrupt Enable (DES_IRQENABLE) Base 0x4403.8000 Offset 0x040 Type RW, reset 0x0000.
PAGE 1039
Tiva™ TM4C129ENCPDT Microcontroller Register 18: DES Dirty Bits (DES_DIRTYBITS), offset 0x044 DES Dirty Bits (DES_DIRTYBITS) Base 0x4403.8000 Offset 0x044 Type RW1C, reset 0x0000.
PAGE 1040
Data Encryption Standard Accelerator (DES) Register 19: DES DMA Interrupt Mask (DES_DMAIM), offset 0x030 The DES DMA Interrupt Mask register control interrupt behavior and are used to program which interrupts are suppressed. DES DMA Interrupt Mask (DES_DMAIM) Base 0x4403.0000 Offset 0x030 Type RW, reset 0x0000.
PAGE 1041
Tiva™ TM4C129ENCPDT Microcontroller Register 20: DES DMA Raw Interrupt Status (DES_DMARIS), offset 0x034 The DES DMA Raw Interrupt Status register contains the raw interrupt status. If any of these bits read 1, the processor is interrupted if the corresponding masked interrupt status bit is set to 1. DES DMA Raw Interrupt Status (DES_DMARIS) Base 0x4403.0000 Offset 0x034 Type RO, reset 0x0000.
PAGE 1042
Data Encryption Standard Accelerator (DES) Register 21: DES DMA Masked Interrupt Status (DES_DMAMIS), offset 0x038 The DES DMA Masked Interrupt Status register displays the raw interrupts that are unmasked in the DES DMA Raw Interrupt Status (DES_DMARIS) register. DES DMA Masked Interrupt Status (DES_DMAMIS) Base 0x4403.0000 Offset 0x038 Type RO, reset 0x0000.
PAGE 1043
Tiva™ TM4C129ENCPDT Microcontroller Register 22: DES DMA Interrupt Clear (DES_DMAIC), offset 0x03C The DES DMA Interrupt Clear register is used to clear the DES_DMARIS and DES_DMAMIS registers by writing a 1 to the corresponding register bit. Note: This registers always reads as zero. DES DMA Interrupt Clear (DES_DMAIC) Base 0x4403.0000 Offset 0x03C Type W1C, reset 0x0000.
PAGE 1044
SHA/MD5 Accelerator 15 SHA/MD5 Accelerator The SHA/MD5 module provides hardware-accelerated hash functions and can run: ■ MD5 message digest algorithm developed by Ron Rivest in 1991 ■ SHA-1 algorithm compliant with the FIPS 180-3 standard ■ SHA-2 (SHA-224 and SHA-256) algorithm compliant with the FIPS 180-3 standard ■ Hash message authentication code (HMAC) operation The algorithms produce a condensed representation of a message or a data file, called digest or signature, which can then be used to verify
PAGE 1045
Tiva™ TM4C129ENCPDT Microcontroller Interrupt Handler 15.1.1.1 Host Interface Bank Hash Scheduler µDMA Interface to µDMA and Interrupt Handler Figure 15-1.
PAGE 1046
SHA/MD5 Accelerator 15.1.1.4 Host Interface Bank The Host Interface Bank can access the hash core for hashing individual 64-byte hash blocks. The Host Interface Bank contains registers such as the data FIFO (SHA Data n Input (SHA_DATA_n_IN) registers), the SHA Inner Digest x (SHA_IDIGEST_X) registers, and several control and status registers.
PAGE 1047
Tiva™ TM4C129ENCPDT Microcontroller when context out, context in, data in or data out is ready. The SHA Interrupt Status (SHA_IRQSTATUS), offset 0x118, indicates when an interrupt is triggered. Note: If the application uses Interrupt Mode, an interrupt is generated for each block of processed data. To support larger data flow, SHA µDMA Mode should be used and the bits in the SHA_IRQENABLE register should be cleared. Table 15-1. Interrupts and Events 15.1.
PAGE 1048
SHA/MD5 Accelerator data to process. Data must be written to the 16 x 32-bit SHA_DATA_n_IN registers that provide storage for one 64-byte block of data. Unless the CLOSE_HASH bit is set, all of the SHA_DATA_n_IN input buffers must be filled. Data can be written by single write accesses to the 16 registers from a processor or by a DMA transfer.
PAGE 1049
Tiva™ TM4C129ENCPDT Microcontroller Table 15-4.
PAGE 1050
SHA/MD5 Accelerator SHA_ODIGEST_D, the SHA-1 outer digest from registers SHA_ODIGEST_A to SHA_ODIGEST_E, and the SHA-224 and SHA-256 outer digest from registersSHA_ODIGEST_A to SHA_ODIGEST_H. Note: The HMAC key is not preserved. If another block must be authenticated using the same key, the key must be reloaded by the host.
PAGE 1051
Tiva™ TM4C129ENCPDT Microcontroller If the size of the last block of data is less than or equal to 55 bytes, no additional 64-byte block is required. However, if the last block of data contains more than 55 bytes, an extra 64-byte block must be added to make the padding as specified by FIPS 180-1. This extra block is added automatically by the hardware; thus, the module is fed with a 64-byte block of data.
PAGE 1052
SHA/MD5 Accelerator Table 15-6. SHA Digest Processed in One Pass (continued) Digest (A to E) SHA_DATA_n_IN Round 1 digest calculation Second 64 bytes of message Round 2 digest calculation Last byte of message Final digest 15.1.5.2 SHA_DIGEST_COUNT SHA_MODE and SHA_LENGTH Read: 129 MD5 Mode Starting a New Hash To start a new hash, perform the following steps: 1. Set the ALGO bit field in the SHA_MODE register to 0x0 to select the MD5 algorithm. 2.
PAGE 1053
Tiva™ TM4C129ENCPDT Microcontroller Closing a Hash The amount of data to hash is not necessarily a multiple of 64 bytes. In this case, the CLOSE_HASH bit in the SHA_MODE register must be set to append padding so that the message size becomes a multiple of 64 bytes. See the previous MD5 algorithm for more information on padding. The module is fed with a 64-byte block of data, as long as enough data is available. However, a pad is appended on the last block of data.
PAGE 1054
SHA/MD5 Accelerator Table 15-7. SHA/MD5 Performance (continued) Operation Algorithm Cycles per operation Cycles per block MD5 196 / 261 65 SHA-1 244 / 325 81 HMAC from Key SHA-224 196 / 261 65 SHA-256 196 / 261 65 MD5 66 / 131 65 SHA-1 82 / 163 81 SHA-224 66 / 131 65 SHA-256 66 / 131 65 HMAC from precomputes Note: 15.1.7 An extra block needs to be processed if the length of the data block to be hashed module 64 is 0 or equal to 56.
PAGE 1055
Tiva™ TM4C129ENCPDT Microcontroller 2. Pad the rest of the SHA _ODIGEST_x and SHA_IDIGEST registers with zeros. 3. Load the message in the SHA_DATA_n_IN FIFO registers. 4. Enable HMAC key processing by setting the HMAC_KEY_PROC bit in the SHA_MODE register. 5. Select the SHA-1 hash function by programming the ALGO bit in the SHA_MODE register to 0x1. 6. Select the already loaded key by programming the ALGO_CONSTANT bit in the SHA_MODE register to 0x0. 7.
PAGE 1056
SHA/MD5 Accelerator Table 15-9. SHA-1 Apply on the Key Step Register/Bit Field/Programming Model Value Load the first part of the key. (Here, the key is like a message.) SHA_DATA_n_IN (i = 0 to 15) - Select the SHA-1 hash function. SHA_MODE[2:1] ALGO 0x1 Select a new hash operation. SHA_MODE[3] ALGO_CONSTANT 0x1 Close the hash; the key is processed in single pass.
PAGE 1057
Tiva™ TM4C129ENCPDT Microcontroller Table 15-10. Interrupt Mode (continued) Step Register/Bit Field/Programming Model Value Load the message length; this is the trigger to start processing. SHA_LENGTH[31:0] LENGTH - SHA/MD5 DMA Mode The procedure in configures the SHA/MD5 module to work in DMA-based mode. Table 15-11. DMA Mode Step Register/Bit Field/Programming Model Value Enable the DMA request to the CDMA controller.
PAGE 1058
SHA/MD5 Accelerator Figure 15-3.
PAGE 1059
Tiva™ TM4C129ENCPDT Microcontroller Table 15-12. SHA/MD5 Register Map (continued) Description See page 0x0000.0000 SHA Outer Digest E 1062 RW 0x0000.0000 SHA Outer Digest F 1062 SHA_ODIGEST_G RW 0x0000.0000 SHA Outer Digest G 1062 0x01C SHA_ODIGEST_H RW 0x0000.0000 SHA Outer Digest H 1062 0x020 SHA_IDIGEST_A RW 0x0000.0000 SHA Inner Digest A 1062 0x024 SHA_IDIGEST_B RW 0x0000.0000 SHA Inner Digest B 1062 0x028 SHA_IDIGEST_C RW 0x0000.
PAGE 1060
SHA/MD5 Accelerator Table 15-12. SHA/MD5 Register Map (continued) Description See page 0x0000.0001 SHA System Configuration 1069 RO 0x0000.0001 SHA System Status 1071 SHA_IRQSTATUS RO 0x0000.0008 SHA Interrupt Status 1072 SHA_IRQENABLE RW 0x0000.0007 SHA Interrupt Enable 1073 Offset Name Type Reset 0x110 SHA_SYSCONFIG RW 0x114 SHA_SYSSTATUS 0x118 0x11C Encryption Control (Encryption Control Offset) 0x010 SHA_DMAIM RW 0x0000.
PAGE 1061
Tiva™ TM4C129ENCPDT Microcontroller Table 15-13.
PAGE 1062
SHA/MD5 Accelerator Register 1: SHA Outer Digest A (SHA_ODIGEST_A), offset 0x000 Register 2: SHA Outer Digest B (SHA_ODIGEST_B), offset 0x004 Register 3: SHA Outer Digest C (SHA_ODIGEST_C), offset 0x008 Register 4: SHA Outer Digest D (SHA_ODIGEST_D), offset 0x00C Register 5: SHA Outer Digest E (SHA_ODIGEST_E), offset 0x010 Register 6: SHA Outer Digest F (SHA_ODIGEST_F), offset 0x014 Register 7: SHA Outer Digest G (SHA_ODIGEST_G), offset 0x018 Register 8: SHA Outer Digest H (SHA_ODIGEST_H), offset 0x01C Reg
PAGE 1063
Tiva™ TM4C129ENCPDT Microcontroller Register 17: SHA Digest Count (SHA_DIGEST_COUNT), offset 0x040 This register is written with the initial digest count and can be read to determine the digest count result. Note that for Initial Digest Count writes, bits 5:0 must be zero. This register is written the initial digest byte count when both the HMAC_KEY_PROC bit and the ALGO_CONSTANT bit is zero in the SHA_MODE register.
PAGE 1064
SHA/MD5 Accelerator Register 18: SHA Mode (SHA_MODE), offset 0x044 This register is written to configure the hash algorithm to be used in the hash operation. SHA Mode (SHA_MODE) 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 reserved CLOSE_HASH ALGO_CONSTANT 30 HMAC_KEY_PROC 31 HMAC_OUTER_HASH Base 0x4403.4000 Offset 0x044 Type RW, reset 0x0000.
PAGE 1065
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset Description 5 HMAC_KEY_PROC RW 0x00 HMAC Key Processing Enable This bit enables HMAC key processing on the 512-bit HMAC key loaded into the SHA_IDIGEST_A through SHA_IDIGEST_H registers and the SHA_ODIGEST_A through SHA_ODIGEST_H register block. Once HMAC key processing is finished, this bit is automatically cleared and the resulting Inner and Outer digest is available in the SHA_IDIGEST_x and SHA_ODIGEST_x respectively.
PAGE 1066
SHA/MD5 Accelerator Register 19: SHA Length (SHA_LENGTH), offset 0x048 WRITE: Block Length/Remaining Byte Count (bytes) READ: Remaining Byte Count. The value programmed MUST be a 64-byte multiple if Close Hash is set to 0. This register is also the trigger to start processing: once this register is written, the core will commence requesting input data via DMA or IRQ (if programmed length > 0) and start processing.
PAGE 1067
Tiva™ TM4C129ENCPDT Microcontroller Register 20: SHA Data 0 Input (SHA_DATA_0_IN), offset 0x080 Register 21: SHA Data 1 Input (SHA_DATA_1_IN), offset 0x084 Register 22: SHA Data 2 Input (SHA_DATA_2_IN), offset 0x088 Register 23: SHA Data 3 Input (SHA_DATA_3_IN), offset 0x08C Register 24: SHA Data 4 Input (SHA_DATA_4_IN), offset 0x090 Register 25: SHA Data 5 Input (SHA_DATA_5_IN), offset 0x094 Register 26: SHA Data 6 Input (SHA_DATA_6_IN), offset 0x098 Register 27: SHA Data 7 Input (SHA_DATA_7_IN), offset 0
PAGE 1068
SHA/MD5 Accelerator Register 36: SHA Revision (SHA_REVISION), offset 0x100 This register provides the unique revision number of the module. This can be used by the driver to determine the capabilities available. SHA Revision (SHA_REVISION) Base 0x4403.
PAGE 1069
Tiva™ TM4C129ENCPDT Microcontroller Register 37: SHA System Configuration (SHA_SYSCONFIG), offset 0x110 System configuration register Note: After one operation has completed, the SHA_SYSCONFIG register must be cleared and re-configured for the next operation to ensure proper µDMA and data operation functionality. SHA System Configuration (SHA_SYSCONFIG) Base 0x4403.4000 Offset 0x110 Type RW, reset 0x0000.
PAGE 1070
SHA/MD5 Accelerator Bit/Field Name Type Reset 3 DMA_EN RW 0 Description µDMA Request Enable This bit controls whether the µDMA interrupts can be programmed/controlled in the SHA_DMA_IM register. Note: If the µDMA is used for transferring data, then the IT_EN bit should be set to 0 and the SHA_IRQENABLE register should be clear. Value Description 2 IT_EN RW 0 0 µDMA interrupts are disabled. 1 µDMA interrupts are enabled.
PAGE 1071
Tiva™ TM4C129ENCPDT Microcontroller Register 38: SHA System Status (SHA_SYSSTATUS), offset 0x114 System status register SHA System Status (SHA_SYSSTATUS) Base 0x4403.4000 Offset 0x114 Type RO, reset 0x0000.
PAGE 1072
SHA/MD5 Accelerator Register 39: SHA Interrupt Status (SHA_IRQSTATUS), offset 0x118 Interrupt Status Register SHA Interrupt Status (SHA_IRQSTATUS) 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 reserved OUTPUT_READY 30 INPUT_READY 31 CONTEXT_READY Base 0x4403.4000 Offset 0x118 Type RO, reset 0x0000.
PAGE 1073
Tiva™ TM4C129ENCPDT Microcontroller Register 40: SHA Interrupt Enable (SHA_IRQENABLE), offset 0x11C The SHA_IRQENABLE register contains an enable bit for each unique interrupt. An interrupt is enabled when both the global enable, the IT_EN bit, in the SHA_SYSCONFIG register and the bit in this register are both set to 1.
PAGE 1074
SHA/MD5 Accelerator 15.4 SHA/MD5 µDMA Control Register Descriptions (Encryption Control Offset) This section lists and describes the SHA/MD5 µDMA registers, in numerical order by address offset. Registers in this section are relative to the Encryption Control base address of 0x4403.0000. Note: The SHA module can only be accessed through privileged mode.
PAGE 1075
Tiva™ TM4C129ENCPDT Microcontroller Register 41: SHA DMA Interrupt Mask (SHA_DMAIM), offset 0x010 The SHA DMA Interrupt Mask (SHA_DMA_IM) register controls interrupt behavior and are used to program which interrupts are suppressed. SHA DMA Interrupt Mask (SHA_DMAIM) Base Offset 0x010 Type RW, reset 0x0000.
PAGE 1076
SHA/MD5 Accelerator Register 42: SHA DMA Raw Interrupt Status (SHA_DMARIS), offset 0x014 The SHA DMA Raw Interrupt Status (SHA_DMA_RIS) register contains the raw interrupt status. If any of these bits read 1, the processor is interrupted if the corresponding masked interrupt status bit is set to '1.' SHA DMA Raw Interrupt Status (SHA_DMARIS) Base Offset 0x014 Type RO, reset 0x0000.
PAGE 1077
Tiva™ TM4C129ENCPDT Microcontroller Register 43: SHA DMA Masked Interrupt Status (SHA_DMAMIS), offset 0x018 The SHA DMA Masked Interrupt Status (SHA_DMA_MIS) register displays the raw interrupts that are unmasked in the SHA_DMA_RIS register. SHA DMA Masked Interrupt Status (SHA_DMAMIS) Base Offset 0x018 Type RO, reset 0x0000.
PAGE 1078
SHA/MD5 Accelerator Register 44: SHA DMA Interrupt Clear (SHA_DMAIC), offset 0x01C The SHA DMA Interrupt Clear register is used to clear the SHA_DMA_RIS and SHA_DMA_MIS registers by writing a 1 to each register bit. Note: This registers always reads as zero. SHA DMA Interrupt Clear (SHA_DMAIC) Base Offset 0x01C Type W1C, reset 0x0000.
PAGE 1079
Tiva™ TM4C129ENCPDT Microcontroller 16 General-Purpose Timers Programmable timers can be used to count or time external events that drive the Timer input pins. The TM4C129ENCPDT General-Purpose Timer Module (GPTM) contains 16/32-bit GPTM blocks. Each 16/32-bit GPTM block provides two 16-bit timers/counters (referred to as Timer A and Timer B) that can be configured to operate independently as timers or event counters, or concatenated to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
PAGE 1080
General-Purpose Timers ■ Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt service routine ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Dedicated channel for each timer – Burst request generated on timer interrupt 16.1 Block Diagram In the block diagram, the specific Capture Compare PWM (CCP) pins available depend on the TM4C129ENCPDT device.
PAGE 1081
Tiva™ TM4C129ENCPDT Microcontroller Table 16-1. Available CCP Pins (continued) Timer 16/32-Bit Timer 3 16/32-Bit Timer 4 16/32-Bit Timer 5 16/32-Bit Timer 6 16/32-Bit Timer 7 16.
PAGE 1082
General-Purpose Timers Table 16-2. General-Purpose Timers Signals (128TQFP) (continued) Pin Name 16.3 Pin Number Pin Mux / Pin Assignment Pin Type Buffer Type Description T4CCP0 74 95 127 PM4 (3) PB0 (3) PD6 (3) I/O TTL 16/32-Bit Timer 4 Capture/Compare/PWM 0. T4CCP1 73 96 128 PM5 (3) PB1 (3) PD7 (3) I/O TTL 16/32-Bit Timer 4 Capture/Compare/PWM 1. T5CCP0 72 91 PM6 (3) PB2 (3) I/O TTL 16/32-Bit Timer 5 Capture/Compare/PWM 0.
PAGE 1083
Tiva™ TM4C129ENCPDT Microcontroller 16.3.1 GPTM Reset Conditions After reset has been applied to the GPTM module, the module is in an inactive state, and all control registers are cleared and in their default states.
PAGE 1084
General-Purpose Timers of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 1100). In the following sections, the variable "n" is used in bit field and register names to imply either a Timer A function or a Timer B function. Throughout this section, the timeout event in down-count mode is 0x0 and in up-count mode is the value in the GPTM Timer n Interval Load (GPTMTnILR) and the optional GPTM Timer n Prescale (GPTMTnPR) registers, with the exception of RTC mode. 16.3.3.
PAGE 1085
Tiva™ TM4C129ENCPDT Microcontroller (GPTMRIS) register). Note that the interrupt status bits are not updated by the hardware unless the TnMIE bit in the GPTMTnMR register is set, which is different than the behavior for the time-out interrupt. The ADC trigger is enabled by setting the TnOTE bit in GPTMCTL and the event that activates the ADC is configured in the GPTM ADC Event (GPTMADCEV) register.
PAGE 1086
General-Purpose Timers The TCACT field can be changed while the GPTM is enabled to generate different combinations of actions. For example, during a periodic event, encodings TCACT = 0x6 or 0x7 can be used to force the initial state of the CCPn pin before the first interrupt and following that, TCACT=0x2 and TCACT=0x3 can be used (alternately) to change the sense of the pin for the subsequent toggle, while possible changing load value for the next period.
PAGE 1087
Tiva™ TM4C129ENCPDT Microcontroller determined by the TnEVENT fields of the GPTMCTL register. During initialization in down-count mode, the GPTMTnMATCHR and GPTMTnPMR registers are configured so that the difference between the value in the GPTMTnILR and GPTMTnPR registers and the GPTMTnMATCHR and GPTMTnPMR registers equals the number of edge events that must be counted. In up-count mode, the timer counts from 0x0 to the value in the GPTMTnMATCHR and GPTMTnPMR registers.
PAGE 1088
General-Purpose Timers Figure 16-2. Input Edge-Count Mode Example, Counting Down Timer stops, flags asserted Count Timer reload on next cycle Ignored Ignored 0x000A 0x0009 0x0008 0x0007 0x0006 Input Signal 16.3.3.4 Input Edge-Time Mode Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge. Similarly, for falling edge detection, the input signal must be Low for at least two system clock periods following the falling edge.
PAGE 1089
Tiva™ TM4C129ENCPDT Microcontroller the GPTMTnV register holds the free-running timer value. These registers can be read to determine the time that elapsed between the interrupt assertion and the entry into the ISR. In addition to generating interrupts, an ADC and/or a μDMA trigger can be generated. The ADC trigger is enabled by setting the TnOTE bit in GPTMCTL and the event that activates the ADC is configured in the GPTM ADC Event (GPTMADCEV) register.
PAGE 1090
General-Purpose Timers 16.3.3.5 PWM Mode The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a 24-bit down-counter with a start value (and thus period) defined by the GPTMTnILR and GPTMTnPR registers. In this mode, the PWM frequency and period are synchronous events and therefore guaranteed to be glitch free. PWM mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2.
PAGE 1091
Tiva™ TM4C129ENCPDT Microcontroller Figure 16-4. 16-Bit PWM Mode Example Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR 0xC350 0x411A Time TnEN set TnPWML = 0 Output Signal TnPWML = 1 When synchronizing the timers using the GPTMSYNC register, the timer must be properly configured to avoid glitches on the CCP outputs. Both the TnPLO and the TnMRSU bits must be set in the GPTMTnMR register.
PAGE 1092
General-Purpose Timers Figure 16-6. CCP Output, GPTMTnMATCHR = GPTMTnILR GPTMnMATCHR CounterValue GPTMnILR CCP CCP not set if GPTMnMATCHR = GPTMnILR Figure 16-7 on page 1092 shows how the CCP output operates when the PLO and MRSU bits are set and the GPTMTnILR is greater than the GPTMTnMATCHR value. Figure 16-7. CCP Output, GPTMTnILR > GPTMTnMATCHR GPTMnILR GPTMnMATCHR = GPTMnILR-1 GPTMnMATCHR = GPTMnILR-2 GPTMnMATCHR == 0 16.3.
PAGE 1093
Tiva™ TM4C129ENCPDT Microcontroller Figure 16-8. Timer Daisy Chain GP Timer N+1 1 0 GPTMTnMR.TnWOT Timer B ADC Trigger Timer B Timer A Timer A ADC Trigger GP Timer N 1 0 GPTMTnMR.TnWOT Timer B ADC Trigger Timer B Timer A 16.3.5 Timer A ADC Trigger Synchronizing GP Timer Blocks The GPTM Synchronizer Control (GPTMSYNC) register in the GPTM0 block can be used to synchronize selected timers to begin counting at the same time.
PAGE 1094
General-Purpose Timers 16.3.6 DMA Operation The timers each have a dedicated μDMA channel and can provide a request signal to the μDMA controller. Pulse requests are generated by a timer via its own dma_req signal. A dma_done signal is provided from the µDMA to each timer to indicate transfer completion and trigger a µDMA done interrupt (DMAnRIS) in the GPTM Raw Interrupt Status Register (GPTMRIS) register. The request is a burst type and occurs whenever a timer raw interrupt condition occurs.
PAGE 1095
Tiva™ TM4C129ENCPDT Microcontroller In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is: GPTMTBILR[15:0]:GPTMTAILR[15:0] Likewise, a 32-bit read access to GPTMTAR returns the value: GPTMTBR[15:0]:GPTMTAR[15:0] A 32-bit read access to GPTMTAV returns the value: GPTMTBV[15:0]:GPTMTAV[15:0] 16.
PAGE 1096
General-Purpose Timers If the TnMIE bit in the GPTMTnMR register is set, the RTCRIS bit in the GPTMRIS register is set, and the timer continues counting. In One-Shot mode, the timer stops counting after the time-out event. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode reloads the timer and continues counting after the time-out event. 16.4.2 Real-Time Clock (RTC) Mode To use the RTC mode, the timer must have a 32.768-KHz input signal on an even CCP input.
PAGE 1097
Tiva™ TM4C129ENCPDT Microcontroller 6. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 7. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events. 8. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM Interrupt Clear (GPTMICR) register.
PAGE 1098
General-Purpose Timers 4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnPWML field of the GPTM Control (GPTMCTL) register. 5. If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale Register (GPTMTnPR). 6. If PWM interrupts are used, configure the interrupt condition in the TnEVENT field in the GPTMCTL register and enable the interrupts by setting the TnPWMIE bit in the GPTMTnMR register.
PAGE 1099
Tiva™ TM4C129ENCPDT Microcontroller Table 16-11. Timers Register Map (continued) Description See page 0x0000.0000 GPTM Raw Interrupt Status 1120 RO 0x0000.0000 GPTM Masked Interrupt Status 1123 GPTMICR W1C 0x0000.0000 GPTM Interrupt Clear 1126 0x028 GPTMTAILR RW 0xFFFF.FFFF GPTM Timer A Interval Load 1128 0x02C GPTMTBILR RW 0x0000.FFFF GPTM Timer B Interval Load 1129 0x030 GPTMTAMATCHR RW 0xFFFF.FFFF GPTM Timer A Match 1130 0x034 GPTMTBMATCHR RW 0x0000.
PAGE 1100
General-Purpose Timers Register 1: GPTM Configuration (GPTMCFG), offset 0x000 This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32- or 16-bit mode. Important: Bits in this register should only be changed when the TAEN and TBEN bits in the GPTMCTL register are cleared. GPTM Configuration (GPTMCFG) 16/32-bit Timer 0 base: 0x4003.0000 16/32-bit Timer 1 base: 0x4003.1000 16/32-bit Timer 2 base: 0x4003.
PAGE 1101
Tiva™ TM4C129ENCPDT Microcontroller Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in PWM mode, set the TAAMS bit, clear the TACMR bit, and configure the TAMR field to 0x1 or 0x2. This register controls the modes for Timer A when it is used individually. When Timer A and Timer B are concatenated, this register controls the modes for both Timer A and Timer B, and the contents of GPTMTBMR are ignored.
PAGE 1102
General-Purpose Timers Bit/Field Name Type Reset 12 TACINTD RW 0 Description One-shot/Periodic Interrupt Disable Value Description 0 Time-out interrupt functions as normal. 1 Time-out interrupt are disabled. Note: 11 TAPLO RW 0 Setting the TACINTD bit in the GPTMTAMR register does not have an effect on the µDMA or ADC interrupt time-out event trigger assertions.
PAGE 1103
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 8 TAILD RW 0 Description GPTM Timer A Interval Load Write Value Description 0 Update the GPTMTAR and GPTMTAV registers with the value in the GPTMTAILR register on the next cycle. Also update the GPTMTAPS register with the value in the GPTMTAPR register on the next cycle. 1 Update the GPTMTAR and GPTMTAV registers with the value in the GPTMTAILR register on the next timeout.
PAGE 1104
General-Purpose Timers Bit/Field Name Type Reset 5 TAMIE RW 0 Description GPTM Timer A Match Interrupt Enable Value Description 0 The match interrupt is disabled for match events. Note: 1 4 TACDIR RW 0 Clearing the TAMIE bit in the GPTMTAMR register prevents assertion of µDMA or ADC requests generated on a match event.
PAGE 1105
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1:0 TAMR RW 0x0 Description GPTM Timer A Mode The TAMR values are defined as follows: Value Description 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register.
PAGE 1106
General-Purpose Timers Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in PWM mode, set the TBAMS bit, clear the TBCMR bit, and configure the TBMR field to 0x1 or 0x2. This register controls the modes for Timer B when it is used individually. When Timer A and Timer B are concatenated, this register is ignored and GPTMTAMR controls the modes for both Timer A and Timer B.
PAGE 1107
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 12 TBCINTD RW 0 Description One-Shot/Periodic Interrupt Disable Value Description 0 Time-out interrupt functions normally 1 Time-out interrupt functionality is disabled Note: 11 TBPLO RW 0 Setting the TBCINTD bit in the GPTMTBMR register does not have an effect on the µDMA or ADC interrupt time-out event trigger assertions.
PAGE 1108
General-Purpose Timers Bit/Field Name Type Reset 8 TBILD RW 0 Description GPTM Timer B Interval Load Write Value Description 0 Update the GPTMTBR and GPTMTBV registers with the value in the GPTMTBILR register on the next cycle. Also update the GPTMTBPS register with the value in the GPTMTBPR register on the next cycle. 1 Update the GPTMTBR and GPTMTBV registers with the value in the GPTMTBILR register on the next timeout.
PAGE 1109
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 TBCDIR RW 0 Description GPTM Timer B Count Direction Value Description 0 The timer counts down. 1 The timer counts up. When counting up, the timer starts from a value of 0x0. When in PWM or RTC mode, the status of this bit is ignored. PWM mode always counts down and RTC mode always counts up.
PAGE 1110
General-Purpose Timers Register 4: GPTM Control (GPTMCTL), offset 0x00C This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger. The output trigger can be used to initiate transfers on the ADC module. Important: Bits in this register should only be changed when the TnEN bit for the respective timer is cleared. GPTM Control (GPTMCTL) 16/32-bit Timer 0 base: 0x4003.
PAGE 1111
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 11:10 TBEVENT RW 0x0 Description GPTM Timer B Event Mode The TBEVENT values are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges Note: 9 TBSTALL RW 0 If PWM output inversion is enabled, edge detection interrupt behavior is reversed. Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a postive edge, no event-trigger interrupt asserts.
PAGE 1112
General-Purpose Timers Bit/Field Name Type Reset 5 TAOTE RW 0 Description GPTM Timer A Output Trigger Enable The TAOTE values are defined as follows: Value Description 0 The output Timer A ADC trigger is disabled. 1 The output Timer A ADC trigger is enabled. In addition, the ADC must be enabled and the timer selected as a trigger source with the EMn bit in the ADCEMUX register (see page 1215).
PAGE 1113
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 0 TAEN RW 0 Description GPTM Timer A Enable The TAEN values are defined as follows: Value Description 0 Timer A is disabled. 1 Timer A is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register.
PAGE 1114
General-Purpose Timers Register 5: GPTM Synchronize (GPTMSYNC), offset 0x010 Note: This register is only implemented on GPTM Module 0 only. This register allows software to synchronize a number of timers. GPTM Synchronize (GPTMSYNC) 16/32-bit Timer 0 base: 0x4003.0000 16/32-bit Timer 1 base: 0x4003.1000 16/32-bit Timer 2 base: 0x4003.2000 16/32-bit Timer 3 base: 0x4003.3000 16/32-bit Timer 4 base: 0x4003.4000 16/32-bit Timer 5 base: 0x4003.5000 16/32-bit Timer 6 base: 0x400E.
PAGE 1115
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 11:10 SYNCT5 WO 0x0 Description Synchronize GPTM Timer 5 Value Description 9:8 SYNCT4 WO 0x0 0x0 GPTM5 is not affected. 0x1 A timeout event for Timer A of GPTM5 is triggered. 0x2 A timeout event for Timer B of GPTM5 is triggered. 0x3 A timeout event for both Timer A and Timer B of GPTM5 is triggered. Synchronize GPTM Timer 4 Value Description 7:6 SYNCT3 WO 0x0 0x0 GPTM4 is not affected.
PAGE 1116
General-Purpose Timers Bit/Field Name Type Reset 1:0 SYNCT0 WO 0x0 Description Synchronize GPTM Timer 0 Value Description 0x0 GPTM0 is not affected. 0x1 A timeout event for Timer A of GPTM0 is triggered. 0x2 A timeout event for Timer B of GPTM0 is triggered. 0x3 A timeout event for both Timer A and Timer B of GPTM0 is triggered.
PAGE 1117
Tiva™ TM4C129ENCPDT Microcontroller Register 6: GPTM Interrupt Mask (GPTMIMR), offset 0x018 This register allows software to enable/disable GPTM controller-level interrupts. Setting a bit enables the corresponding interrupt, while clearing a bit disables it. GPTM Interrupt Mask (GPTMIMR) 16/32-bit Timer 0 base: 0x4003.0000 16/32-bit Timer 1 base: 0x4003.1000 16/32-bit Timer 2 base: 0x4003.2000 16/32-bit Timer 3 base: 0x4003.3000 16/32-bit Timer 4 base: 0x4003.4000 16/32-bit Timer 5 base: 0x4003.
PAGE 1118
General-Purpose Timers Bit/Field Name Type Reset 9 CBMIM RW 0 Description GPTM Timer B Capture Mode Match Interrupt Mask The CBMIM values are defined as follows: Value Description 8 TBTOIM RW 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM Timer B Time-Out Interrupt Mask The TBTOIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 7:6 reserved RO 0 Software should not rely on the value of a reserved bit.
PAGE 1119
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1 CAMIM RW 0 Description GPTM Timer A Capture Mode Match Interrupt Mask The CAMIM values are defined as follows: Value Description 0 TATOIM RW 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM Timer A Time-Out Interrupt Mask The TATOIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled.
PAGE 1120
General-Purpose Timers Register 7: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its corresponding bit in GPTMICR. Note: The state of the GPTMRIS register is not affected by disabling and then re-enabling the timer using the TnEN bits in the GPTM Control (GPTMCTL) register.
PAGE 1121
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 11 TBMRIS RO 0 Description GPTM Timer B Match Raw Interrupt Value Description 0 The match value has not been reached. 1 The TBMIE bit is set in the GPTMTBMR register, and the match values in the GPTMTBMATCHR and (optionally) GPTMTBPMR registers have been reached when configured in one-shot or periodic mode. This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR register.
PAGE 1122
General-Purpose Timers Bit/Field Name Type Reset 4 TAMRIS RO 0 Description GPTM Timer A Match Raw Interrupt Value Description 0 The match value has not been reached. 1 The TAMIE bit is set in the GPTMTAMR register, and the match value in the GPTMTAMATCHR and (optionally) GPTMTAPMR registers have been reached when configured in one-shot or periodic mode. This bit is cleared by writing a 1 to the TAMCINT bit in the GPTMICR register.
PAGE 1123
Tiva™ TM4C129ENCPDT Microcontroller Register 8: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR. GPTM Masked Interrupt Status (GPTMMIS) 16/32-bit Timer 0 base: 0x4003.0000 16/32-bit Timer 1 base: 0x4003.
PAGE 1124
General-Purpose Timers Bit/Field Name Type Reset 10 CBEMIS RO 0 Description GPTM Timer B Capture Mode Event Masked Interrupt Value Description 0 A Capture B event interrupt has not occurred or is masked. 1 An unmasked Capture B event interrupt has occurred. This bit is cleared by writing a 1 to the CBECINT bit in the GPTMICR register. 9 CBMMIS RO 0 GPTM Timer B Capture Mode Match Masked Interrupt Value Description 0 A Capture B Mode Match interrupt has not occurred or is masked.
PAGE 1125
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3 RTCMIS RO 0 Description GPTM RTC Masked Interrupt Value Description 0 An RTC event interrupt has not occurred or is masked. 1 An unmasked RTC event interrupt has occurred. This bit is cleared by writing a 1 to the RTCCINT bit in the GPTMICR register. 2 CAEMIS RO 0 GPTM Timer A Capture Mode Event Masked Interrupt Value Description 0 A Capture A event interrupt has not occurred or is masked.
PAGE 1126
General-Purpose Timers Register 9: GPTM Interrupt Clear (GPTMICR), offset 0x024 This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers. GPTM Interrupt Clear (GPTMICR) 16/32-bit Timer 0 base: 0x4003.0000 16/32-bit Timer 1 base: 0x4003.1000 16/32-bit Timer 2 base: 0x4003.2000 16/32-bit Timer 3 base: 0x4003.3000 16/32-bit Timer 4 base: 0x4003.4000 16/32-bit Timer 5 base: 0x4003.
PAGE 1127
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 5 DMAAINT W1C 0 Description GPTM Timer A DMA Done Interrupt Clear Writing a 1 to this bit clears the DMAARIS bit in the GPTMRIS register and the DMAAMIS bit in the GPTMMIS register. 4 TAMCINT W1C 0 GPTM Timer A Match Interrupt Clear Writing a 1 to this bit clears the TAMRIS bit in the GPTMRIS register and the TAMMIS bit in the GPTMMIS register.
PAGE 1128
General-Purpose Timers Register 10: GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 When the timer is counting down, this register is used to load the starting count value into the timer. When the timer is counting up, this register sets the upper bound for the timeout event. When a GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B Interval Load (GPTMTBILR) register).
PAGE 1129
Tiva™ TM4C129ENCPDT Microcontroller Register 11: GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C When the timer is counting down, this register is used to load the starting count value into the timer. When the timer is counting up, this register sets the upper bound for the timeout event. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the GPTMTAILR register.
PAGE 1130
General-Purpose Timers Register 12: GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 This register is loaded with a match value. Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this register along with GPTMTAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTAILR minus this value.
PAGE 1131
Tiva™ TM4C129ENCPDT Microcontroller Register 13: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 This register is loaded with a match value. Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this register along with GPTMTBILR determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTBILR minus this value.
PAGE 1132
General-Purpose Timers Register 14: GPTM Timer A Prescale (GPTMTAPR), offset 0x038 This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in the GPTMTAR and GPTMTAV registers are incremented.
PAGE 1133
Tiva™ TM4C129ENCPDT Microcontroller Register 15: GPTM Timer B Prescale (GPTMTBPR), offset 0x03C This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in the GPTMTBR and GPTMTBV registers are incremented.
PAGE 1134
General-Purpose Timers Register 16: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 This register allows software to extend the range of the GPTMTAMATCHR when the timers are used individually. This register holds bits 23:16 in the 16-bit modes of the 16/32-bit GPTM. GPTM TimerA Prescale Match (GPTMTAPMR) 16/32-bit Timer 0 base: 0x4003.0000 16/32-bit Timer 1 base: 0x4003.1000 16/32-bit Timer 2 base: 0x4003.2000 16/32-bit Timer 3 base: 0x4003.3000 16/32-bit Timer 4 base: 0x4003.
PAGE 1135
Tiva™ TM4C129ENCPDT Microcontroller Register 17: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 This register allows software to extend the range of the GPTMTBMATCHR when the timers are used individually. This register holds bits 23:16 in the 16-bit modes of the 16/32-bit GPTM. GPTM TimerB Prescale Match (GPTMTBPMR) 16/32-bit Timer 0 base: 0x4003.0000 16/32-bit Timer 1 base: 0x4003.1000 16/32-bit Timer 2 base: 0x4003.2000 16/32-bit Timer 3 base: 0x4003.3000 16/32-bit Timer 4 base: 0x4003.
PAGE 1136
General-Purpose Timers Register 18: GPTM Timer A (GPTMTAR), offset 0x048 This register shows the current value of the Timer A counter in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. Note: When an alternate clock source is enabled, a read of this register returns the current count -1.
PAGE 1137
Tiva™ TM4C129ENCPDT Microcontroller Register 19: GPTM Timer B (GPTMTBR), offset 0x04C This register shows the current value of the Timer B counter in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. Note: When an alternate clock source is enabled, a read of this register returns the current count -1.
PAGE 1138
General-Purpose Timers Register 20: GPTM Timer A Value (GPTMTAV), offset 0x050 When read, this register shows the current, free-running value of Timer A in all modes. Software can use this value to determine the time elapsed between an interrupt and the ISR entry when using the snapshot feature with the periodic operating mode. When written, the value written into this register is loaded into the GPTMTAR register on the next clock cycle.
PAGE 1139
Tiva™ TM4C129ENCPDT Microcontroller Register 21: GPTM Timer B Value (GPTMTBV), offset 0x054 When read, this register shows the current, free-running value of Timer B in all modes. Software can use this value to determine the time elapsed between an interrupt and the ISR entry. When written, the value written into this register is loaded into the GPTMTBR register on the next clock cycle. Note: When an alternate clock source is enabled, a read of this register returns the current count -1.
PAGE 1140
General-Purpose Timers Register 22: GPTM RTC Predivide (GPTMRTCPD), offset 0x058 This register provides the current RTC predivider value when the timer is operating in RTC mode. Software must perform an atomic access with consecutive reads of the GPTMTAR, GPTMTBR, and GPTMRTCPD registers. Note: When an alternate clock source is enabled, a read of this register returns the current count -1. GPTM RTC Predivide (GPTMRTCPD) 16/32-bit Timer 0 base: 0x4003.0000 16/32-bit Timer 1 base: 0x4003.
PAGE 1141
Tiva™ TM4C129ENCPDT Microcontroller Register 23: GPTM Timer A Prescale Snapshot (GPTMTAPS), offset 0x05C For 16-/32-bit wide GPTM, this register shows the current value of the Timer A prescaler for periodic snapshot mode. GPTM Timer A Prescale Snapshot (GPTMTAPS) 16/32-bit Timer 0 base: 0x4003.0000 16/32-bit Timer 1 base: 0x4003.1000 16/32-bit Timer 2 base: 0x4003.2000 16/32-bit Timer 3 base: 0x4003.3000 16/32-bit Timer 4 base: 0x4003.4000 16/32-bit Timer 5 base: 0x4003.5000 16/32-bit Timer 6 base: 0x400E.
PAGE 1142
General-Purpose Timers Register 24: GPTM Timer B Prescale Snapshot (GPTMTBPS), offset 0x060 For 16-/32-bit wide GPTM, this register shows the current value of the Timer B prescaler for periodic snapshot mode. GPTM Timer B Prescale Snapshot (GPTMTBPS) 16/32-bit Timer 0 base: 0x4003.0000 16/32-bit Timer 1 base: 0x4003.1000 16/32-bit Timer 2 base: 0x4003.2000 16/32-bit Timer 3 base: 0x4003.3000 16/32-bit Timer 4 base: 0x4003.4000 16/32-bit Timer 5 base: 0x4003.5000 16/32-bit Timer 6 base: 0x400E.
PAGE 1143
Tiva™ TM4C129ENCPDT Microcontroller Register 25: GPTM DMA Event (GPTMDMAEV), offset 0x06C This register allows software to enable/disable GPTM DMA trigger events. Setting a bit enables the corresponding DMA trigger, while clearing a bit disables it. GPTM DMA Event (GPTMDMAEV) 16/32-bit Timer 0 base: 0x4003.0000 16/32-bit Timer 1 base: 0x4003.1000 16/32-bit Timer 2 base: 0x4003.2000 16/32-bit Timer 3 base: 0x4003.3000 16/32-bit Timer 4 base: 0x4003.4000 16/32-bit Timer 5 base: 0x4003.
PAGE 1144
General-Purpose Timers Bit/Field Name Type Reset 8 TBTODMAEN RW 0 Description GPTM B Time-Out Event DMA Trigger Enable When this bit is enabled, a Timer B dma_req signal is sent to the µDMA on a time-out event. Value Description 0 Timer B Time-Out DMA trigger is disabled. 1 Timer B Time-Out DMA trigger is enabled. 7:5 reserved RO 0 Software should not rely on the value of a reserved bit.
PAGE 1145
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 0 TATODMAEN RW 0 Description GPTM A Time-Out Event DMA Trigger Enable When this bit is enabled, a Timer A dma_req signal is sent to the µDMA on a time-out event. Value Description 0 Timer A Time-Out DMA trigger is disabled. 1 Timer A Time-Out DMA trigger is enabled.
PAGE 1146
General-Purpose Timers Register 26: GPTM ADC Event (GPTMADCEV), offset 0x070 This register allows software to enable/disable GPTM ADC trigger events. Setting a bit enables the corresponding ADC trigger, while clearing a bit disables it. GPTM ADC Event (GPTMADCEV) 16/32-bit Timer 0 base: 0x4003.0000 16/32-bit Timer 1 base: 0x4003.1000 16/32-bit Timer 2 base: 0x4003.2000 16/32-bit Timer 3 base: 0x4003.3000 16/32-bit Timer 4 base: 0x4003.4000 16/32-bit Timer 5 base: 0x4003.5000 16/32-bit Timer 6 base: 0x400E.
PAGE 1147
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 8 TBTOADCEN RW 0 Description GPTM B Time-Out Event ADC Trigger Enable When this bit is enabled, a trigger signal is sent to the ADC on a time-out event. Value Description 0 Timer B Time-Out ADC trigger is disabled. 1 Timer B Time-Out ADC trigger is enabled. 7:5 reserved RO 0 Software should not rely on the value of a reserved bit.
PAGE 1148
General-Purpose Timers Bit/Field Name Type Reset 0 TATOADCEN RW 0 Description GPTM A Time-Out Event ADC Trigger Enable When this bit is enabled, a trigger signal is sent to the ADC on a time-out event. Value Description 0 Timer A Time-Out Event ADC trigger is disabled. 1 Timer A Time-Out Event ADC trigger is enabled.
PAGE 1149
Tiva™ TM4C129ENCPDT Microcontroller Register 27: GPTM Peripheral Properties (GPTMPP), offset 0xFC0 The GPTMPP register provides information regarding the properties of the General-Purpose Timer module. GPTM Peripheral Properties (GPTMPP) 16/32-bit Timer 0 base: 0x4003.0000 16/32-bit Timer 1 base: 0x4003.1000 16/32-bit Timer 2 base: 0x4003.2000 16/32-bit Timer 3 base: 0x4003.3000 16/32-bit Timer 4 base: 0x4003.4000 16/32-bit Timer 5 base: 0x4003.5000 16/32-bit Timer 6 base: 0x400E.
PAGE 1150
General-Purpose Timers Bit/Field Name Type Reset Description 3:0 SIZE RO 0x0 Count Size Value Description 0 Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter. 1 Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter.
PAGE 1151
Tiva™ TM4C129ENCPDT Microcontroller Register 28: GPTM Clock Configuration (GPTMCC), offset 0xFC8 The GPTMCC register controls the clock source for the General-Purpose Timer module. Note: When the ALTCLK bit is set in the GPTMCC register to enable using the alternate clock source, the synchronization imposes restrictions on the starting count value (down-count), terminal value (up-count) and the match value. This restriction applies to all modes of operation.
PAGE 1152
Watchdog Timers 17 Watchdog Timers A watchdog timer can generate a non-maskable interrupt (NMI), a regular interrupt or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way.
PAGE 1153
Tiva™ TM4C129ENCPDT Microcontroller 17.1 Block Diagram Figure 17-1. WDT Module Block Diagram WDTLOAD Control / Clock / Interrupt Generation WDTCTL WDTICR Interrupt/NMI WDTRIS 32-Bit Down Counter WDTMIS 0x0000.0000 WDTLOCK System Clock/ PIOSC WDTTEST Comparator WDTVALUE Identification Registers 17.
PAGE 1154
Watchdog Timers Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared by writing to the Watchdog Interrupt Clear (WDTICR) register. The Watchdog module interrupt and reset generation can be enabled or disabled as required. When the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state. The watchdog timer is disabled by default out of reset.
PAGE 1155
Tiva™ TM4C129ENCPDT Microcontroller Note that the Watchdog Timer module clock must be enabled before the registers can be programmed (see page 386). Table 17-1. Watchdog Timers Register Map Description See page 0xFFFF.FFFF Watchdog Load 1156 RO 0xFFFF.FFFF Watchdog Value 1157 WDTCTL RW 0x0000.0000 (WDT0) 0x8000.0000 (WDT1) Watchdog Control 1158 0x00C WDTICR WO - Watchdog Interrupt Clear 1160 0x010 WDTRIS RO 0x0000.0000 Watchdog Raw Interrupt Status 1161 0x014 WDTMIS RO 0x0000.
PAGE 1156
Watchdog Timers Register 1: Watchdog Load (WDTLOAD), offset 0x000 This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter restarts counting down from the new value. If the WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated. Watchdog Load (WDTLOAD) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x000 Type RW, reset 0xFFFF.
PAGE 1157
Tiva™ TM4C129ENCPDT Microcontroller Register 2: Watchdog Value (WDTVALUE), offset 0x004 This register contains the current count value of the timer. Watchdog Value (WDTVALUE) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x004 Type RO, reset 0xFFFF.
PAGE 1158
Watchdog Timers Register 3: Watchdog Control (WDTCTL), offset 0x008 This register is the watchdog control register. The watchdog timer can be configured to generate a reset signal (on second time-out) or an interrupt on time-out. When the watchdog interrupt has been enabled by setting the INTEN bit, all subsequent writes to the INTEN bit are ignored.
PAGE 1159
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 2 INTTYPE RW 0 Description Watchdog Interrupt Type The INTTYPE values are defined as follows: Value Description 1 RESEN RW 0 0 Watchdog interrupt is a standard interrupt. 1 Watchdog interrupt is a non-maskable interrupt. Watchdog Reset Enable The RESEN values are defined as follows: Value Description 0 Disabled. 1 Enable the Watchdog module reset output. Setting this bit enables the Watchdog Timer.
PAGE 1160
Watchdog Timers Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C This register is the interrupt clear register. A write of any value to this register clears the Watchdog interrupt and reloads the 32-bit counter from the WDTLOAD register. Write to this register when a watchdog time-out interrupt has occurred to properly service the Watchdog. Value for a read or reset is indeterminate.
PAGE 1161
Tiva™ TM4C129ENCPDT Microcontroller Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 This register is the raw interrupt status register. Watchdog interrupt events can be monitored via this register if the controller interrupt is masked. Watchdog Raw Interrupt Status (WDTRIS) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x010 Type RO, reset 0x0000.
PAGE 1162
Watchdog Timers Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the Watchdog interrupt enable bit. Watchdog Masked Interrupt Status (WDTMIS) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x014 Type RO, reset 0x0000.
PAGE 1163
Tiva™ TM4C129ENCPDT Microcontroller Register 7: Watchdog Test (WDTTEST), offset 0x418 This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag during debug. Watchdog Test (WDTTEST) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x418 Type RW, reset 0x0000.
PAGE 1164
Watchdog Timers Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing any other value to the WDTLOCK register re-enables the locked state for register writes to all the other registers, except for the Watchdog Test (WDTTEST) register. Reading the WDTLOCK register returns the lock status rather than the 32-bit value written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns 0x0000.
PAGE 1165
Tiva™ TM4C129ENCPDT Microcontroller Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 4 (WDTPeriphID4) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFD0 Type RO, reset 0x0000.
PAGE 1166
Watchdog Timers Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 5 (WDTPeriphID5) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFD4 Type RO, reset 0x0000.
PAGE 1167
Tiva™ TM4C129ENCPDT Microcontroller Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 6 (WDTPeriphID6) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFD8 Type RO, reset 0x0000.
PAGE 1168
Watchdog Timers Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 7 (WDTPeriphID7) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFDC Type RO, reset 0x0000.
PAGE 1169
Tiva™ TM4C129ENCPDT Microcontroller Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 0 (WDTPeriphID0) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFE0 Type RO, reset 0x0000.
PAGE 1170
Watchdog Timers Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 1 (WDTPeriphID1) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFE4 Type RO, reset 0x0000.
PAGE 1171
Tiva™ TM4C129ENCPDT Microcontroller Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 2 (WDTPeriphID2) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFE8 Type RO, reset 0x0000.
PAGE 1172
Watchdog Timers Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 3 (WDTPeriphID3) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFEC Type RO, reset 0x0000.
PAGE 1173
Tiva™ TM4C129ENCPDT Microcontroller Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 0 (WDTPCellID0) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFF0 Type RO, reset 0x0000.
PAGE 1174
Watchdog Timers Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 1 (WDTPCellID1) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFF4 Type RO, reset 0x0000.
PAGE 1175
Tiva™ TM4C129ENCPDT Microcontroller Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 2 (WDTPCellID2) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFF8 Type RO, reset 0x0000.
PAGE 1176
Watchdog Timers Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 3 (WDTPCellID3) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFFC Type RO, reset 0x0000.
PAGE 1177
Tiva™ TM4C129ENCPDT Microcontroller 18 Analog-to-Digital Converter (ADC) An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. Two identical converter modules are included, which share 20 input channels. The TM4C129ENCPDT ADC module features 12-bit conversion resolution and supports 20 input channels, plus an internal temperature sensor.
PAGE 1178
Analog-to-Digital Converter (ADC) ■ Converter uses signals VREFA+ and GNDA as the voltage reference ■ Power and ground for the analog circuitry is separate from the digital power and ground ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Dedicated channel for each sample sequencer – ADC module uses burst requests for DMA ■ Global Alternate Clock (ALTCLK) resource or System Clock (SYSCLK) can be used to generate ADC clock 18.
PAGE 1179
Tiva™ TM4C129ENCPDT Microcontroller Figure 18-2.
PAGE 1180
Analog-to-Digital Converter (ADC) Table 18-1. ADC Signals (128TQFP) (continued) Pin Name Pin Number Pin Mux / Pin Assignment Pin Type Buffer Type Description AIN8 124 PE5 I Analog Analog-to-digital converter input 8. AIN9 123 PE4 I Analog Analog-to-digital converter input 9. AIN10 121 PB4 I Analog Analog-to-digital converter input 10. AIN11 120 PB5 I Analog Analog-to-digital converter input 11. AIN12 4 PD3 I Analog Analog-to-digital converter input 12.
PAGE 1181
Tiva™ TM4C129ENCPDT Microcontroller For a given sample sequence, each sample is defined by bit fields in the ADC Sample Sequence Input Multiplexer Select (ADCSSMUXn), ADC Sample Sequence Extended Input Multiplexer Select (ADCSSEMUXn) and ADC Sample Sequence Control (ADCSSCTLn) registers, where "n" corresponds to the sequence number.
PAGE 1182
Analog-to-Digital Converter (ADC) signals; and the ADC Interrupt Status and Clear (ADCISC) register, which shows active interrupts that are enabled by the ADCIM register. Sequencer interrupts are cleared by writing a 1 to the corresponding IN bit in ADCISC. Digital comparator interrupts are cleared by writing a 1 to the ADC Digital Comparator Interrupt Status and Clear (ADCDCISC) register. 18.3.2.
PAGE 1183
Tiva™ TM4C129ENCPDT Microcontroller Table 18-3.
PAGE 1184
Analog-to-Digital Converter (ADC) 18.3.2.6 Sample Phase Control The trigger source for ADC0 and ADC1 may be independent or the two ADC modules may operate from the same trigger source and operate on the same or different inputs. If the converters are running at the same sample rate, they may be configured to start the conversions coincidentally or one ADC may be programmed to lag up to 15 clock cycles relative to the other ADC.
PAGE 1185
Tiva™ TM4C129ENCPDT Microcontroller – ADC Module 1, ADCSPC = 0x0, sampling AIN1 Note: If two ADCs are configured to sample the same signal, a skew (phase lag) must be added to one of the ADC modules to prevent coincident sampling. Phase lag can be added by programming the PHASE field in the ADCSPC register. ■ Skewed sampling of the same signal. The skew is determined by both the TSHn field in the ADCSSTSHn registers and the PHASE field in the ADCSPC register.
PAGE 1186
Analog-to-Digital Converter (ADC) ■ 16 MHz PIOSC. Using the PIOSC provides a conversion rate near 1 Msps. To use the PIOSC to clock the ADC, first power up the PLL and then enable the PIOSC in the CS bit field in the ADCCC register, then disable the PLL. ■ MOSC. The MOSC clock source must be 16 MHz for a 1 Msps conversion rate and 32 MHz for a 2 Msps conversion rate. The system clock must be at the same frequency or higher than the ADC clock.
PAGE 1187
Tiva™ TM4C129ENCPDT Microcontroller Figure 18-6. Sample Averaging Example A+B+C+D 4 A+B+C+D 4 INT 18.3.4 Analog-to-Digital Converter The Analog-to-Digital Converter (ADC) module uses a Successive Approximation Register (SAR) architecture to deliver a 12-bit, low-power, high-precision conversion value. The successive approximation uses a switched capacitor array to perform the dual functions of sampling and holding the signal as well as providing the 12-bit DAC operation.
PAGE 1188
Analog-to-Digital Converter (ADC) Figure 18-7. ADC Input Equivalency Tiva™ Microcontroller VDD Zs Rs VS Input PAD Equivalent Circuit ZADC RADC Pin Cs VADCIN ESD Clamp 12-bit SAR ADC Converter 12-bit Word IL Pin Input PAD Equivalent Circuit Pin Input PAD Equivalent Circuit RADC RADC CADC The ADC operates from both the 3.3-V analog and 1.2-V digital power supplies.
PAGE 1189
Tiva™ TM4C129ENCPDT Microcontroller The range of this conversion value is from 0x000 to 0xFFF. In single-ended-input mode, the 0x000 value corresponds to the voltage level on VREFN; the 0xFFF value corresponds to the voltage level on VREFP.
PAGE 1190
Analog-to-Digital Converter (ADC) pair 1 samples analog inputs 2 and 3; and so on (see Table 18-6 on page 1190). The ADC does not support other differential pairings such as analog input 0 with analog input 3. Table 18-6.
PAGE 1191
Tiva™ TM4C129ENCPDT Microcontroller ■ In order to take advantage of the maximum possible differential input swing, VINCM should be very close to VREFCM, see Table 30-44 on page 1985. If VINCM is not equal to VREFCM, the differential input signal may clip at either maximum or minimum voltage, because either single ended input can never be larger than VREFP or smaller than VREFN, and it is not possible to achieve full swing.
PAGE 1192
Analog-to-Digital Converter (ADC) Figure 18-11. Internal Temperature Sensor Characteristic VTSENS VTSENS = 2.7 V – (TEMP+55) 75 2.5 V 1.633 V 0.833 V -40° C 25° C 85° C Temp The temperature sensor reading can be sampled in a sample sequence by setting the TSn bit in the ADCSSCTLn register. The sample and hold width should be configured for at least 16 ADC clocks using the ADCSSTSHn register. The temperature reading from the temperature sensor can also be given as a function of the ADC value.
PAGE 1193
Tiva™ TM4C129ENCPDT Microcontroller data is used by each function to determine if the right conditions have been met to assert the associated output. Interrupts The digital comparator interrupt function is enabled by setting the CIE bit in the ADC Digital Comparator Control (ADCDCCTLn) register. This bit enables the interrupt function state machine to start monitoring the incoming ADC conversions.
PAGE 1194
Analog-to-Digital Converter (ADC) Hysteresis-Once Mode The Hysteresis-Once operational mode can only be used in conjunction with the low-band or high-band regions because the mid-band region must be crossed and the opposite region entered to clear the hysteresis condition.
PAGE 1195
Tiva™ TM4C129ENCPDT Microcontroller Mid-Band Operation To operate in the mid-band region, the CIC field or the CTC field in the ADCDCCTLn register must be programmed to 0x1. This setting causes interrupts or triggers to be generated in the mid-band region according the operation mode. Only the Always and Once operational modes are available in the mid-band region.
PAGE 1196
Analog-to-Digital Converter (ADC) Figure 18-14. High-Band Operation (CIC=0x3 and/or CTC=0x3) COMP1 COMP0 Always – 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 Once – 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 Hysteresis Always – 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 Hysteresis Once – 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 18.4 Initialization and Configuration 18.4.
PAGE 1197
Tiva™ TM4C129ENCPDT Microcontroller 18.4.2 Sample Sequencer Configuration Configuration of the sample sequencers is slightly more complex than the module initialization because each sample sequencer is completely programmable. The configuration for each sample sequencer should be as follows: 1. Ensure that the sample sequencer is disabled by clearing the corresponding ASENn bit in the ADCACTSS register. Programming of the sample sequencers is allowed without having them enabled.
PAGE 1198
Analog-to-Digital Converter (ADC) Table 18-7. ADC Register Map (continued) Description See page 0x0000.0000 ADC Underflow Status 1220 RW 0x0000.0000 ADC Trigger Source Select 1221 ADCSSPRI RW 0x0000.3210 ADC Sample Sequencer Priority 1223 0x024 ADCSPC RW 0x0000.0000 ADC Sample Phase Control 1225 0x028 ADCPSSI RW - ADC Processor Sample Sequence Initiate 1227 0x030 ADCSAC RW 0x0000.0000 ADC Sample Averaging Control 1229 0x034 ADCDCISC RW1C 0x0000.
PAGE 1199
Tiva™ TM4C129ENCPDT Microcontroller Table 18-7. ADC Register Map (continued) Description See page 0x0000.0000 ADC Sample Sequence Extended Input Multiplexer Select 2 1261 RW 0x0000.0000 ADC Sample Sequence 2 Sample and Hold Time 1263 ADCSSMUX3 RW 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 3 1265 0x0A4 ADCSSCTL3 RW 0x0000.0000 ADC Sample Sequence Control 3 1266 0x0A8 ADCSSFIFO3 RO - ADC Sample Sequence Result FIFO 3 1242 0x0AC ADCSSFSTAT3 RO 0x0000.
PAGE 1200
Analog-to-Digital Converter (ADC) 18.6 Register Descriptions The remainder of this section lists and describes the ADC registers, in numerical order by address offset.
PAGE 1201
Tiva™ TM4C129ENCPDT Microcontroller Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 This register controls the activation of the sample sequencers. Each sample sequencer can be enabled or disabled independently. ADC Active Sample Sequencer (ADCACTSS) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x000 Type RW, reset 0x0000.
PAGE 1202
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 9 ADEN1 RW 0 Description ADC SS1 DMA Enable Value Description 8 ADEN0 RW 0 0 DMA for Sample Sequencer 1 is disabled. 1 DMA for Sample Sequencer 1 is enabled. ADC SS1 DMA Enable Value Description 0 DMA for Sample Sequencer 1 is disabled. 1 DMA for Sample Sequencer 1 is enabled. 7:4 reserved RO 0 Software should not rely on the value of a reserved bit.
PAGE 1203
Tiva™ TM4C129ENCPDT Microcontroller Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 This register shows the status of the raw interrupt signal of each sample sequencer. These bits may be polled by software to look for interrupt conditions without sending the interrupts to the interrupt controller. ADC Raw Interrupt Status (ADCRIS) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x004 Type RO, reset 0x0000.
PAGE 1204
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 9 DMAINR1 RO 0 Description SS1 DMA Raw Interrupt Status Value Description 0 The DMA interrupt has not occurred. 1 The sample sequence 1 DMA interrupt is asserted. This bit is cleared by writing a 1 to the DMAINR1 bit in the ADCISC register. 8 DMAINR0 RO 0 SS0 DMA Raw Interrupt Status Value Description 0 The DMA interrupt has not occurred. 1 The sample sequence 0 DMA interrupt is asserted.
PAGE 1205
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 0 INR0 RO 0 Description SS0 Raw Interrupt Status Value Description 0 An interrupt has not occurred. 1 A sample has completed conversion and the respective ADCSSCTL0 IEn bit is set, enabling a raw interrupt. This bit is cleared by writing a 1 to the IN0 bit in the ADCISC register.
PAGE 1206
Analog-to-Digital Converter (ADC) Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 This register controls whether the sample sequencer and digital comparator raw interrupt signals are sent to the interrupt controller. Each raw interrupt signal can be masked independently.
PAGE 1207
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 17 DCONSS1 RW 0 Description Digital Comparator Interrupt on SS1 Value Description 16 DCONSS0 RW 0 0 The status of the digital comparators does not affect the SS1 interrupt status. 1 The raw interrupt signal from the digital comparators (INRDC bit in the ADCRIS register) is sent to the interrupt controller on the SS1 interrupt line.
PAGE 1208
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 8 DMAMASK0 RW 0 Description SS0 DMA Interrupt Mask Value Description 0 The status of Sample Sequencer 0 DMA does not affect the SS0 interrupt status. 1 The raw interrupt signal from Sample Sequencer 0 DMA (ADCRIS register DMAINR0 bit) is sent to the interrupt controller. 7:4 reserved RO 0 Software should not rely on the value of a reserved bit.
PAGE 1209
Tiva™ TM4C129ENCPDT Microcontroller Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C This register provides the mechanism for clearing sample sequencer interrupt conditions and shows the status of interrupts generated by the sample sequencers and the digital comparators which have been sent to the interrupt controller. When read, each bit field is the logical AND of the respective INR and MASK bits. Sample sequencer interrupts are cleared by writing a 1 to the corresponding bit position.
PAGE 1210
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 17 DCINSS1 RO 0 Description Digital Comparator Interrupt Status on SS1 Value Description 0 No interrupt has occurred or the interrupt is masked. 1 Both the INRDC bit in the ADCRIS register and the DCONSS1 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. This bit is cleared by writing a 1 to it. Clearing this bit also clears the INRDC bit in the ADCRIS register.
PAGE 1211
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 9 DMAIN1 RW1C 0 Description SS1 DMA Interrupt Status and Clear Value Description 0 No interrupt has occurred or the interrupt is masked. 1 Both the DMAINR1 bit in the ADCRIS register and the DMAMASK1 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. This bit is cleared by writing a 1. Clearing this bit also clears the DMAINR1 bit in the ADCRIS register.
PAGE 1212
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 1 IN1 RW1C 0 Description SS1 Interrupt Status and Clear Value Description 0 No interrupt has occurred or the interrupt is masked. 1 Both the INR1 bit in the ADCRIS register and the MASK1 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. This bit is cleared by writing a 1. Clearing this bit also clears the INR1 bit in the ADCRIS register.
PAGE 1213
Tiva™ TM4C129ENCPDT Microcontroller Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 This register indicates overflow conditions in the sample sequencer FIFOs. Once the overflow condition has been handled by software, the condition can be cleared by writing a 1 to the corresponding bit position. ADC Overflow Status (ADCOSTAT) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x010 Type RW1C, reset 0x0000.
PAGE 1214
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 0 OV0 RW1C 0 Description SS0 FIFO Overflow Value Description 0 The FIFO has not overflowed. 1 The FIFO for Sample Sequencer 0 has hit an overflow condition, meaning that the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped. This bit is cleared by writing a 1.
PAGE 1215
Tiva™ TM4C129ENCPDT Microcontroller Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 The ADCEMUX selects the event (trigger) that initiates sampling for each sample sequencer. Each sample sequencer can be configured with a unique trigger source. ADC Event Multiplexer Select (ADCEMUX) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x014 Type RW, reset 0x0000.
PAGE 1216
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 15:12 EM3 RW 0x0 Description SS3 Trigger Select This field selects the trigger source for Sample Sequencer 3. The valid configurations for this field are: Value Event 0x0 Processor (default) The trigger is initiated by setting the SSn bit in the ADCPSSI register. 0x1 Analog Comparator 0 This trigger is configured by the Analog Comparator Control 0 (ACCTL0) register (page 1789).
PAGE 1217
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 11:8 EM2 RW 0x0 Description SS2 Trigger Select This field selects the trigger source for Sample Sequencer 2. The valid configurations for this field are: Value Event 0x0 Processor (default) The trigger is initiated by setting the SSn bit in the ADCPSSI register. 0x1 Analog Comparator 0 This trigger is configured by the Analog Comparator Control 0 (ACCTL0) register (page 1789).
PAGE 1218
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 7:4 EM1 RW 0x0 Description SS1 Trigger Select This field selects the trigger source for Sample Sequencer 1. The valid configurations for this field are: Value Event 0x0 Processor (default) The trigger is initiated by setting the SSn bit in the ADCPSSI register. 0x1 Analog Comparator 0 This trigger is configured by the Analog Comparator Control 0 (ACCTL0) register (page 1789).
PAGE 1219
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3:0 EM0 RW 0x0 Description SS0 Trigger Select This field selects the trigger source for Sample Sequencer 0 The valid configurations for this field are: Value Event 0x0 Processor (default) The trigger is initiated by setting the SSn bit in the ADCPSSI register. 0x1 Analog Comparator 0 This trigger is configured by the Analog Comparator Control 0 (ACCTL0) register (page 1789).
PAGE 1220
Analog-to-Digital Converter (ADC) Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 This register indicates underflow conditions in the sample sequencer FIFOs. The corresponding underflow condition is cleared by writing a 1 to the relevant bit position. ADC Underflow Status (ADCUSTAT) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x018 Type RW1C, reset 0x0000.
PAGE 1221
Tiva™ TM4C129ENCPDT Microcontroller Register 8: ADC Trigger Source Select (ADCTSSEL), offset 0x01C If a PWM Generator n is selected as a trigger source through the EMn bit field in the ADC Event Multiplexer Select (ADCEMUX) register, the ADCTSSEL register is programmed to identify in which PWM module instance the generator creating the trigger is located. The register resets to 0x0000.0000, which selects PWM module 0 for all generators.
PAGE 1222
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 13:12 PS1 RW 0x0 Description Generator 1 PWM Module Trigger Select This field selects in which PWM module the Generator 1 trigger is located. Value Description 0x0 Use Generator 1 (and its trigger) in PWM module 0 0x1-0x3 reserved 11:6 reserved RO 0x0 Software should not rely on the value of a reserved bit.
PAGE 1223
Tiva™ TM4C129ENCPDT Microcontroller Register 9: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 This register sets the priority for each of the sample sequencers. Out of reset, Sequencer 0 has the highest priority, and Sequencer 3 has the lowest priority. When reconfiguring sequence priorities, each sequence must have a unique priority for the ADC to operate properly. ADC Sample Sequencer Priority (ADCSSPRI) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x020 Type RW, reset 0x0000.
PAGE 1224
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset Description 1:0 SS0 RW 0x0 SS0 Priority This field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 0. A priority encoding of 0x0 is highest and 0x3 is lowest. The priorities assigned to the sequencers must be uniquely mapped. The ADC may not operate properly if two or more fields are equal.
PAGE 1225
Tiva™ TM4C129ENCPDT Microcontroller Register 10: ADC Sample Phase Control (ADCSPC), offset 0x024 The ADC Sample Phase Control (ADCSPC) register is used to insert a delay in ADC module sampling. This feature can be used with the SYNCWAIT and GSYNC bit in the ADCPSSI register to provide concurrent sampling of two different signals by two different ADC modules or skewed sampling of two ADC modules to increase the effective sampling rate.
PAGE 1226
Analog-to-Digital Converter (ADC) ADC Sample Phase Control (ADCSPC) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x024 Type RW, reset 0x0000.
PAGE 1227
Tiva™ TM4C129ENCPDT Microcontroller Register 11: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 This register provides a mechanism for application software to initiate sampling in the sample sequencers. Sample sequences can be initiated individually or in any combination. When multiple sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution order. This register also provides a means to configure and then initiate concurrent sampling on all ADC modules.
PAGE 1228
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset Description 3 SS3 WO - SS3 Initiate Value Description 0 No effect. 1 Begin sampling on Sample Sequencer 3, if the sequencer is enabled in the ADCACTSS register. Only a write by software is valid; a read of this register returns no meaningful data. 2 SS2 WO - SS2 Initiate Value Description 0 No effect. 1 Begin sampling on Sample Sequencer 2, if the sequencer is enabled in the ADCACTSS register.
PAGE 1229
Tiva™ TM4C129ENCPDT Microcontroller Register 12: ADC Sample Averaging Control (ADCSAC), offset 0x030 This register controls the amount of hardware averaging applied to conversion results. The final conversion result stored in the FIFO is averaged from 2 AVG consecutive ADC samples at the specified ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6, then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO.
PAGE 1230
Analog-to-Digital Converter (ADC) Register 13: ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 This register provides status and acknowledgement of digital comparator interrupts. One bit is provided for each comparator. ADC Digital Comparator Interrupt Status and Clear (ADCDCISC) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x034 Type RW1C, reset 0x0000.
PAGE 1231
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 DCINT4 RW1C 0 Description Digital Comparator 4 Interrupt Status and Clear Value Description 0 No interrupt. 1 Digital Comparator 4 has generated an interrupt. This bit is cleared by writing a 1. 3 DCINT3 RW1C 0 Digital Comparator 3 Interrupt Status and Clear Value Description 0 No interrupt. 1 Digital Comparator 3 has generated an interrupt. This bit is cleared by writing a 1.
PAGE 1232
Analog-to-Digital Converter (ADC) Register 14: ADC Control (ADCCTL), offset 0x038 This register configures the voltage reference. The voltage references for the conversion can be VREFA+ and GNDA or VDDA and GNDA. Note that values set in this register apply to all ADC modules, it is not possible to set one module to use internal references and another to use external references. ADC Control (ADCCTL) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x038 Type RW, reset 0x0000.
PAGE 1233
Tiva™ TM4C129ENCPDT Microcontroller Register 15: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 This register, along with the ADCSSEMUX0 register, defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 0. If the corresponding EMUXn bit in the ADCSSEMUX0 register is set, the MUXn field in this register selects from AIN[19:16]. When the corresponding EMUXn bit is clear, the MUXn field selects from AIN[15:0].
PAGE 1234
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 15:12 MUX3 RW 0x0 Description 4th Sample Input Select The MUX3 field is used during the fourth sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 11:8 MUX2 RW 0x0 3rd Sample Input Select The MUX2 field is used during the third sample of a sequence executed with the sample sequencer.
PAGE 1235
Tiva™ TM4C129ENCPDT Microcontroller Register 16: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 This register contains the configuration information for each sample for a sequence executed with a sample sequencer. When configuring a sample sequence, the END bit must be set for the final sample, whether it be after the first sample, eighth sample, or any sample in between. This register is 32 bits wide and contains information for eight possible samples.
PAGE 1236
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 28 D7 RW 0 Description 8th Sample Differential Input Select Value Description 0 The analog inputs are not differentially sampled. 1 The analog input is differentially sampled. The corresponding ADCSSMUXn nibble must be set to the pair number "i", where the paired inputs are "2i and 2i+1". Because the temperature sensor does not have a differential option, this bit must not be set when the TS7 bit is set.
PAGE 1237
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 23 TS5 RW 0 Description 6th Sample Temp Sensor Select Value Description 22 IE5 RW 0 0 The input pin specified by the ADCSSMUXn register is read during the sixth sample of the sample sequence. 1 The temperature sensor is read during the sixth sample of the sample sequence. 6th Sample Interrupt Enable Value Description 0 The raw interrupt is not asserted to the interrupt controller.
PAGE 1238
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 18 IE4 RW 0 Description 5th Sample Interrupt Enable Value Description 0 The raw interrupt is not asserted to the interrupt controller. 1 The raw interrupt signal (INR0 bit) is asserted at the end of the fifth sample's conversion. If the MASK0 bit in the ADCIM register is set, the interrupt is promoted to the interrupt controller. It is legal to have multiple samples within a sequence generate interrupts.
PAGE 1239
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 13 END3 RW 0 Description 4th Sample is End of Sequence Value Description 0 Another sample in the sequence is the final sample. 1 The fourth sample is the last sample of the sequence. It is possible to end the sequence on any sample position. Software must set an ENDn bit somewhere within the sequence. Samples defined after the sample containing a set ENDn bit are not requested for conversion even though the fields may be non-zero.
PAGE 1240
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 8 D2 RW 0 Description 3rd Sample Differential Input Select Value Description 0 The analog inputs are not differentially sampled. 1 The analog input is differentially sampled. The corresponding ADCSSMUXn nibble must be set to the pair number "i", where the paired inputs are "2i and 2i+1". Because the temperature sensor does not have a differential option, this bit must not be set when the TS2 bit is set.
PAGE 1241
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3 TS0 RW 0 Description 1st Sample Temp Sensor Select Value Description 2 IE0 RW 0 0 The input pin specified by the ADCSSMUXn register is read during the first sample of the sample sequence. 1 The temperature sensor is read during the first sample of the sample sequence. 1st Sample Interrupt Enable Value Description 0 The raw interrupt is not asserted to the interrupt controller.
PAGE 1242
Analog-to-Digital Converter (ADC) Register 17: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 Register 18: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 Register 19: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 Register 20: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 Important: This register is read-sensitive. See the register description for details.
PAGE 1243
Tiva™ TM4C129ENCPDT Microcontroller Register 21: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C Register 22: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C Register 23: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C Register 24: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC This register provides a window into the sample sequencer, providing full/empty status information as well as the positions of the head and tail pointers.
PAGE 1244
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 7:4 HPTR RO 0x0 Description FIFO Head Pointer This field contains the current "head" pointer index for the FIFO, that is, the next entry to be written. Valid values are 0x0-0x7 for FIFO0; 0x0-0x3 for FIFO1 and FIFO2; and 0x0 for FIFO3. 3:0 TPTR RO 0x0 FIFO Tail Pointer This field contains the current "tail" pointer index for the FIFO, that is, the next entry to be read.
PAGE 1245
Tiva™ TM4C129ENCPDT Microcontroller Register 25: ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 This register determines whether the sample from the given conversion on Sample Sequence 0 is saved in the Sample Sequence FIFO0 or sent to the digital comparator unit. ADC Sample Sequence 0 Operation (ADCSSOP0) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x050 Type RW, reset 0x0000.
PAGE 1246
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 12 S3DCOP RW 0 Description Sample 3 Digital Comparator Operation Same definition as S7DCOP but used during the fourth sample. 11:9 reserved RO 0x0 8 S2DCOP RW 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
PAGE 1247
Tiva™ TM4C129ENCPDT Microcontroller Register 26: ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 This register determines which digital comparator receives the sample from the given conversion on Sample Sequence 0, if the corresponding SnDCOP bit in the ADCSSOP0 register is set. ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x054 Type RW, reset 0x0000.
PAGE 1248
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 11:8 S2DCSEL RW 0x0 Description Sample 2 Digital Comparator Select This field has the same encodings as S7DCSEL but is used during the third sample. 7:4 S1DCSEL RW 0x0 Sample 1 Digital Comparator Select This field has the same encodings as S7DCSEL but is used during the second sample. 3:0 S0DCSEL RW 0x0 Sample 0 Digital Comparator Select This field has the same encodings as S7DCSEL but is used during the first sample.
PAGE 1249
Tiva™ TM4C129ENCPDT Microcontroller Register 27: ADC Sample Sequence Extended Input Multiplexer Select 0 (ADCSSEMUX0), offset 0x058 This register, along with the ADCSSMUX0 register, defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 0. If a bit in this register is set, the corresponding MUXn field in the ADCSSMUX0 register selects from AIN[19:16]. When a bit in this register is clear, the corresponding MUXn field selects from AIN[15:0].
PAGE 1250
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 20 EMUX5 RW 0x0 Description 6th Sample Input Select (Upper Bit) The EMUX5 field is used during the sixth sample of a sequence executed with the sample sequencer. This bit has the same description as EMUX7. 19:17 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
PAGE 1251
Tiva™ TM4C129ENCPDT Microcontroller Register 28: ADC Sample Sequence 0 Sample and Hold Time (ADCSSTSH0), offset 0x05C This register controls the sample period size for each sample of sequencer 0. Each sample and hold period select specifies the time allocated to the sample and hold circuit as shown by the encodings in Table 18-3 on page 1182. Note: If sampling the internal temperature sensor, the sample and hold width should be at least 16 ADC clocks (TSHn = 0x4). Table 18-8.
PAGE 1252
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 23:20 TSH5 RW 0x0 Description 6th Sample and Hold Period Select The TSH5 field is used during the sixth sample of a sequence executed with the sample sequencer. 19:16 TSH4 RW 0x0 5th Sample and Hold Period Select The TSH4 field is used during the fifth sample of a sequence executed with the sample sequencer.
PAGE 1253
Tiva™ TM4C129ENCPDT Microcontroller Register 29: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 Register 30: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 This register, along with the ADCSSEMUX1 or ADCSSEMUX2 register, defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 1 or 2.
PAGE 1254
Analog-to-Digital Converter (ADC) Register 31: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 Register 32: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 These registers contain the configuration information for each sample for a sequence executed with Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set for the final sample, whether it be after the first sample, fourth sample, or any sample in between.
PAGE 1255
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 13 END3 RW 0 Description 4th Sample is End of Sequence Value Description 0 Another sample in the sequence is the final sample. 1 The fourth sample is the last sample of the sequence. It is possible to end the sequence on any sample position. Software must set an ENDn bit somewhere within the sequence. Samples defined after the sample containing a set ENDn bit are not requested for conversion even though the fields may be non-zero.
PAGE 1256
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 8 D2 RW 0 Description 3rd Sample Differential Input Select Value Description 0 The analog inputs are not differentially sampled. 1 The analog input is differentially sampled. The corresponding ADCSSMUXn nibble must be set to the pair number "i", where the paired inputs are "2i and 2i+1". Because the temperature sensor does not have a differential option, this bit must not be set when the TS2 bit is set.
PAGE 1257
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3 TS0 RW 0 Description 1st Sample Temp Sensor Select Value Description 2 IE0 RW 0 0 The input pin specified by the ADCSSMUXn register is read during the first sample of the sample sequence. 1 The temperature sensor is read during the first sample of the sample sequence. 1st Sample Interrupt Enable Value Description 0 The raw interrupt is not asserted to the interrupt controller.
PAGE 1258
Analog-to-Digital Converter (ADC) Register 33: ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 Register 34: ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 This register determines whether the sample from the given conversion on Sample Sequence n is saved in the Sample Sequence n FIFO or sent to the digital comparator unit. The ADCSSOP1 register controls Sample Sequencer 1 and the ADCSSOP2 register controls Sample Sequencer 2. ADC Sample Sequence n Operation (ADCSSOPn) ADC0 base: 0x4003.
PAGE 1259
Tiva™ TM4C129ENCPDT Microcontroller Register 35: ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 Register 36: ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 These registers determine which digital comparator receives the sample from the given conversion on Sample Sequence n if the corresponding SnDCOP bit in the ADCSSOPn register is set.
PAGE 1260
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 7:4 S1DCSEL RW 0x0 Description Sample 1 Digital Comparator Select This field has the same encodings as S3DCSEL but is used during the second sample. 3:0 S0DCSEL RW 0x0 Sample 0 Digital Comparator Select This field has the same encodings as S3DCSEL but is used during the first sample.
PAGE 1261
Tiva™ TM4C129ENCPDT Microcontroller Register 37: ADC Sample Sequence Extended Input Multiplexer Select 1 (ADCSSEMUX1), offset 0x078 Register 38: ADC Sample Sequence Extended Input Multiplexer Select 2 (ADCSSEMUX2), offset 0x098 This register, along with the ADCSSMUX1 or ADCSSMUX2 register, defines the analog input configuration for each sample in a sequence executed with either Sample Sequencer 1 or 2.
PAGE 1262
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 8 EMUX2 RW 0x0 Description 3rd Sample Input Select (Upper Bit) The EMUX2 field is used during the third sample of a sequence executed with the sample sequencer. This bit has the same description as EMUX3. 7:5 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
PAGE 1263
Tiva™ TM4C129ENCPDT Microcontroller Register 39: ADC Sample Sequence 1 Sample and Hold Time (ADCSSTSH1), offset 0x07C Register 40: ADC Sample Sequence 2 Sample and Hold Time (ADCSSTSH2), offset 0x09C These registers control the sample period size for each sample step of sequencer 1 and sequencer 2. Each sample and hold period select specifies the time allocated to the sample and hold circuit as shown by the encodings in Table 18-3 on page 1182.
PAGE 1264
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 15:12 TSH3 RW 0x0 Description 4th Sample and Hold Period Select The TSH3 field is used during the fourth sample of a sequence executed with the sample sequencer. 11:8 TSH2 RW 0x0 3rd Sample and Hold Period Select The TSH2 field is used during the third sample of a sequence executed with the sample sequencer.
PAGE 1265
Tiva™ TM4C129ENCPDT Microcontroller Register 41: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 This register, along with the ADCSSEMUX3 register, defines the analog input configuration for the sample in a sequence executed with Sample Sequencer 3. If the EMUX0 bit in the ADCSSEMUX3 register is set, the MUX0 field in this register selects from AIN[19:16]. When the EMUX0 bit is clear, the MUX0 field selects from AIN[15:0].
PAGE 1266
Analog-to-Digital Converter (ADC) Register 42: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 This register contains the configuration information for a sample executed with Sample Sequencer 3. This register is 4 bits wide and contains information for one possible sample. See the ADCSSCTL0 register on page 1235 for detailed bit descriptions. Note: When configuring a sample sequence in this register, the END0 bit must be set. ADC Sample Sequence Control 3 (ADCSSCTL3) ADC0 base: 0x4003.
PAGE 1267
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 0 D0 RW 0 Description Sample Differential Input Select Value Description 0 The analog inputs are not differentially sampled. 1 The analog input is differentially sampled. The corresponding ADCSSMUXn nibble must be set to the pair number "i", where the paired inputs are "2i and 2i+1". Because the temperature sensor does not have a differential option, this bit must not be set when the TS0 bit is set.
PAGE 1268
Analog-to-Digital Converter (ADC) Register 43: ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 This register determines whether the sample from the given conversion on Sample Sequence 3 is saved in the Sample Sequence 3 FIFO or sent to the digital comparator unit. ADC Sample Sequence 3 Operation (ADCSSOP3) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x0B0 Type RW, reset 0x0000.
PAGE 1269
Tiva™ TM4C129ENCPDT Microcontroller Register 44: ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 This register determines which digital comparator receives the sample from the given conversion on Sample Sequence 3 if the corresponding SnDCOP bit in the ADCSSOP3 register is set. ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x0B4 Type RW, reset 0x0000.
PAGE 1270
Analog-to-Digital Converter (ADC) Register 45: ADC Sample Sequence Extended Input Multiplexer Select 3 (ADCSSEMUX3), offset 0x0B8 This register, along with the ADCSSMUX3 register, defines the analog input configuration for the sample in a sequence executed with Sample Sequencer 3. If EMUX0 is set, the MUX0 field in the ADCSSMUX3 register selects from AIN[19:16]. When EMUX0 is clear, the MUX0 field selects from AIN[15:0]. This register is 1 bit wide and contains information for one possible sample.
PAGE 1271
Tiva™ TM4C129ENCPDT Microcontroller Register 46: ADC Sample Sequence 3 Sample and Hold Time (ADCSSTSH3), offset 0x0BC This register controls the sample period size for the sample in sequencer 3. The sample and hold period select specifies the time allocated to the sample and hold circuit as shown by the encodings in Table 18-3 on page 1182 Note: If sampling the internal temperature sensor, the sample and hold width should be at least 16 ADC clocks (TSHn = 0x4). Table 18-10.
PAGE 1272
Analog-to-Digital Converter (ADC) Register 47: ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 This register provides the ability to reset any of the digital comparator interrupt or trigger functions back to their initial conditions. Resetting these functions ensures that the data that is being used by the interrupt and trigger functions in the digital comparator unit is not stale. ADC Digital Comparator Reset Initial Conditions (ADCDCRIC) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.
PAGE 1273
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 21 DCTRIG5 WO 0 Description Digital Comparator Trigger 5 Value Description 0 No effect. 1 Resets the Digital Comparator 5 trigger unit to its initial conditions. When the trigger has been cleared, this bit is automatically cleared.
PAGE 1274
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 17 DCTRIG1 WO 0 Description Digital Comparator Trigger 1 Value Description 0 No effect. 1 Resets the Digital Comparator 1 trigger unit to its initial conditions. When the trigger has been cleared, this bit is automatically cleared.
PAGE 1275
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 5 DCINT5 WO 0 Description Digital Comparator Interrupt 5 Value Description 0 No effect. 1 Resets the Digital Comparator 5 interrupt unit to its initial conditions. When the interrupt has been cleared, this bit is automatically cleared.
PAGE 1276
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 1 DCINT1 WO 0 Description Digital Comparator Interrupt 1 Value Description 0 No effect. 1 Resets the Digital Comparator 1 interrupt unit to its initial conditions. When the interrupt has been cleared, this bit is automatically cleared.
PAGE 1277
Tiva™ TM4C129ENCPDT Microcontroller Register 48: ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 Register 49: ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 Register 50: ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 Register 51: ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C Register 52: ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 Register 53: ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 Register 54: ADC Digital Comparator Control
PAGE 1278
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 11:10 CTC RW 0x0 Description Comparison Trigger Condition This field specifies the operational region in which a trigger is generated when the ADC conversion data is compared against the values of COMP0 and COMP1. The COMP0 and COMP1 fields are defined in the ADCDCCMPx registers.
PAGE 1279
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 CIE RW 0 Description Comparison Interrupt Enable Value Description 3:2 CIC RW 0x0 0 Disables the comparison interrupt. ADC conversion data has no effect on interrupt generation. 1 Enables the comparison interrupt. The ADC conversion data is used to determine if an interrupt should be generated according to the programming of the CIC and CIM fields.
PAGE 1280
Analog-to-Digital Converter (ADC) Register 56: ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 Register 57: ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 Register 58: ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 Register 59: ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C Register 60: ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 Register 61: ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 Register 62: ADC Digital Comparator Range 6 (ADCDCCMP6),
PAGE 1281
Tiva™ TM4C129ENCPDT Microcontroller Register 64: ADC Peripheral Properties (ADCPP), offset 0xFC0 The ADCPP register provides information regarding the properties of the ADC module. ADC Peripheral Properties (ADCPP) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0xFC0 Type RO, reset 0x01B0.
PAGE 1282
Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset Description 9:4 CH RO 0x14 ADC Channel Count This field specifies the number of ADC input channels available to the converter. This field is encoded as a binary value, in the range of 0 to 63. This field provides similar information to the legacy DC3 and DC8 register ADCnAINn bits. 3:0 MCR RO 0x7 Maximum Conversion Rate This field specifies the maximum value that may be programmed into the ADCPC register's CR field.
PAGE 1283
Tiva™ TM4C129ENCPDT Microcontroller Register 65: ADC Peripheral Configuration (ADCPC), offset 0xFC4 The ADCPC register provides information regarding the configuration of the peripheral. ADC Peripheral Configuration (ADCPC) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0xFC4 Type RW, reset 0x0000.
PAGE 1284
Analog-to-Digital Converter (ADC) Register 66: ADC Clock Configuration (ADCCC), offset 0xFC8 The ADCCC register controls the clock source for the ADC module. ADC Clock Configuration (ADCCC) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0xFC8 Type RW, reset 0x0000.
PAGE 1285
Tiva™ TM4C129ENCPDT Microcontroller 19 Universal Asynchronous Receivers/Transmitters (UARTs) The TM4C129ENCPDT controller includes eight Universal Asynchronous Receiver/Transmitter (UART) with the following features: ■ Programmable baud-rate generator allowing speeds up to 7.
PAGE 1286
Universal Asynchronous Receivers/Transmitters (UARTs) ■ Standard FIFO-level and End-of-Transmission interrupts ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level – Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level ■ Global Alternate Clock (ALTCLK) resource or System Clock
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Tiva™ TM4C129ENCPDT Microcontroller placements for these UART signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 778) should be set to choose the UART function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 795) to assign the UART signal to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 750. Table 19-1.
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Universal Asynchronous Receivers/Transmitters (UARTs) Table 19-1. UART Signals (128TQFP) (continued) Pin Name Pin Number Pin Mux / Pin Assignment Pin Type Buffer Type Description U3RTS 105 111 PP4 (1) PN4 (2) O TTL UART module 3 Request to Send modem flow control output line. U3Rx 37 116 PA4 (1) PJ0 (1) I TTL UART module 3 receive. U3Tx 38 117 PA5 (1) PJ1 (1) O TTL UART module 3 transmit. U4CTS 21 PK3 (1) I TTL UART module 4 Clear To Send modem flow control input signal.
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Tiva™ TM4C129ENCPDT Microcontroller Figure 19-2. UART Character Frame UnTX LSB 1 5-8 data bits 0 n Parity bit if enabled Start 19.3.2 1-2 stop bits MSB Baud-Rate Generation The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divisor allows the UART to generate all the standard baud rates.
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Universal Asynchronous Receivers/Transmitters (UARTs) 19.3.3 Data Transmission Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit FIFO.
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Tiva™ TM4C129ENCPDT Microcontroller duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but pulses greater than 1.4 μs are accepted as valid pulses. Figure 19-3 on page 1291 shows the UART transmit and receive signals, with and without IrDA modulation. Figure 19-3.
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Universal Asynchronous Receivers/Transmitters (UARTs) 19.3.6 Modem Handshake Support This section describes how to configure and use the modem flow control and status signals for a UART when connected as a DTE (data terminal equipment) or as a DCE (data communications equipment). In general, a modem is a DCE and a computing device that connects to a modem is the DTE. 19.3.6.1 Signaling The status signals provided by a UART differ based on whether the UART is used as a DTE or DCE.
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Tiva™ TM4C129ENCPDT Microcontroller Table 19-2. Flow Control Mode Description CTSEN RTSEN 1 1 RTS and CTS flow control enabled 1 0 Only CTS flow control enabled 0 1 Only RTS flow control enabled 0 0 Both RTS and CTS flow control disabled Note that when RTSEN is 1, software cannot modify the UnRTS output value through the UARTCTL register Request to Send (RTS) bit, and the status of the RTS bit should be ignored.
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Universal Asynchronous Receivers/Transmitters (UARTs) UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits), and the UARTRSR register shows overrun status via the OE bit. If the FIFOs are disabled, the empty and full flags are set according to the status of the 1-byte-deep holding registers. The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO Level Select (UARTIFLS) register (see page 1316).
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Tiva™ TM4C129ENCPDT Microcontroller ■ If the FIFOs are disabled (have a depth of one location) and data is received thereby filling the location, the RXRIS bit is set. The receive interrupt is cleared by performing a single read of the receive FIFO, or by clearing the interrupt by writing a 1 to the RXIC bit. The transmit interrupt changes state when one of the following events occurs: ■ If the FIFOs are enabled and the transmit FIFO progresses through the programmed trigger level, the TXRIS bit is set.
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Universal Asynchronous Receivers/Transmitters (UARTs) 19.4 Initialization and Configuration To enable and initialize the UART, the following steps are necessary: 1. Enable the UART module using the RCGCUART register (see page 395). 2. Enable the clock to the appropriate GPIO module via the RCGCGPIO register (see page 389). To find out which GPIO port to enable, refer to Table 29-5 on page 1932. 3. Set the GPIO AFSEL bits for the appropriate pins (see page 778).
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Tiva™ TM4C129ENCPDT Microcontroller 4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of 0x0000.0060). 5. Configure the UART clock source by writing to the UARTCC register. 6. Optionally, configure the µDMA channel (see “Micro Direct Memory Access (μDMA)” on page 686) and enable the DMA option(s) in the UARTDMACTL register. 7. Enable the UART by setting the UARTEN bit in the UARTCTL register. 19.5 Register Map Table 19-3 on page 1297 lists the UART registers.
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Universal Asynchronous Receivers/Transmitters (UARTs) Table 19-3. UART Register Map (continued) Description See page 0x0000.0000 UART Integer Baud-Rate Divisor 1308 RW 0x0000.0000 UART Fractional Baud-Rate Divisor 1309 UARTLCRH RW 0x0000.0000 UART Line Control 1310 0x030 UARTCTL RW 0x0000.0300 UART Control 1312 0x034 UARTIFLS RW 0x0000.0012 UART Interrupt FIFO Level Select 1316 0x038 UARTIM RW 0x0000.0000 UART Interrupt Mask 1318 0x03C UARTRIS RO 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 1: UART Data (UARTDR), offset 0x000 Important: This register is read-sensitive. See the register description for details. This register is the data register (the interface to the FIFOs). For transmitted data, if the FIFO is enabled, data written to this location is pushed onto the transmit FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
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Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 10 BE RO 0 Description UART Break Error Value Description 0 No break condition has occurred 1 A break condition has been detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO.
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Tiva™ TM4C129ENCPDT Microcontroller Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 The UARTRSR/UARTECR register is the receive status register/error clear register. In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If the status is read from this register, then the status information corresponds to the entry read from UARTDR prior to reading UARTRSR.
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Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 2 BE RO 0 Description UART Break Error Value Description 0 No break condition has occurred 1 A break condition has been detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 31:8 reserved WO 0x0000.00 7:0 DATA WO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Error Clear A write to this register of any data clears the framing, parity, break, and overrun flags.
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Universal Asynchronous Receivers/Transmitters (UARTs) Register 3: UART Flag (UARTFR), offset 0x018 The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and TXFE and RXFE bits are 1.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 7 TXFE RO 1 Description UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. Value Description 0 The transmitter has data to transmit. 1 If the FIFO is disabled (FEN is 0), the transmit holding register is empty. If the FIFO is enabled (FEN is 1), the transmit FIFO is empty.
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Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset Description 3 BUSY RO 0 UART Busy Value Description 0 The UART is not busy. 1 The UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty (regardless of whether UART is enabled).
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Tiva™ TM4C129ENCPDT Microcontroller Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 The UARTILPR register stores the 8-bit low-power counter divisor value used to derive the low-power SIR pulse width clock by dividing down the system clock (SysClk). All the bits are cleared when reset. The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power divisor value written to UARTILPR.
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Universal Asynchronous Receivers/Transmitters (UARTs) Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD register is ignored. When changing the UARTIBRD register, the new value does not take effect until transmission/reception of the current character is complete.
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Tiva™ TM4C129ENCPDT Microcontroller Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on reset. When changing the UARTFBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register.
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Universal Asynchronous Receivers/Transmitters (UARTs) Register 7: UART Line Control (UARTLCRH), offset 0x02C The UARTLCRH register is the line control register. Serial parameters such as data length, parity, and stop bit selection are implemented in this register. When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register. UART Line Control (UARTLCRH) UART0 base: 0x4000.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 FEN RW 0 Description UART Enable FIFOs Value Description 3 STP2 RW 0 0 The FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. 1 The transmit and receive FIFO buffers are enabled (FIFO mode). UART Two Stop Bits Select Value Description 0 One stop bit is transmitted at the end of a frame. 1 Two stop bits are transmitted at the end of a frame.
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Universal Asynchronous Receivers/Transmitters (UARTs) Register 8: UART Control (UARTCTL), offset 0x030 The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set. To enable the UART module, the UARTEN bit must be set. If software requires a configuration change in the module, the UARTEN bit must be cleared before the configuration changes are written.
PAGE 1313
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15 CTSEN RW 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Enable Clear To Send Value Description 14 RTSEN RW 0 0 CTS hardware flow control is disabled. 1 CTS hardware flow control is enabled.
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Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 7 LBE RW 0 Description UART Loop Back Enable Value Description 0 Normal operation. 1 The UnTx path is fed through the UnRx path. 6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 2 SIRLP RW 0 Description UART SIR Low-Power Mode This bit selects the IrDA encoding mode. Value Description 0 Low-level bits are transmitted as an active High pulse with a width of 3/16th of the bit period. 1 The UART operates in SIR Low-Power mode. Low-level bits are transmitted with a pulse width which is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate.
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Universal Asynchronous Receivers/Transmitters (UARTs) Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered. The interrupts are generated based on a transition through a level rather than being based on the level.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 2:0 TXIFLSEL RW 0x2 Description UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Value Description 0x0 TX FIFO ≤ ⅞ empty 0x1 TX FIFO ≤ ¾ empty 0x2 TX FIFO ≤ ½ empty (default) 0x3 TX FIFO ≤ ¼ empty 0x4 TX FIFO ≤ ⅛ empty 0x5-0x7 Reserved Note: If the EOT bit in UARTCTL is set (see page 1312), the transmit interrupt is generated once the FIFO is completely empty and all dat
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Universal Asynchronous Receivers/Transmitters (UARTs) Register 10: UART Interrupt Mask (UARTIM), offset 0x038 The UARTIM register is the interrupt mask set/clear register. On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit prevents the raw interrupt signal from being sent to the interrupt controller.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 16 DMARXIM RW 0 Description Receive DMA Interrupt Mask Value Description 0 The DMARXRIS interrupt is suppressed and not sent to the interrupt controller. 1 An interrupt is sent to the interrupt controller when the DMARXRIS bit in the UARTRIS register is set. 15:13 reserved RO 0 Software should not rely on the value of a reserved bit.
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Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 8 PEIM RW 0 Description UART Parity Error Interrupt Mask Value Description 7 FEIM RW 0 0 The PERIS interrupt is suppressed and not sent to the interrupt controller. 1 An interrupt is sent to the interrupt controller when the PERIS bit in the UARTRIS register is set. UART Framing Error Interrupt Mask Value Description 6 RTIM RW 0 0 The FERIS interrupt is suppressed and not sent to the interrupt controller.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 2 DCDIM RW 0 Description UART Data Carrier Detect Modem Interrupt Mask Value Description 1 CTSIM RW 0 0 The DCDRIS interrupt is suppressed and not sent to the interrupt controller. 1 An interrupt is sent to the interrupt controller when the DCDRIS bit in the UARTRIS register is set.
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Universal Asynchronous Receivers/Transmitters (UARTs) Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C The UARTRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt. A write has no effect. UART Raw Interrupt Status (UARTRIS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UART3 base: 0x4000.F000 UART4 base: 0x4001.0000 UART5 base: 0x4001.1000 UART6 base: 0x4001.
PAGE 1323
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 12 9BITRIS RO 0 Description 9-Bit Mode Raw Interrupt Status Value Description 0 No interrupt 1 A receive address match has occurred. This bit is cleared by writing a 1 to the 9BITIC bit in the UARTICR register. 11 EOTRIS RO 0 End of Transmission Raw Interrupt Status Value Description 0 No interrupt 1 The last bit of all transmitted data and flags has left the serializer.
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Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 6 RTRIS RO 0 Description UART Receive Time-Out Raw Interrupt Status Value Description 0 No interrupt 1 A receive time out has occurred. This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register. For receive timeout, the RTIM bit in the UARTIM register must be set to see the RTRIS status.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1 CTSRIS RO 0 Description UART Clear to Send Modem Raw Interrupt Status Value Description 0 No interrupt 1 Clear to Send used for software flow control. This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR register. 0 RIRIS RO 0 UART Ring Indicator Modem Raw Interrupt Status Value Description 0 No interrupt 1 Ring Indicator used for software flow control.
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Universal Asynchronous Receivers/Transmitters (UARTs) Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 The UARTMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. UART Masked Interrupt Status (UARTMIS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UART3 base: 0x4000.F000 UART4 base: 0x4001.0000 UART5 base: 0x4001.1000 UART6 base: 0x4001.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 12 9BITMIS RO 0 Description 9-Bit Mode Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked interrupt was signaled due to a receive address match. This bit is cleared by writing a 1 to the 9BITIC bit in the UARTICR register. 11 EOTMIS RO 0 End of Transmission Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked.
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Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 6 RTMIS RO 0 Description UART Receive Time-Out Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked interrupt was signaled due to a receive time out. This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register. For receive timeout, the RTIM bit in the UARTIM register must be set to see the RTMIS status.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1 CTSMIS RO 0 Description UART Clear to Send Modem Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked interrupt was signaled due to Clear to Send. This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR register. 0 RIMIS RO 0 UART Ring Indicator Modem Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked.
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Universal Asynchronous Receivers/Transmitters (UARTs) Register 13: UART Interrupt Clear (UARTICR), offset 0x044 The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect. Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2. UART Interrupt Clear (UARTICR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.
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Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 9 BEIC W1C 0 Description Break Error Interrupt Clear Writing a 1 to this bit clears the BERIS bit in the UARTRIS register and the BEMIS bit in the UARTMIS register. 8 PEIC W1C 0 Parity Error Interrupt Clear Writing a 1 to this bit clears the PERIS bit in the UARTRIS register and the PEMIS bit in the UARTMIS register.
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Universal Asynchronous Receivers/Transmitters (UARTs) Register 14: UART DMA Control (UARTDMACTL), offset 0x048 The UARTDMACTL register is the DMA control register. UART DMA Control (UARTDMACTL) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UART3 base: 0x4000.F000 UART4 base: 0x4001.0000 UART5 base: 0x4001.1000 UART6 base: 0x4001.2000 UART7 base: 0x4001.3000 Offset 0x048 Type RW, reset 0x0000.
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Tiva™ TM4C129ENCPDT Microcontroller Register 15: UART 9-Bit Self Address (UART9BITADDR), offset 0x0A4 The UART9BITADDR register is used to write the specific address that should be matched with the receiving byte when the 9-bit Address Mask (UART9BITAMASK) is set to 0xFF. This register is used in conjunction with UART9BITAMASK to form a match for address-byte received. UART 9-Bit Self Address (UART9BITADDR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UART3 base: 0x4000.
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Universal Asynchronous Receivers/Transmitters (UARTs) Register 16: UART 9-Bit Self Address Mask (UART9BITAMASK), offset 0x0A8 The UART9BITAMASK register is used to enable the address mask for 9-bit mode. The address bits are masked to create a set of addresses to be matched with the received address byte. UART 9-Bit Self Address Mask (UART9BITAMASK) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UART3 base: 0x4000.F000 UART4 base: 0x4001.0000 UART5 base: 0x4001.
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Tiva™ TM4C129ENCPDT Microcontroller Register 17: UART Peripheral Properties (UARTPP), offset 0xFC0 The UARTPP register provides information regarding the properties of the UART module. UART Peripheral Properties (UARTPP) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UART3 base: 0x4000.F000 UART4 base: 0x4001.0000 UART5 base: 0x4001.1000 UART6 base: 0x4001.2000 UART7 base: 0x4001.3000 Offset 0xFC0 Type RO, reset 0x0000.
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Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 0 SC RO 0x1 Description Smart Card Support Value Description 0 The UART module does not provide smart card support. 1 The UART module provides smart card support.
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Tiva™ TM4C129ENCPDT Microcontroller Register 18: UART Clock Configuration (UARTCC), offset 0xFC8 The UARTCC register controls the baud clock source for the UART module. For more information, see the section called “Peripheral Clock Sources” on page 241. Note: If the PIOSC is used for the UART baud clock, the system clock frequency must be at least 9 MHz in Run mode. UART Clock Configuration (UARTCC) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UART3 base: 0x4000.
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Universal Asynchronous Receivers/Transmitters (UARTs) Register 19: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 4 (UARTPeriphID4) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UART3 base: 0x4000.F000 UART4 base: 0x4001.0000 UART5 base: 0x4001.1000 UART6 base: 0x4001.2000 UART7 base: 0x4001.
PAGE 1339
Tiva™ TM4C129ENCPDT Microcontroller Register 20: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 5 (UARTPeriphID5) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UART3 base: 0x4000.F000 UART4 base: 0x4001.0000 UART5 base: 0x4001.1000 UART6 base: 0x4001.2000 UART7 base: 0x4001.3000 Offset 0xFD4 Type RO, reset 0x0000.
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Universal Asynchronous Receivers/Transmitters (UARTs) Register 21: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 6 (UARTPeriphID6) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UART3 base: 0x4000.F000 UART4 base: 0x4001.0000 UART5 base: 0x4001.1000 UART6 base: 0x4001.2000 UART7 base: 0x4001.
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Tiva™ TM4C129ENCPDT Microcontroller Register 22: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 7 (UARTPeriphID7) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UART3 base: 0x4000.F000 UART4 base: 0x4001.0000 UART5 base: 0x4001.1000 UART6 base: 0x4001.2000 UART7 base: 0x4001.3000 Offset 0xFDC Type RO, reset 0x0000.
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Universal Asynchronous Receivers/Transmitters (UARTs) Register 23: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 0 (UARTPeriphID0) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UART3 base: 0x4000.F000 UART4 base: 0x4001.0000 UART5 base: 0x4001.1000 UART6 base: 0x4001.2000 UART7 base: 0x4001.
PAGE 1343
Tiva™ TM4C129ENCPDT Microcontroller Register 24: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 1 (UARTPeriphID1) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UART3 base: 0x4000.F000 UART4 base: 0x4001.0000 UART5 base: 0x4001.1000 UART6 base: 0x4001.2000 UART7 base: 0x4001.3000 Offset 0xFE4 Type RO, reset 0x0000.
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Universal Asynchronous Receivers/Transmitters (UARTs) Register 25: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 2 (UARTPeriphID2) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UART3 base: 0x4000.F000 UART4 base: 0x4001.0000 UART5 base: 0x4001.1000 UART6 base: 0x4001.2000 UART7 base: 0x4001.
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Tiva™ TM4C129ENCPDT Microcontroller Register 26: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 3 (UARTPeriphID3) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UART3 base: 0x4000.F000 UART4 base: 0x4001.0000 UART5 base: 0x4001.1000 UART6 base: 0x4001.2000 UART7 base: 0x4001.3000 Offset 0xFEC Type RO, reset 0x0000.
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Universal Asynchronous Receivers/Transmitters (UARTs) Register 27: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 0 (UARTPCellID0) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UART3 base: 0x4000.F000 UART4 base: 0x4001.0000 UART5 base: 0x4001.1000 UART6 base: 0x4001.2000 UART7 base: 0x4001.3000 Offset 0xFF0 Type RO, reset 0x0000.
PAGE 1347
Tiva™ TM4C129ENCPDT Microcontroller Register 28: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 1 (UARTPCellID1) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UART3 base: 0x4000.F000 UART4 base: 0x4001.0000 UART5 base: 0x4001.1000 UART6 base: 0x4001.2000 UART7 base: 0x4001.3000 Offset 0xFF4 Type RO, reset 0x0000.
PAGE 1348
Universal Asynchronous Receivers/Transmitters (UARTs) Register 29: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 2 (UARTPCellID2) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UART3 base: 0x4000.F000 UART4 base: 0x4001.0000 UART5 base: 0x4001.1000 UART6 base: 0x4001.2000 UART7 base: 0x4001.3000 Offset 0xFF8 Type RO, reset 0x0000.
PAGE 1349
Tiva™ TM4C129ENCPDT Microcontroller Register 30: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 3 (UARTPCellID3) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UART3 base: 0x4000.F000 UART4 base: 0x4001.0000 UART5 base: 0x4001.1000 UART6 base: 0x4001.2000 UART7 base: 0x4001.3000 Offset 0xFFC Type RO, reset 0x0000.
PAGE 1350
Quad Synchronous Serial Interface (QSSI) 20 Quad Synchronous Serial Interface (QSSI) The TM4C129ENCPDT microcontroller includes four Quad-Synchronous Serial Interface (QSSI) modules. All four of the modules support Advanced and Bi-SSI interfaces as well as a Quad-SSI enhancement to provide faster throughput of data.
PAGE 1351
Tiva™ TM4C129ENCPDT Microcontroller Figure 20-1. QSSI Module with Advanced, Bi-SSI and Quad-SSI Support DMA Request DMA Control SSIDMACTL Interrupt Interrupt Control TxFIFO 8 x 16 SSIIM SSIMIS SSIRIS SSIICR . . . Control/Status SSInXDAT3 SSICR0 SSICR1 SSISR SSInXDAT2 Transmit/ Receive Logic SSIDR RxFIFO 8 x 16 Clock Prescaler System Clock . . .
PAGE 1352
Quad Synchronous Serial Interface (QSSI) parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 795) to assign the QSSI signal to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 750. Note that for the QSSI module, when operating in Legacy Mode, SSInXDAT0 functions as SSInTX and SSInXDAT1 functions as SSInRX. Table 20-1.
PAGE 1353
Tiva™ TM4C129ENCPDT Microcontroller with internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. The QSSI also supports the µDMA interface. The transmit and receive FIFOs can be programmed as destination/source addresses in the µDMA module. µDMA operation is enabled by setting the appropriate bit(s) in the SSIDMACTL register (see page 1384). 20.3.
PAGE 1354
Quad Synchronous Serial Interface (QSSI) The SSI only provides an SSIClk while transmitting data. When receiving data in master mode, a dummy write to the SSIDR register must be performed before any read so that the SSIClk can be properly received by the slave and allow data to be sent to the receive FIFO of the master.
PAGE 1355
Tiva™ TM4C129ENCPDT Microcontroller Table 20-2.
PAGE 1356
Quad Synchronous Serial Interface (QSSI) Table 20-3. SSInFss Functionality (continued) Mode FSSHLDFRM 0 Advanced/Bi-/Quad1 SSI Mode 20.3.5 Description SSInFss is asserted low after every byte of data New data written to the TX FIFO notifies SSInFss to assert low until the Tx FIFO is empty. High Speed Clock Operation In master mode, QSSI module can enable a high speed clock by setting the HSCLKEN bit in the SSI Control 1 (SSICR1) register.
PAGE 1357
Tiva™ TM4C129ENCPDT Microcontroller a new or next byte is written to the RX FIFO, thus the counter will continue to count down to zero unless there is new activity. The time-out period is 32 periods based on the period of SSInClk. When the counter reaches zero, a time-out interrupt bit, RTRIS, is set in the SSIRIS register. The time-out interrupt can be cleared by writing a 1 to the RTIC bit of the SSI Interrupt Clear (SSIIC) register or by emptying the RX FIFO.
PAGE 1358
Quad Synchronous Serial Interface (QSSI) Table 20-4.
PAGE 1359
Tiva™ TM4C129ENCPDT Microcontroller Figure 20-3. TI Synchronous Serial Frame Format (Continuous Transfer) SSInClk SSInFss SSInTx/SSInRx MSB LSB 4 to 16 bits 20.3.7.2 Freescale SPI Frame Format The Freescale SPI interface is a four-wire interface where the SSInFss signal behaves as a slave select. If operating in Legacy Mode and using the Freescale SPI Frame Format, the inactive state and phase of the SSInClk signal are programmable through the SPO and SPH bits in the SSICR0 control register.
PAGE 1360
Quad Synchronous Serial Interface (QSSI) Figure 20-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 SSInClk SSInFss SSInRx LSB MSB Q 4 to 16 bits SSInTx MSB Note: LSB Q is undefined. Figure 20-5.
PAGE 1361
Tiva™ TM4C129ENCPDT Microcontroller In the case of a single word transmission, after all bits of the data word have been transferred, the SSInFss line is returned to its idle High state one SSInClk period after the last bit has been captured.
PAGE 1362
Quad Synchronous Serial Interface (QSSI) In the case of a single word transfer, after all bits have been transferred, the SSInFss line is returned to its idle High state one SSInClk period after the last bit has been captured. For continuous back-to-back transfers, the SSInFss pin is held Low between successive data words, and termination is the same as that of the single word transfer. 20.3.7.
PAGE 1363
Tiva™ TM4C129ENCPDT Microcontroller If the QSSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by the SSInFss master signal being driven Low, causing slave data to be immediately transferred onto the SSInDAT1/SSInRX line of the master. The master SSInDAT0/SSInTX output pad is enabled. One-half period later, valid master data is transferred to the SSInDAT0/SSInTX line.
PAGE 1364
Quad Synchronous Serial Interface (QSSI) If the QSSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by the SSInFss master signal being driven Low. The master SSInDAT0/SSInTX output pad is enabled. After an additional one-half SSInClk period, both master and slave data are enabled onto their respective transmission lines. At the same time, SSInClk is enabled with a falling edge transition.
PAGE 1365
Tiva™ TM4C129ENCPDT Microcontroller 1. Enable the QSSI module using the RCGCSSI register (see page 397). 2. Enable the clock to the appropriate GPIO module via the RCGCGPIO register (see page 389). To find out which GPIO port to enable, refer to Table 29-5 on page 1932. 3. Set the GPIO AFSEL bits for the appropriate pins (see page 778). To determine which GPIOs to configure, see Table 29-4 on page 1921. 4.
PAGE 1366
Quad Synchronous Serial Interface (QSSI) c. Optionally, enable the µDMA completion interrupt by setting the DMATXIM or DMARXIM bit in the SSIIM register. Note: For a TX DMA completion interrupt, software must disable the µDMA transmit enable to the SSI by clearing the TXDMAE bit in the QSSI DMA Control (SSIDMACTL) register and then setting the DMATXIC bit in the SSIICR register. This clears the DMA completion interrupt.
PAGE 1367
Tiva™ TM4C129ENCPDT Microcontroller 3. Set the MODE bit to 0x1 and the FSSHLDFM bit to 1 in the SSICR1 register. To operate in the master mode, program the MS bit to 0. Program the remaining bits in the SSICR0 and SSICR1 register to relevant values. 4. Fill the Tx FIFO with one data byte. 5. Set the EOM bit in the SSICR1 register. 6. Fill the Tx FIFO with one data byte. 20.5 Register Map Table 20-5 on page 1367 lists the QSSI registers.
PAGE 1368
Quad Synchronous Serial Interface (QSSI) Table 20-5. SSI Register Map (continued) Description See page 0x0000.0000 QSSI Peripheral Identification 1 1392 RO 0x0000.0018 QSSI Peripheral Identification 2 1393 SSIPeriphID3 RO 0x0000.0001 QSSI Peripheral Identification 3 1394 0xFF0 SSIPCellID0 RO 0x0000.000D QSSI PrimeCell Identification 0 1395 0xFF4 SSIPCellID1 RO 0x0000.00F0 QSSI PrimeCell Identification 1 1396 0xFF8 SSIPCellID2 RO 0x0000.
PAGE 1369
Tiva™ TM4C129ENCPDT Microcontroller Register 1: QSSI Control 0 (SSICR0), offset 0x000 The SSICR0 register contains bit fields that control various functions within the QSSI module. Functionality such as protocol mode, clock rate, and data size are configured in this register. QSSI Control 0 (SSICR0) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0x000 Type RW, reset 0x0000.
PAGE 1370
Quad Synchronous Serial Interface (QSSI) Bit/Field Name Type Reset 5:4 FRF RW 0x0 Description QSSI Frame Format Select Note: When operating in Advanced/Bi-/Quad-SSI mode these bits must be programmed to 0x0 (Freescale SPI Frame Format). Value Frame Format 0x0 Freescale SPI Frame Format 0x1 Texas Instruments Synchronous Serial Frame Format 0x2-0x3 Reserved 3:0 DSS RW 0x0 QSSI Data Size Select Note: When operating in Advanced, Bi- or Quad-SSI, data size can only be 8-bit.
PAGE 1371
Tiva™ TM4C129ENCPDT Microcontroller Register 2: QSSI Control 1 (SSICR1), offset 0x004 The SSICR1 register contains bit fields that control various functions within the QSSI module. Master and slave mode functionality is controlled by this register. QSSI Control 1 (SSICR1) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0x004 Type RW, reset 0x0000.
PAGE 1372
Quad Synchronous Serial Interface (QSSI) Bit/Field Name Type Reset 8 DIR RW 0 Description QSSI Direction of Operation Value Description 7:6 MODE RW 0x0 0 TX (Transmit Mode) write direction 1 RX (Receive Mode) read direction QSSI Mode Value Description 0x0 Legacy SSI mode 0x1 Bi-SSI mode 0x2 Quad-SSI Mode 0x3 Advanced SSI Mode with 8-bit packet size 5:3 reserved RO 0 Software should not rely on the value of a reserved bit.
PAGE 1373
Tiva™ TM4C129ENCPDT Microcontroller Register 3: QSSI Data (SSIDR), offset 0x008 Important: This register is read-sensitive. See the register description for details. The SSIDR register is 16-bits wide. When the SSIDR register is read, the entry in the receive FIFO that is pointed to by the current FIFO read pointer is accessed. When a data value is removed by the QSSI receive logic from the incoming data frame, it is placed into the entry in the receive FIFO pointed to by the current FIFO write pointer.
PAGE 1374
Quad Synchronous Serial Interface (QSSI) Register 4: QSSI Status (SSISR), offset 0x00C The SSISR register contains bits that indicate the FIFO fill status and the QSSI busy status. QSSI Status (SSISR) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0x00C Type RO, reset 0x0000.
PAGE 1375
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 0 TFE RO 1 Description QSSI Transmit FIFO Empty Value Description 0 The transmit FIFO is not empty. 1 The transmit FIFO is empty.
PAGE 1376
Quad Synchronous Serial Interface (QSSI) Register 5: QSSI Clock Prescale (SSICPSR), offset 0x010 The SSICPSR register specifies the division factor which is used to derive the SSInClk from the system clock. The clock is further divided by a value from 1 to 256, which is 1 + SCR. SCR is programmed in the SSICR0 register. The frequency of the SSInClk is defined by: SSInClk = SysClk / (CPSDVSR * (1 + SCR)) The value programmed into this register must be an even number between 2 and 254.
PAGE 1377
Tiva™ TM4C129ENCPDT Microcontroller Register 6: QSSI Interrupt Mask (SSIIM), offset 0x014 The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits are cleared on reset. On a read, this register gives the current value of the mask on the corresponding interrupt. Setting a bit clears the mask, enabling the interrupt to be sent to the interrupt controller. Clearing a bit sets the corresponding mask, preventing the interrupt from being signaled to the controller.
PAGE 1378
Quad Synchronous Serial Interface (QSSI) Bit/Field Name Type Reset 2 RXIM RW 0 Description QSSI Receive FIFO Interrupt Mask Value Description 1 RTIM RW 0 0 The receive FIFO interrupt is masked. 1 The receive FIFO interrupt is not masked. QSSI Receive Time-Out Interrupt Mask Value Description 0 RORIM RW 0 0 The receive FIFO time-out interrupt is masked. 1 The receive FIFO time-out interrupt is not masked.
PAGE 1379
Tiva™ TM4C129ENCPDT Microcontroller Register 7: QSSI Raw Interrupt Status (SSIRIS), offset 0x018 The SSIRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. QSSI Raw Interrupt Status (SSIRIS) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0x018 Type RO, reset 0x0000.
PAGE 1380
Quad Synchronous Serial Interface (QSSI) Bit/Field Name Type Reset 3 TXRIS RO 1 Description QSSI Transmit FIFO Raw Interrupt Status Value Description 0 No interrupt. 1 The transmit FIFO is half empty or less. This bit is cleared when the transmit FIFO is more than half full. 2 RXRIS RO 0 QSSI Receive FIFO Raw Interrupt Status Value Description 0 No interrupt. 1 The receive FIFO is half full or more. This bit is cleared when the receive FIFO is less than half full.
PAGE 1381
Tiva™ TM4C129ENCPDT Microcontroller Register 8: QSSI Masked Interrupt Status (SSIMIS), offset 0x01C The SSIMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. QSSI Masked Interrupt Status (SSIMIS) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0x01C Type RO, reset 0x0000.
PAGE 1382
Quad Synchronous Serial Interface (QSSI) Bit/Field Name Type Reset 3 TXMIS RO 0 Description QSSI Transmit FIFO Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked interrupt was signaled due to the transmit FIFO being half empty or less. This bit is cleared when the transmit FIFO is more than half empty . 2 RXMIS RO 0 QSSI Receive FIFO Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked.
PAGE 1383
Tiva™ TM4C129ENCPDT Microcontroller Register 9: QSSI Interrupt Clear (SSIICR), offset 0x020 The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. QSSI Interrupt Clear (SSIICR) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0x020 Type W1C, reset 0x0000.
PAGE 1384
Quad Synchronous Serial Interface (QSSI) Register 10: QSSI DMA Control (SSIDMACTL), offset 0x024 The SSIDMACTL register is the µDMA control register. QSSI DMA Control (SSIDMACTL) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0x024 Type RW, reset 0x0000.
PAGE 1385
Tiva™ TM4C129ENCPDT Microcontroller Register 11: QSSI Peripheral Properties (SSIPP), offset 0xFC0 The SSIPP register provides information regarding the properties of the QSSI module. QSSI Peripheral Properties (SSIPP) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0xFC0 Type RO, reset 0x0000.
PAGE 1386
Quad Synchronous Serial Interface (QSSI) Register 12: QSSI Clock Configuration (SSICC), offset 0xFC8 The SSICC register controls the baud clock source for the QSSI module. Note: If ALTCLK is used for the QSSI baud clock, the system clock frequency must be at least twice that of the ALTCLK programmed value in Run mode. QSSI Clock Configuration (SSICC) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0xFC8 Type RW, reset 0x0000.
PAGE 1387
Tiva™ TM4C129ENCPDT Microcontroller Register 13: QSSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. QSSI Peripheral Identification 4 (SSIPeriphID4) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0xFD0 Type RO, reset 0x0000.
PAGE 1388
Quad Synchronous Serial Interface (QSSI) Register 14: QSSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. QSSI Peripheral Identification 5 (SSIPeriphID5) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0xFD4 Type RO, reset 0x0000.
PAGE 1389
Tiva™ TM4C129ENCPDT Microcontroller Register 15: QSSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. QSSI Peripheral Identification 6 (SSIPeriphID6) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0xFD8 Type RO, reset 0x0000.
PAGE 1390
Quad Synchronous Serial Interface (QSSI) Register 16: QSSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. QSSI Peripheral Identification 7 (SSIPeriphID7) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0xFDC Type RO, reset 0x0000.
PAGE 1391
Tiva™ TM4C129ENCPDT Microcontroller Register 17: QSSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. QSSI Peripheral Identification 0 (SSIPeriphID0) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0xFE0 Type RO, reset 0x0000.
PAGE 1392
Quad Synchronous Serial Interface (QSSI) Register 18: QSSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. QSSI Peripheral Identification 1 (SSIPeriphID1) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0xFE4 Type RO, reset 0x0000.
PAGE 1393
Tiva™ TM4C129ENCPDT Microcontroller Register 19: QSSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. QSSI Peripheral Identification 2 (SSIPeriphID2) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0xFE8 Type RO, reset 0x0000.
PAGE 1394
Quad Synchronous Serial Interface (QSSI) Register 20: QSSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. QSSI Peripheral Identification 3 (SSIPeriphID3) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0xFEC Type RO, reset 0x0000.
PAGE 1395
Tiva™ TM4C129ENCPDT Microcontroller Register 21: QSSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. QSSI PrimeCell Identification 0 (SSIPCellID0) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0xFF0 Type RO, reset 0x0000.
PAGE 1396
Quad Synchronous Serial Interface (QSSI) Register 22: QSSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. QSSI PrimeCell Identification 1 (SSIPCellID1) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0xFF4 Type RO, reset 0x0000.
PAGE 1397
Tiva™ TM4C129ENCPDT Microcontroller Register 23: QSSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. QSSI PrimeCell Identification 2 (SSIPCellID2) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0xFF8 Type RO, reset 0x0000.
PAGE 1398
Quad Synchronous Serial Interface (QSSI) Register 24: QSSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. QSSI PrimeCell Identification 3 (SSIPCellID3) QSSI0 base: 0x4000.8000 QSSI1 base: 0x4000.9000 QSSI2 base: 0x4000.A000 QSSI3 base: 0x4000.B000 Offset 0xFFC Type RO, reset 0x0000.
PAGE 1399
Tiva™ TM4C129ENCPDT Microcontroller 21 Inter-Integrated Circuit (I2C) Interface The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacturing.
PAGE 1400
Inter-Integrated Circuit (I2C) Interface – Slave generates interrupts when data has been transferred or requested by a master or when a START or STOP condition is detected ■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Ability to execute single data transfers or burst data transfers using the RX and TX FIFOs in the I2C 21.
PAGE 1401
Tiva™ TM4C129ENCPDT Microcontroller 21.2 Signal Description The following table lists the external signals of the I2C interface and describes the function of each. The I2C interface signals are alternate functions for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for the I2C signals.
PAGE 1402
Inter-Integrated Circuit (I2C) Interface Table 21-1. I2C Signals (128TQFP) (continued) Pin Name Pin Number Pin Mux / Pin Assignment Pin Type Buffer Type Description I2C8SCL 3 35 PD2 (2) PA2 (2) I/O OD I2C module 8 clock. Note that this signal has an active pull-up. The corresponding port pin should not be configured as open drain. I2C8SDA 4 36 PD3 (2) PA3 (2) I/O OD I2C module 8 data. I2C9SCL 33 PA0 (2) I/O OD I2C module 9 clock. Note that this signal has an active pull-up.
PAGE 1403
Tiva™ TM4C129ENCPDT Microcontroller 21.3.1.1 START and STOP Conditions The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP. A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition, and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition. The bus is considered busy after a START condition and free after a STOP condition. See Figure 21-3. Figure 21-3.
PAGE 1404
Inter-Integrated Circuit (I2C) Interface master transmits (sends) data to the selected slave, and a one in this position means that the master receives data from the slave. Figure 21-5. R/S Bit in First Byte MSB LSB R/S Slave address 21.3.1.3 Data Validity The data on the SDA line must be stable during the high period of the clock, and the data line can only change when SCL is Low (see Figure 21-6). Figure 21-6. Data Validity During Bit Transfer on the I2C Bus SDA SCL 21.3.1.
PAGE 1405
Tiva™ TM4C129ENCPDT Microcontroller 2. Data is written to the I2CMDR register. 3. When the BUSY bit in the I2CMCS register is 0 , the Master writes 0x3 to the I2CMCS register to initiate a transfer. 4. The Master does not generate a STOP condition but instead writes another slave address to the I2CMSA register and then writes 0x3 to initiate the repeated START. A repeated start sequence for a Master receive is similar: 1.
PAGE 1406
Inter-Integrated Circuit (I2C) Interface slave after bus recovery, the actual behavior on the bus varies. If the slave resumes in a state where it can acknowledge the master (essentially, where it was before the bus hang), it continues where it left off. However, if the slave resumes in a reset state (or if a forced STOP by the master causes the slave to enter the idle state), it may ignore the master's attempt to complete the burst operation and NAK the first data byte that the master sends or requests.
PAGE 1407
Tiva™ TM4C129ENCPDT Microcontroller 21.3.1.9 Glitch Suppression in Multi-Master Configuration When a multi-master configuration is being used, the PULSEL bit in the I2CMTPR register can be programmed to provide glitch suppression on the SCL and SDA lines and assure proper signal values. The glitch suppression value is in terms of buffered system clocks. Note that all signals will be delayed internally when glitch suppression is nonzero.
PAGE 1408
Inter-Integrated Circuit (I2C) Interface receive a Quick Command, it should be expecting such a command because it must write the I2CSDR with a specific value when R/S is set. 21.3.2 Available Speed Modes The I2C bus can run in Standard mode (100 kbps), Fast mode (400 kbps), Fast mode plus (1 Mbps) or High-Speed mode (3.4 Mbps, provided correct system clock frequency is set and there is appropriate pull strength on SCL and SDA lines).
PAGE 1409
Tiva™ TM4C129ENCPDT Microcontroller Table 21-2. Examples of I2C Master Timer Period Versus Speed Mode (continued) 21.3.2.
PAGE 1410
Inter-Integrated Circuit (I2C) Interface then to send the master code byte, software should place the value of the master code byte into the I2CMSA register and write the I2CMCS register with 0x50. Either configuration places the I2C master peripheral in High-speed mode, and all subsequent transfers (until STOP) are carried out at High-speed data rate using the normal I2CMCS command bits, without setting the HS bit in the I2CMCS register.
PAGE 1411
Tiva™ TM4C129ENCPDT Microcontroller ■ Slave transaction received (DATARIS bit) ■ Slave transaction requested (DATARIS bit) ■ Slave next byte transfer request (DATARIS bit) ■ Stop condition on bus detected (STOPRIS bit) ■ Start condition on bus detected (STARTRIS bit) ■ RX DMA interrupt pending (DMARXRIS bit) ■ TX DMA interrupt pending (DMATXRIS bit) ■ Programmable trigger value for FIFO has been reached and a TX FIFO request interrupt is pending (TXRIS bit) ■ Programmable trigger value for FIFO has been re
PAGE 1412
Inter-Integrated Circuit (I2C) Interface Each FIFO has a programmable threshold point which indicates when the FIFO service interrupt should be generated. Additionally, a FIFO receive full and transmit empty interrupt can be enabled in the Interrupt Mask (I2CxIMR) registers of both the master and slave. Note that if we clear the TXFERIS interrupt (by setting the TXFEIC bit) when the TX FIFO is empty, the TXFERIS interrupt does not reassert even though the TX FIFO remains empty in this situation.
PAGE 1413
Tiva™ TM4C129ENCPDT Microcontroller bytes specified in the I2CMBLEN register has been transferred to the FIFO (and the I2CMBCOUNT register reaches 0x0). At this point, no further requests are generated until the next BURST command is issued. If the µDMA is disabled, FIFOs will be serviced based on the interrupts active in the Master interrupt status registers, the FIFO trigger values shown in the I2CFIFOSTATUS register and completion of a BURST transfer.
PAGE 1414
Inter-Integrated Circuit (I2C) Interface Figure 21-8.
PAGE 1415
Tiva™ TM4C129ENCPDT Microcontroller Figure 21-9.
PAGE 1416
Inter-Integrated Circuit (I2C) Interface Figure 21-10.
PAGE 1417
Tiva™ TM4C129ENCPDT Microcontroller Figure 21-11.
PAGE 1418
Inter-Integrated Circuit (I2C) Interface Figure 21-12.
PAGE 1419
Tiva™ TM4C129ENCPDT Microcontroller Figure 21-13.
PAGE 1420
Inter-Integrated Circuit (I2C) Interface Figure 21-14. Standard High Speed Mode Master Transmit IDLE write slave address to I2CMSA register Master code and arbitration is always done in FAST or STANDARD mode write „---10011” to I2CMCS register read I2CMCS register no Busy=’0' yes no IDLE Error=’0' yes Normal sequence starts here.
PAGE 1421
Tiva™ TM4C129ENCPDT Microcontroller 21.3.6.2 I2C Slave Command Sequences Figure 21-15 on page 1421 presents the command sequence available for the I2C slave. Figure 21-15. Slave Command Sequence Idle Write OWN Slave Address to I2CSOAR Write -------1 to I2CSCSR Read I2CSCSR NO TREQ bit=1? YES Write data to I2CSDR NO RREQ bit=1? FBR is also valid YES Read data from I2CSDR 21.4 Initialization and Configuration 21.4.
PAGE 1422
Inter-Integrated Circuit (I2C) Interface 4. Enable the I2CSDA pin for open-drain operation. See page 783. 5. Configure the PMCn fields in the GPIOPCTL register to assign the I2C signals to the appropriate pins. See page 795 and Table 29-5 on page 1932. 6. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0010. 7. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct value.
PAGE 1423
Tiva™ TM4C129ENCPDT Microcontroller TPR = (System Clock/(2*(SCL_LP + SCL_HP)*SCL_CLK))-1; TPR = (80 MHz/(2*(2+1)*3330000))-1; TPR = 3 Write the I2CMTPR register with the value of 0x0000.0003. 8. To send the master code byte, software should place the value of the master code byte into the I2CMSA register and write the I2CMCS register with the following value depending on the required operation: ■ For Standard High-Speed mode, the I2CMCS register should be written with 0x13.
PAGE 1424
Inter-Integrated Circuit (I2C) Interface Table 21-4. Inter-Integrated Circuit (I2C) Interface Register Map Offset Name Type Reset Description See page I2C Master 0x000 I2CMSA RW 0x0000.0000 I2C Master Slave Address 1426 0x004 I2CMCS RW 0x0000.0020 I2C Master Control/Status 1427 0x008 I2CMDR RW 0x0000.0000 I2C Master Data 1436 0x00C I2CMTPR RW 0x0000.0001 I2C Master Timer Period 1437 0x010 I2CMIMR RW 0x0000.0000 I2C Master Interrupt Mask 1439 0x014 I2CMRIS RO 0x0000.
PAGE 1425
Tiva™ TM4C129ENCPDT Microcontroller 21.6 Register Descriptions (I2C Master) The remainder of this section lists and describes the I2C master registers, in numerical order by address offset.
PAGE 1426
Inter-Integrated Circuit (I2C) Interface Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which determines if the next operation is a Receive (High), or Transmit (Low). I2C Master Slave Address (I2CMSA) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.
PAGE 1427
Tiva™ TM4C129ENCPDT Microcontroller Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 This register accesses status bits when read and control bits when written. When read, the status register indicates the state of the I2C bus controller. When written, the control register configures the I2C controller operation. The START bit generates the START or REPEATED START condition.
PAGE 1428
Inter-Integrated Circuit (I2C) Interface Bit/Field Name Type Reset 29:8 reserved RO 0x0000.00 7 CLKTO RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clock Timeout Error Value Description 0 No clock timeout error. 1 The clock timeout error has occurred.
PAGE 1429
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1 ERROR RO 0 Description Error Value Description 0 No error was detected on the last operation. 1 An error occurred on the last operation. The error can be from the slave address not being acknowledged or the transmit data not being acknowledged. 0 BUSY RO 0 I2C Busy Value Description 0 The controller is idle. 1 The controller is busy. When the BUSY bit is set, the other status bits are not valid.
PAGE 1430
Inter-Integrated Circuit (I2C) Interface Bit/Field Name Type Reset 5 QCMD WO 0 Description Quick Command Value Description 4 HS WO 0 0 Bus transaction is not a quick command. 1 The bus transaction is a quick command. To execute a quick command, the START, STOP and RUN bits also need to be set. After the quick command is issued, the master generates a STOP.
PAGE 1431
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 0 RUN WO 0 Description I2C Master Enable Value Description 0 In standard and high speed mode, this encoding means the master is unable to transmit or receive data. In Burst mode, this bit is not used and must be set to 0. 1 The master is able to transmit or receive data. Note that this bit cannot be set in Burst mode. See field decoding in Table 21-5 on page 1432. Note that the BURST and RUN bits are mutually exclusive.
PAGE 1432
Inter-Integrated Circuit (I2C) Interface Table 21-5. Write Field Decoding for I2CMCS[6:0] I2CMCS[6:0] Current I2CMSA[0] Next State Description State R/S BURST QCCMD HS ACK STOP START RUN Idle 0 0 0 0 X a 0 1 1 START condition followed by TRANSMIT (master goes to the Master Transmit state). 0 0 0 0 X 1 1 1 START condition followed by a TRANSMIT and STOP condition (master remains in Idle state).
PAGE 1433
Tiva™ TM4C129ENCPDT Microcontroller Table 21-5. Write Field Decoding for I2CMCS[6:0] (continued) I2CMCS[6:0] Current I2CMSA[0] Next State Description State R/S BURST QCCMD HS ACK STOP START RUN X 0 0 0 X 0 0 1 TRANSMIT operation (master remains in Master Transmit state). X 0 0 0 X 1 0 0 STOP condition (master goes to Idle state). X 0 0 0 X 1 0 1 TRANSMIT followed by STOP condition (master goes to Idle state).
PAGE 1434
Inter-Integrated Circuit (I2C) Interface Table 21-5. Write Field Decoding for I2CMCS[6:0] (continued) I2CMCS[6:0] Current I2CMSA[0] Next State Description State R/S BURST QCCMD HS ACK STOP START RUN Master Receive X 0 0 0 0 0 0 1 RECEIVE operation with negative ACK (master remains in Master Receive state). X 0 0 0 X 1 0 0 STOP condition (master goes to Idle state). X 0 0 0 0 1 0 1 RECEIVE followed by STOP condition (master goes to Idle state).
PAGE 1435
Tiva™ TM4C129ENCPDT Microcontroller b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by the master or an Address Negative Acknowledge executed by the slave.
PAGE 1436
Inter-Integrated Circuit (I2C) Interface Register 3: I2C Master Data (I2CMDR), offset 0x008 Important: This register is read-sensitive. See the register description for details. This register contains the data to be transmitted when in the Master Transmit state and the data received when in the Master Receive state. If the BURST bit is enabled in the I2CMCS register, then the I2CFIFODATA register is used for the current data transmit or receive value and this register is ignored.
PAGE 1437
Tiva™ TM4C129ENCPDT Microcontroller Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C This register is programmed to set the timer period for the SCL clock and assign the SCL clock to either standard or high-speed mode. I2C Master Timer Period (I2CMTPR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.8000 I2C 9 base: 0x400B.
PAGE 1438
Inter-Integrated Circuit (I2C) Interface Bit/Field Name Type Reset 7 HS WO 0x0 Description High-Speed Enable Value Description 6:0 TPR RW 0x1 0 The SCL Clock Period set by TPR applies to Standard mode (100 Kbps), Fast-mode (400 Kbps), or Fast-mode plus (1 Mbps). 1 The SCL Clock Period set by TPR applies to High-speed mode (3.33 Mbps).
PAGE 1439
Tiva™ TM4C129ENCPDT Microcontroller Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 This register controls whether a raw interrupt is promoted to a controller interrupt. I2C Master Interrupt Mask (I2CMIMR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.8000 I2C 9 base: 0x400B.9000 Offset 0x010 Type RW, reset 0x0000.
PAGE 1440
Inter-Integrated Circuit (I2C) Interface Bit/Field Name Type Reset 9 RXIM RW 0 Description Receive FIFO Request Interrupt Mask Value Description 8 TXIM RW 0 0 The RXRIS interrupt is suppressed and not sent to the interrupt controller. 1 The RX FIFO Request interrupt is sent to the interrupt controller when the RXRIS bit in the I2CMRIS register is set.
PAGE 1441
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3 DMATXIM RW 0 Description Transmit DMA Interrupt Mask Value Description 2 DMARXIM RW 0 0 The DMATXRIS interrupt is suppressed and not sent to the interrupt controller. 1 The transmit DMA complete interrupt is sent to the interrupt controller when the DMATXRIS bit in the I2CMRIS register is set.
PAGE 1442
Inter-Integrated Circuit (I2C) Interface Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 This register specifies whether an interrupt is pending. I2C Master Raw Interrupt Status (I2CMRIS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.8000 I2C 9 base: 0x400B.9000 Offset 0x014 Type RO, reset 0x0000.
PAGE 1443
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 9 RXRIS RO 0 Description Receive FIFO Request Raw Interrupt Status Value Description 0 No interrupt 1 The trigger level for the RX FIFO has been reached or there is data in the FIFO and the burst count is zero. Thus, a RX FIFO request interrupt is pending. This bit is cleared by writing a 1 to the RXIC bit in the I2CMICR register.
PAGE 1444
Inter-Integrated Circuit (I2C) Interface Bit/Field Name Type Reset 3 DMATXRIS RO 0 Description Transmit DMA Raw Interrupt Status Value Description 0 No interrupt. 1 The transmit DMA complete interrupt is pending. This bit is cleared by writing a 1 to the DMATXIC bit in the I2CMICR register. 2 DMARXRIS RO 0 Receive DMA Raw Interrupt Status Value Description 0 No interrupt. 1 The receive DMA complete interrupt is pending.
PAGE 1445
Tiva™ TM4C129ENCPDT Microcontroller Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 This register specifies whether an interrupt was signaled. I2C Master Masked Interrupt Status (I2CMMIS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.8000 I2C 9 base: 0x400B.9000 Offset 0x018 Type RO, reset 0x0000.
PAGE 1446
Inter-Integrated Circuit (I2C) Interface Bit/Field Name Type Reset 9 RXMIS RO 0 Description Receive FIFO Request Interrupt Mask Value Description 0 No interrupt. 1 An unmasked Receive FIFO Request interrupt was signaled and is pending. This bit is cleared by writing a 1 to the RXIC bit in the I2CMICR register. 8 TXMIS RO 0 Transmit Request Interrupt Mask Value Description 0 No interrupt. 1 An unmasked Transmit FIFO Request interrupt was signaled and is pending.
PAGE 1447
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 NACKMIS RO 0 Description Address/Data NACK Interrupt Mask Value Description 0 No interrupt. 1 An unmasked Address/Data NACK interrupt was signaled and is pending. This bit is cleared by writing a 1 to the NACKIC bit in the I2CMICR register. 3 DMATXMIS RO 0 Transmit DMA Interrupt Status Value Description 0 No interrupt. 1 An unmasked transmit DMA complete interrupt was signaled and is pending.
PAGE 1448
Inter-Integrated Circuit (I2C) Interface Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C This register clears the raw and masked interrupts. I2C Master Interrupt Clear (I2CMICR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.8000 I2C 9 base: 0x400B.9000 Offset 0x01C Type WO, reset 0x0000.
PAGE 1449
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 6 STOPIC WO 0 Description STOP Detection Interrupt Clear Writing a 1 to this bit clears the STOPRIS bit in the I2CMRIS register and the STOPMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. 5 STARTIC WO 0 START Detection Interrupt Clear Writing a 1 to this bit clears the STARTRIS bit in the I2CMRIS register and the STARTMIS bit in the I2CMMIS register.
PAGE 1450
Inter-Integrated Circuit (I2C) Interface Register 9: I2C Master Configuration (I2CMCR), offset 0x020 This register configures the mode (Master or Slave), and sets the interface for test mode loopback. I2C Master Configuration (I2CMCR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.8000 I2C 9 base: 0x400B.9000 Offset 0x020 Type RW, reset 0x0000.
PAGE 1451
Tiva™ TM4C129ENCPDT Microcontroller Register 10: I2C Master Clock Low Timeout Count (I2CMCLKOCNT), offset 0x024 This register contains the upper 8 bits of a 12-bit counter that can be used to keep the timeout limit for clock stretching by a remote slave. The lower four bits of the counter are not user visible and are always 0x0. Note: The Master Clock Low Timeout counter counts for the entire time SCL is held Low continuously.
PAGE 1452
Inter-Integrated Circuit (I2C) Interface Register 11: I2C Master Bus Monitor (I2CMBMON), offset 0x02C This register is used to determine the SCL and SDA signal status. I2C Master Bus Monitor (I2CMBMON) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.8000 I2C 9 base: 0x400B.9000 Offset 0x02C Type RO, reset 0x0000.
PAGE 1453
Tiva™ TM4C129ENCPDT Microcontroller Register 12: I2C Master Burst Length (I2CMBLEN), offset 0x030 This register contains the programmed length of bytes that are transferred during a Burst request. I2C Master Burst Length (I2CMBLEN) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.8000 I2C 9 base: 0x400B.9000 Offset 0x030 Type RW, reset 0x0000.
PAGE 1454
Inter-Integrated Circuit (I2C) Interface Register 13: I2C Master Burst Count (I2CMBCNT), offset 0x034 When BURST is active, the value in the I2CMBLEN register is copied into this register and decremented during the BURST transaction. This register can be used to determine the number of transfers that occurred when a BURST terminates early (as a result of a data NACK). When a BURST completes successfully, this register will contain 0. I2C Master Burst Count (I2CMBCNT) I2C 0 base: 0x4002.
PAGE 1455
Tiva™ TM4C129ENCPDT Microcontroller Register 14: I2C Slave Own Address (I2CSOAR), offset 0x800 This register consists of seven address bits that identify the TM4C129ENCPDT I2C device on the I2C bus. I2C Slave Own Address (I2CSOAR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.8000 I2C 9 base: 0x400B.9000 Offset 0x800 Type RW, reset 0x0000.
PAGE 1456
Inter-Integrated Circuit (I2C) Interface Register 15: I2C Slave Control/Status (I2CSCSR), offset 0x804 This register functions as a control register when written, and a status register when read. Read-Only Status Register I2C Slave Control/Status (I2CSCSR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.8000 I2C 9 base: 0x400B.
PAGE 1457
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 QCMDST RC 0 Description Quick Command Status Value Description 3 OAR2SEL RO 0 0 The last transaction was a normal transaction or a transaction has not occurred. 1 The last transaction was a Quick Command transaction. OAR2 Address Matched Value Description 0 Either the address is not matched or the match is in legacy mode. 1 OAR2 address matched and ACKed by the slave.
PAGE 1458
Inter-Integrated Circuit (I2C) Interface Write-Only Control Register I2C Slave Control/Status (I2CSCSR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.8000 I2C 9 base: 0x400B.9000 Offset 0x804 Type WO, reset 0x0000.
PAGE 1459
Tiva™ TM4C129ENCPDT Microcontroller Register 16: I2C Slave Data (I2CSDR), offset 0x808 Important: This register is read-sensitive. See the register description for details. This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state. If the RXFIFO bit or TXFIFO bit are enabled in the I2CSCSR register, then this register is ignored and the data value being transferred from the FIFO is contained in the I2CFIFODATA register.
PAGE 1460
Inter-Integrated Circuit (I2C) Interface Register 17: I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C This register controls whether a raw interrupt is promoted to a controller interrupt. I2C Slave Interrupt Mask (I2CSIMR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.8000 I2C 9 base: 0x400B.9000 Offset 0x80C Type RW, reset 0x0000.
PAGE 1461
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 5 TXIM RW 0 Description Transmit FIFO Request Interrupt Mask Value Description 4 DMATXIM RW 0 0 The TXRIS interrupt is suppressed and not sent to the interrupt controller. 1 The TX FIFO Request interrupt is sent to the interrupt controller when the TXRIS bit in the I2CSRIS register is set.
PAGE 1462
Inter-Integrated Circuit (I2C) Interface Register 18: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 This register specifies whether an interrupt is pending. I2C Slave Raw Interrupt Status (I2CSRIS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.8000 I2C 9 base: 0x400B.9000 Offset 0x810 Type RO, reset 0x0000.
PAGE 1463
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 6 RXRIS RO 0 Description Receive FIFO Request Raw Interrupt Status Value Description 0 No interrupt 1 The trigger value for the FIFO has been reached and a RX FIFO Request interrupt is pending. This bit is cleared by writing a 1 to the RXIC bit in the I2CSICR register.
PAGE 1464
Inter-Integrated Circuit (I2C) Interface Bit/Field Name Type Reset 0 DATARIS RO 0 Description Data Raw Interrupt Status This interrupt encompasses the following: ■ Slave transaction received ■ Slave transaction requested ■ Next byte transfer request Value Description 0 No interrupt. 1 Slave Interrupt is pending. This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR register.
PAGE 1465
Tiva™ TM4C129ENCPDT Microcontroller Register 19: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 This register specifies whether an interrupt was signaled. I2C Slave Masked Interrupt Status (I2CSMIS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.8000 I2C 9 base: 0x400B.9000 Offset 0x814 Type RO, reset 0x0000.
PAGE 1466
Inter-Integrated Circuit (I2C) Interface Bit/Field Name Type Reset 6 RXMIS RO 0 Description Receive FIFO Request Interrupt Mask Value Description 0 No interrupt. 1 An unmasked Receive FIFO Request interrupt was signaled and is pending. This bit is cleared by writing a 1 to the RXIC bit in the I2CSICR register. 5 TXMIS RO 0 Transmit FIFO Request Interrupt Mask Value Description 0 No interrupt. 1 An unmasked Transmit FIFO Request interrupt was signaled and is pending.
PAGE 1467
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1 STARTMIS RO 0 Description Start Condition Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked START condition interrupt was signaled is pending. This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR register. 0 DATAMIS RO 0 Data Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked.
PAGE 1468
Inter-Integrated Circuit (I2C) Interface Register 20: I2C Slave Interrupt Clear (I2CSICR), offset 0x818 This register clears the raw interrupt. A read of this register returns no meaningful data. I2C Slave Interrupt Clear (I2CSICR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.8000 I2C 9 base: 0x400B.9000 Offset 0x818 Type WO, reset 0x0000.
PAGE 1469
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3 DMARXIC WO 0 Description Receive DMA Interrupt Clear Writing a 1 to this bit clears the DMARXRIS bit in the I2CSRIS register and the DMARXMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. 2 STOPIC WO 0 Stop Condition Interrupt Clear Writing a 1 to this bit clears the STOPRIS bit in the I2CSRIS register and the STOPMIS bit in the I2CSMIS register.
PAGE 1470
Inter-Integrated Circuit (I2C) Interface Register 21: I2C Slave Own Address 2 (I2CSOAR2), offset 0x81C This register consists of seven address bits that identify the alternate address for the I2C device on the I2C bus. I2C Slave Own Address 2 (I2CSOAR2) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.8000 I2C 9 base: 0x400B.
PAGE 1471
Tiva™ TM4C129ENCPDT Microcontroller Register 22: I2C Slave ACK Control (I2CSACKCTL), offset 0x820 This register enables the I2C slave to NACK for invalid data or command or ACK for valid data or command. The I2C clock is pulled low after the last data bit until this register is written. I2C Slave ACK Control (I2CSACKCTL) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.
PAGE 1472
Inter-Integrated Circuit (I2C) Interface Register 23: I2C FIFO Data (I2CFIFODATA), offset 0xF00 The I2C FIFO Data (I2CFIFODATA) register contains the current value of the top of the RX or TX FIFO stack being used in the a transfer. Read-Only Status Register I2C FIFO Data (I2CFIFODATA) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.
PAGE 1473
Tiva™ TM4C129ENCPDT Microcontroller Write-Only Control Register I2C FIFO Data (I2CFIFODATA) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.8000 I2C 9 base: 0x400B.9000 Offset 0xF00 Type WO, reset 0x0000.
PAGE 1474
Inter-Integrated Circuit (I2C) Interface Register 24: I2C FIFO Control (I2CFIFOCTL), offset 0xF04 The FIFO Control Register can be programmed to control various aspects of the FIFO transaction, such as RX and TX FIFO assignment, byte count value for FIFO triggers and flushing of the FIFOs. I2C FIFO Control (I2CFIFOCTL) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.
PAGE 1475
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 18:16 RXTRIG RW 0x4 Description RX FIFO Trigger Indicates at what fill level the RX FIFO will generate a trigger. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.
PAGE 1476
Inter-Integrated Circuit (I2C) Interface Register 25: I2C FIFO Status (I2CFIFOSTATUS), offset 0xF08 This register contains the real-time status of the RX and TX FIFOs. I2C FIFO Status (I2CFIFOSTATUS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.8000 I2C 9 base: 0x400B.9000 Offset 0xF08 Type RO, reset 0x0001.
PAGE 1477
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 2 TXBLWTRIG RO 1 Description TX FIFO Below Trigger Level Value Description 1 TXFF RO 0 0 The number of bytes in TX FIFO is above the trigger level programmed by the TXTRIG bit in the I2CFIFOCTL register 1 The number of bytes in the TX FIFO is below the trigger level programmed by the TXTRIG bit in the I2CFIFOCTL register TX FIFO Full Value Description 0 TXFE RO 1 0 The TX FIFO is not full. 1 The TX FIFO is full.
PAGE 1478
Inter-Integrated Circuit (I2C) Interface Register 26: I2C Peripheral Properties (I2CPP), offset 0xFC0 The I2CPP register provides information regarding the properties of the I2C module. I2C Peripheral Properties (I2CPP) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.8000 I2C 9 base: 0x400B.9000 Offset 0xFC0 Type RO, reset 0x0000.
PAGE 1479
Tiva™ TM4C129ENCPDT Microcontroller Register 27: I2C Peripheral Configuration (I2CPC), offset 0xFC4 The I2CPC register allows software to enable features present in the I2C module. I2C Peripheral Configuration (I2CPC) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2C 2 base: 0x4002.2000 I2C 3 base: 0x4002.3000 I2C 4 base: 0x400C.0000 I2C 5 base: 0x400C.1000 I2C 6 base: 0x400C.2000 I2C 7 base: 0x400C.3000 I2C 8 base: 0x400B.8000 I2C 9 base: 0x400B.9000 Offset 0xFC4 Type RO, reset 0x0000.
PAGE 1480
Controller Area Network (CAN) Module 22 Controller Area Network (CAN) Module Controller Area Network (CAN) is a multicast, shared serial bus standard for connecting electronic control units (ECUs). CAN was specifically designed to be robust in electromagnetically-noisy environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair wire. Originally created for automotive purposes, it is also used in many embedded control applications (such as industrial and medical).
PAGE 1481
Tiva™ TM4C129ENCPDT Microcontroller 22.1 Block Diagram Figure 22-1.
PAGE 1482
Controller Area Network (CAN) Module Table 22-1. Controller Area Network Signals (128TQFP) (continued) Pin Name 22.3 Pin Number Pin Mux / Pin Assignment CAN0Tx 34 PA1 (7) CAN1Rx 95 CAN1Tx 96 Pin Type Buffer Type Description O TTL CAN module 0 transmit. PB0 (7) I TTL CAN module 1 receive. PB1 (7) O TTL CAN module 1 transmit. Functional Description The TM4C129ENCPDT CAN controller conforms to the CAN protocol version 2.0 (parts A and B).
PAGE 1483
Tiva™ TM4C129ENCPDT Microcontroller The message object memory is a set of 32 identical memory blocks that hold the current configuration, status, and actual data for each message object. These memory blocks are accessed via either of the CAN message object register interfaces.
PAGE 1484
Controller Area Network (CAN) Module received, it goes through the message handler's filtering process, and if it passes through the filter, is stored in the message object specified by the MNUM bit in the CAN IFn Command Request (CANIFnCRQ) register. The whole message (including all arbitration bits, data-length code, and eight data bytes) is stored in the message object.
PAGE 1485
Tiva™ TM4C129ENCPDT Microcontroller 22.3.4 Configuring a Transmit Message Object The following steps illustrate how to configure a transmit message object. 1.
PAGE 1486
Controller Area Network (CAN) Module ■ Optionally set the RMTEN bit to enable the TXRQST bit to be set on the reception of a matching remote frame allowing automatic transmission ■ Set the EOB bit for a single message object ■ Configure the DLC[3:0] field to specify the size of the data frame. Take care during this configuration not to set the NEWDAT, MSGLST, INTPND or TXRQST bits. 7. Load the data to be transmitted into the CAN IFn Data (CANIFnDA1, CANIFnDA2, CANIFnDB1, CANIFnDB2) registers.
PAGE 1487
Tiva™ TM4C129ENCPDT Microcontroller 22.3.7 Receiving a Data Frame The message handler stores the message from the CAN controller receive shift register into the matching message object in the message RAM. The data bytes, all arbitration bits, and the DLC bits are all stored into the corresponding message object. In this manner, the data bytes are connected with the identifier even if arbitration masks are used. The NEWDAT bit of the CANIFnMCTL register is set to indicate that new data has been received.
PAGE 1488
Controller Area Network (CAN) Module object with the lowest message number. This prioritization is separate from that of the message identifier which is enforced by the CAN bus. As a result, if message object 1 and message object 2 both have valid messages to be transmitted, message object 1 is always transmitted first regardless of the message identifier in the message object itself. 22.3.10 Configuring a Receive Message Object The following steps illustrate how to configure a receive message object. 1.
PAGE 1489
Tiva™ TM4C129ENCPDT Microcontroller The CAN mask registers can be used to allow groups of data frames to be received by a message object. The CAN mask registers, CANIFnMSKn, configure which groups of frames are received by a message object. The UMASK bit in the CANIFnMCTL register enables the MSK bits in the CANIFnMSKn register to filter which frames are received. The MXTD bit in the CANIFnMSK2 register should be set if only 29-bit extended identifiers are expected by this message object. 22.3.
PAGE 1490
Controller Area Network (CAN) Module 22.3.11.3 Reading from a FIFO Buffer When the CPU transfers the contents of a message object from a FIFO buffer by writing its number to the CANIFnCRQ register, the TXRQST and CLRINTPND bits in the CANIFnCMSK register should be set such that the NEWDAT and INTPEND bits in the CANIFnMCTL register are cleared after the read. The values of these bits in the CANIFnMCTL register always reflect the status of the message object before the bits are cleared.
PAGE 1491
Tiva™ TM4C129ENCPDT Microcontroller Figure 22-3. Message Objects in a FIFO Buffer START Message Interrupt Read Interrupt Pointer 0x0000 Case Interrupt Pointer else 0x8000 END Status Change Interrupt Handling MNUM = Interrupt Pointer Write MNUM to IFn Command Request (Read Message to IFn Registers, Reset NEWDAT = 0, Reset INTPND = 0 Read IFn Message Control Yes No NEWDAT = 1 Read Data from IFn Data A,B EOB = 1 Yes No MNUM = MNUM + 1 22.3.
PAGE 1492
Controller Area Network (CAN) Module priority. Among the message interrupts, the message object's interrupt with the lowest message number has the highest priority. A message interrupt is cleared by clearing the message object's INTPND bit in the CANIFnMCTL register or by reading the CAN Status (CANSTS) register. The status Interrupt is cleared by reading the CANSTS register. The interrupt identifier INTID in the CANINT register indicates the cause of the interrupt.
PAGE 1493
Tiva™ TM4C129ENCPDT Microcontroller 22.3.13.2 Loopback Mode Loopback mode is useful for self-test functions. In Loopback Mode, the CAN Controller internally routes the CANnTX signal on to the CANnRX signal and treats its own transmitted messages as received messages and stores them (if they pass acceptance filtering) into the message buffer. The CAN Controller is put in Loopback Mode by setting the LBACK bit in the CANTST register.
PAGE 1494
Controller Area Network (CAN) Module The last two functions, combined with the readable CAN receive pin CANnRX, can be used to check the physical layer of the CAN bus. The Transmit Control function is enabled by programming the TX[1:0] field in the CANTST register. The three test functions for the CANnTX signal interfere with all CAN protocol functions. TX[1:0] must be cleared when CAN message transfer or Loopback Mode, Silent Mode, or Basic Mode are selected. 22.3.
PAGE 1495
Tiva™ TM4C129ENCPDT Microcontroller Figure 22-4. CAN Bit Time Nominal CAN Bit Time a b TSEG1 Sync Prop TSEG2 Phase1 c 1 Time Quantum q) (tq Phase2 Sample Point a. TSEG1 = Prop + Phase1 b. TSEG2 = Phase2 c. Phase1 = Phase2 or Phase1 + 1 = Phase2 a Table 22-3. CAN Protocol Ranges Parameter Range Remark BRP [1 .. 64] Defines the length of the time quantum tq. The CANBRPE register can be used to extend the range to 1024.
PAGE 1496
Controller Area Network (CAN) Module unit of the bit time; the bit timing logic (configured by TSEG1, TSEG2, and SJW) defines the number of time quanta in the bit time. The processing of the bit time, the calculation of the position of the sample point, and occasional synchronizations are controlled by the CAN controller and are evaluated once per time quantum. The CAN controller translates messages to and from frames.
PAGE 1497
Tiva™ TM4C129ENCPDT Microcontroller − )df × fnom ≤ fosc + )df × fnom (1 −(1df × )fnom ≤ fosc ≤ (1≤ +(1df × )fnom (Phase _ seg 1, Phase _ seg 2) min (Phase _ seg 1, Phase _ seg 2) min df df ≤ ≤ 2 × (13 × tbit − Phase _ Seg 2) 2 × (13 × tbit − Phase _ Seg 2) × df × fnom df df maxmax = 2=× 2df × fnom where: ■ Phase1 and Phase2 are from Table 22-3 on page 1495 ■ tbit = Bit Time ■ dfmax = Maximum difference between two oscillators If more than one configuration is possible, that configuration allowing the high
PAGE 1498
Controller Area Network (CAN) Module tTSeg1 = tProp + tPhase1 tTSeg1 = (2 * tq) + (1 * tq) tTSeg1 = 3 * tq tTSeg2 = tPhase2 tTSeg2 = (Information Processing Time + 1) * tq tTSeg2 = 1 * tq \\Assumes IPT=0 tSJW = 1 * tq \\Least of 4, Phase1 and Phase2 In the above example, the bit field values for the CANBIT register are: = TSeg2 -1 TSEG2 = 1-1 =0 = TSeg1 -1 TSEG1 = 3-1 =2 = SJW -1 SJW = 1-1 =0 = Baud rate prescaler - 1 BRP = 5-1 =4 The final value programmed into the CANBIT register = 0x0204.
PAGE 1499
Tiva™ TM4C129ENCPDT Microcontroller tTSeg1 tTSeg1 tTSeg1 tTSeg2 tTSeg2 tTSeg2 = = = = = = tProp + tPhase1 (1 * tq) + (4 * tq) 5 * tq tPhase2 (Information Processing Time + 4) × tq 4 * tq \\Assumes IPT=0 tSJW = 4 * tq \\Least of 4, Phase1, and Phase2 = TSeg2 -1 TSEG2 = 4-1 =3 = TSeg1 -1 TSEG1 = 5-1 =4 = SJW -1 SJW = 4-1 =3 = Baud rate prescaler - 1 BRP = 50-1 =49 The final value programmed into the CANBIT register = 0x34F1. 22.4 Register Map Table 22-5 on page 1499 lists the registers.
PAGE 1500
Controller Area Network (CAN) Module Table 22-5. CAN Register Map (continued) Description See page 0x0000.0000 CAN IF1 Command Mask 1514 RW 0x0000.FFFF CAN IF1 Mask 1 1517 CANIF1MSK2 RW 0x0000.FFFF CAN IF1 Mask 2 1518 0x030 CANIF1ARB1 RW 0x0000.0000 CAN IF1 Arbitration 1 1520 0x034 CANIF1ARB2 RW 0x0000.0000 CAN IF1 Arbitration 2 1521 0x038 CANIF1MCTL RW 0x0000.0000 CAN IF1 Message Control 1523 0x03C CANIF1DA1 RW 0x0000.
PAGE 1501
Tiva™ TM4C129ENCPDT Microcontroller the Message RAM: CANIF1x and CANIF2x. The function of the two sets are identical and are used to queue transactions.
PAGE 1502
Controller Area Network (CAN) Module Register 1: CAN Control (CANCTL), offset 0x000 This control register initializes the module and enables test mode and interrupts. The bus-off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting or clearing INIT. If the device goes bus-off, it sets INIT, stopping all bus activities. Once INIT has been cleared by the CPU, the device then waits for 129 occurrences of Bus Idle (129 * 11 consecutive High bits) before resuming normal operations.
PAGE 1503
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 EIE RW 0 Error Interrupt Enable 2 1 0 SIE IE INIT RW RW RW 0 0 1 Description Value Description 0 No error status interrupt is generated.
PAGE 1504
Controller Area Network (CAN) Module Register 2: CAN Status (CANSTS), offset 0x004 Important: This register is read-sensitive. See the register description for details. The status register contains information for interrupt servicing such as Bus-Off, error count threshold, and error types. The LEC field holds the code that indicates the type of the last error to occur on the CAN bus. This field is cleared when a message has been transferred (reception or transmission) without error.
PAGE 1505
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 5 EPASS RO 0 4 RXOK RW 0 Description Error Passive Value Description 0 The CAN module is in the Error Active state, that is, the receive or transmit error count is less than or equal to 127. 1 The CAN module is in the Error Passive state, that is, the receive or transmit error count is greater than 127.
PAGE 1506
Controller Area Network (CAN) Module Bit/Field Name Type Reset 2:0 LEC RW 0x0 Description Last Error Code This is the type of the last error to occur on the CAN bus. Value Description 0x0 No Error 0x1 Stuff Error More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 0x2 Format Error A fixed format part of the received frame has the wrong format. 0x3 ACK Error The message transmitted was not acknowledged by another node.
PAGE 1507
Tiva™ TM4C129ENCPDT Microcontroller Register 3: CAN Error Counter (CANERR), offset 0x008 This register contains the error counter values, which can be used to analyze the cause of an error. CAN Error Counter (CANERR) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x008 Type RO, reset 0x0000.
PAGE 1508
Controller Area Network (CAN) Module Register 4: CAN Bit Timing (CANBIT), offset 0x00C This register is used to program the bit width and bit quantum. Values are programmed to the system clock frequency. This register is write-enabled by setting the CCE and INIT bits in the CANCTL register. See “Bit Time and Bit Rate” on page 1494 for more information. CAN Bit Timing (CANBIT) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x00C Type RW, reset 0x0000.
PAGE 1509
Tiva™ TM4C129ENCPDT Microcontroller Register 5: CAN Interrupt (CANINT), offset 0x010 This register indicates the source of the interrupt. If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt with the highest priority, disregarding the order in which the interrupts occurred. An interrupt remains pending until the CPU has cleared it. If the INTID field is not 0x0000 (the default) and the IE bit in the CANCTL register is set, the interrupt is active.
PAGE 1510
Controller Area Network (CAN) Module Register 6: CAN Test (CANTST), offset 0x014 This register is used for self-test and external pin access. It is write-enabled by setting the TEST bit in the CANCTL register. Different test functions may be combined, however, CAN transfers are affected if the TX bits in this register are not zero. CAN Test (CANTST) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x014 Type RW, reset 0x0000.
PAGE 1511
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 LBACK RW 0 3 2 1:0 SILENT BASIC reserved RW RW RO 0 0 0x0 Description Loopback Mode Value Description 0 Loopback mode is disabled. 1 Loopback mode is enabled. In loopback mode, the data from the transmitter is routed into the receiver. Any data on the receive input is ignored. Silent Mode Value Description 0 Silent mode is disabled. 1 Silent mode is enabled.
PAGE 1512
Controller Area Network (CAN) Module Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 This register is used to further divide the bit time set with the BRP bit in the CANBIT register. It is write-enabled by setting the CCE bit in the CANCTL register. CAN Baud Rate Prescaler Extension (CANBRPE) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x018 Type RW, reset 0x0000.
PAGE 1513
Tiva™ TM4C129ENCPDT Microcontroller Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 A message transfer is started as soon as there is a write of the message object number to the MNUM field when the TXRQST bit in the CANIF1MCTL register is set. With this write operation, the BUSY bit is automatically set to indicate that a transfer between the CAN Interface Registers and the internal message RAM is in progress.
PAGE 1514
Controller Area Network (CAN) Module Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 Reading the Command Mask registers provides status for various functions. Writing to the Command Mask registers specifies the transfer direction and selects which buffer registers are the source or target of the data transfer.
PAGE 1515
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 5 ARB RW 0 4 3 CONTROL CLRINTPND RW RW 0 0 Description Access Arbitration Bits Value Description 0 Arbitration bits unchanged. 1 Transfer ID + DIR + XTD + MSGVAL of the message object into the Interface registers. Access Control Bits Value Description 0 Control bits unchanged. 1 Transfer control bits from the CANIFnMCTL register into the Interface registers.
PAGE 1516
Controller Area Network (CAN) Module Bit/Field Name Type Reset 1 DATAA RW 0 Description Access Data Byte 0 to 3 The function of this bit depends on the configuration of the WRNRD bit. Value Description 0 Data bytes 0-3 are unchanged. 1 If WRNRD is clear, transfer data bytes 0-3 in CANIFnDA1 and CANIFnDA2 to the message object. If WRNRD is set, transfer data bytes 0-3 in message object to CANIFnDA1 and CANIFnDA2.
PAGE 1517
Tiva™ TM4C129ENCPDT Microcontroller Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 The mask information provided in this register accompanies the data (CANIFnDAn), arbitration information (CANIFnARBn), and control information (CANIFnMCTL) to the message object in the message RAM. The mask is used with the ID bit in the CANIFnARBn register for acceptance filtering. Additional mask information is contained in the CANIFnMSK2 register.
PAGE 1518
Controller Area Network (CAN) Module Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C This register holds extended mask information that accompanies the CANIFnMSK1 register. CAN IFn Mask 2 (CANIFnMSK2) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x02C Type RW, reset 0x0000.
PAGE 1519
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset Description 12:0 MSK RW 0xFF Identifier Mask When using a 29-bit identifier, these bits are used for bits [28:16] of the ID. The MSK field in the CANIFnMSK1 register are used for bits [15:0] of the ID. When using an 11-bit identifier, MSK[12:2] are used for bits [10:0] of the ID. Value Description 0 The corresponding identifier field (ID) in the message object cannot inhibit the match in acceptance filtering.
PAGE 1520
Controller Area Network (CAN) Module Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 These registers hold the identifiers for acceptance filtering. CAN IFn Arbitration 1 (CANIFnARB1) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x030 Type RW, reset 0x0000.
PAGE 1521
Tiva™ TM4C129ENCPDT Microcontroller Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 These registers hold information for acceptance filtering. CAN IFn Arbitration 2 (CANIFnARB2) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x034 Type RW, reset 0x0000.
PAGE 1522
Controller Area Network (CAN) Module Bit/Field Name Type Reset 13 DIR RW 0 12:0 ID RW 0x000 Description Message Direction Value Description 0 Receive. When the TXRQST bit in the CANIFnMCTL register is set, a remote frame with the identifier of this message object is received. On reception of a data frame with matching identifier, that message is stored in this message object. 1 Transmit.
PAGE 1523
Tiva™ TM4C129ENCPDT Microcontroller Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 This register holds the control information associated with the message object to be sent to the Message RAM. CAN IFn Message Control (CANIFnMCTL) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x038 Type RW, reset 0x0000.
PAGE 1524
Controller Area Network (CAN) Module Bit/Field Name Type Reset 12 UMASK RW 0 11 10 9 8 TXIE RXIE RMTEN TXRQST RW RW RW RW 0 0 0 0 Description Use Acceptance Mask Value Description 0 Mask is ignored. 1 Use mask (MSK, MXTD, and MDIR bits in the CANIFnMSKn registers) for acceptance filtering. Transmit Interrupt Enable Value Description 0 The INTPND bit in the CANIFnMCTL register is unchanged after a successful transmission of a frame.
PAGE 1525
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 7 EOB RW 0 Description End of Buffer Value Description 0 Message object belongs to a FIFO Buffer and is not the last message object of that FIFO Buffer. 1 Single message object or last message object of a FIFO Buffer. This bit is used to concatenate two or more message objects (up to 32) to build a FIFO buffer. For a single message object (thus not belonging to a FIFO buffer), this bit must be set.
PAGE 1526
Controller Area Network (CAN) Module Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 These registers contain the data t
PAGE 1527
Tiva™ TM4C129ENCPDT Microcontroller Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 The CANTXRQ1 and CANTXRQ2 registers hold the TXRQST bits of the 32 message objects. By reading out these bits, the CPU can check which message object has a transmission request pending.
PAGE 1528
Controller Area Network (CAN) Module Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 The CANNWDA1 and CANNWDA2 registers hold the NEWDAT bits of the 32 message objects. By reading these bits, the CPU can check which message object has its data portion updated.
PAGE 1529
Tiva™ TM4C129ENCPDT Microcontroller Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 The CANMSG1INT and CANMSG2INT registers hold the INTPND bits of the 32 message objects. By reading these bits, the CPU can check which message object has an interrupt pending.
PAGE 1530
Controller Area Network (CAN) Module Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 The CANMSG1VAL and CANMSG2VAL registers hold the MSGVAL bits of the 32 message objects. By reading these bits, the CPU can check which message object is valid. The message valid bit of a specific message object can be changed with the CANIFnARB2 register.
PAGE 1531
Tiva™ TM4C129ENCPDT Microcontroller 23 Ethernet Controller The Ethernet Controller has the following features: ■ Conforms to the IEEE 802.3 specification – 10BASE-T/100BASE-TX IEEE-802.3 compliant – Supports 10/100 Mbps data transmission rates – Supports full-duplex and half-duplex (CSMA/CD) operation – Supports flow control and back pressure – Full-featured and enhanced auto-negotiation – Supports IEEE 802.
PAGE 1532
Ethernet Controller – Round-robin or fixed priority arbitration between TX/RX – Descriptors support up to 8 kB transfer blocks size – Programmable interrupts for flexible system implementation ■ Physical media manipulation – MDI/MDI-X cross-over support – Register-programmable transmit amplitude – Automatic polarity correction and 10BASE-T signal reception 23.
PAGE 1533
Tiva™ TM4C129ENCPDT Microcontroller Table 23-1. Ethernet Signals (128TQFP) Pin Name Pin Number Pin Mux / Pin Assignment Pin Type Buffer Type Description EN0LED0 42 63 PF0 (5) PK4 (5) O TTL Ethernet 0 LED 0. EN0LED1 46 61 PF4 (5) PK6 (5) O TTL Ethernet 0 LED 1. EN0LED2 43 62 PF1 (5) PK5 (5) O TTL Ethernet 0 LED 2. EN0PPS 49 116 PG0 (5) PJ0 (5) O TTL Ethernet 0 Pulse-Per-Second (PPS) Output. EN0RXIN 53 fixed I/O TTL Ethernet PHY negative receive differential input.
PAGE 1534
Ethernet Controller Figure 23-2. Ethernet MAC and PHY Clock Structure Tiva Cortex-M4 Microcontroller Ethernet MAC Internal PHY TX EN0TXOP EN0TXON EN0RXIP Gated SYSCLK PTPCEN MAC Control / Status Registers EMACCC RX EN0INTRN EN0RXIN RBIAS EN0MDC EN0LED0 EN0MDIO EN0LED1 PTP_REFCLK EN0LED2 MOSC 25 MHz 23.3.2 DMA Controller The Ethernet Controller's integrated DMA is used to optimize data transfer between the MAC and system SRAM memory. The DMA has independent transmit and receive engines.
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Tiva™ TM4C129ENCPDT Microcontroller until the specified length is completed. The Ethernet controller can be programmed to interrupt the CPU in situations such as Frame Transmit and Receive transfer completion, and other normal/error conditions. The integrated Ethernet DMA communicates through two data structures: ■ Control and Status registers ■ Descriptor lists and data buffers.
PAGE 1536
Ethernet Controller equal to the size of the configured PBL in the EMACDMABUSMOD register. Thus, all subsequent transfers start at an address that is aligned to the configured PBL. The DMA can only align the address for burst transfers up to size 16 because only bursts of 16 are supported. 23.3.2.2 Data Buffer Alignment The transmit and receive data buffers do not have any restrictions on the start address alignment.
PAGE 1537
Tiva™ TM4C129ENCPDT Microcontroller 23.3.2.4 DMA Arbiter The arbiter inside the DMA module performs the arbitration between the Transmit and Receive channel accesses. The DMA can be configured to arbitrate in a round-robin or fixed-priority configuration. When the DA bit of the EMACDMABUSMOD register is clear, the DMA arbiter allocates the data bus in the ratio set by the PR bit field of the EMACDMABUSMOD register when both the TX and RX DMA request access at the same time.
PAGE 1538
Ethernet Controller Figure 23-3.
PAGE 1539
Tiva™ TM4C129ENCPDT Microcontroller Table 23-2. Enhanced Transmit Descriptor 0 (TDES0) (continued) Bit 29 Description LS: Last Segment When set, this bit indicates that the buffer contains the last segment of the frame. When this bit is set, the TBS1 or TBS2 field in TDES1 should have a non-zero value. 28 FS: First Segment When set, this bit indicates that the buffer contains the first segment of a frame.
PAGE 1540
Ethernet Controller Table 23-2. Enhanced Transmit Descriptor 0 (TDES0) (continued) Bit 19:18 Description VLIC: VLAN Insertion Control When set, these bits request the MAC to perform VLAN tagging or untagging before transmitting the frames. If the frame is modified for VLAN tags, the MAC automatically recalculates and replaces the CRC bytes. The values of this field are as follows: 17 ■ 0x0= Do not add a VLAN tag ■ 0x1= Remove the VLAN tag from the frames before transmission.
PAGE 1541
Tiva™ TM4C129ENCPDT Microcontroller Table 23-2. Enhanced Transmit Descriptor 0 (TDES0) (continued) Bit 11 Description LC: Loss of Carrier When set, this bit indicates that Loss of Carrier occurred during frame transmission. This is valid only for the frames transmitted without collision and when the MAC operates in half-duplex mode. 10 NC: No Carrier When set, this bit indicates that the carrier sense signal form the PHY was not asserted during transmission.
PAGE 1542
Ethernet Controller Table 23-3. Enhanced Transmit Descriptor 1 (TDES1) (continued) Bit Description 28:16 TBS2: Transmit Buffer 2 Size This field indicates the second data buffer size in bytes. This field is not valid if TDES0[20] is set. 15:13 Reserved 12:0 TBS1: Transmit Buffer 1 Size These bits indicate the first data buffer byte size, in bytes. If this field is 0, the DMA ignores this buffer and uses Buffer 2 or the next descriptor, depending on the value of TCH (TDES0[20]). Table 23-4.
PAGE 1543
Tiva™ TM4C129ENCPDT Microcontroller register, offset 0xC00, so that the DMA operates with extended descriptor size. When this control bit is reset to the default (0), the TDES4-TDES7 descriptor space is not valid and only Alternate Descriptors are available, with a default size of 16 bytes (4 words). Figure 23-4.
PAGE 1544
Ethernet Controller Table 23-8. Enhanced Receive Descriptor 0 (RDES0) (continued) Bit 29:16 Description FL: Frame Length These bits indicate the byte length of the received frame that was transferred to the system memory. This field is valid when the Last Descriptor (RDES0[8]) is set and either the Descriptor Error (RDES0[14]) or the Overflow Error bit (RDES0[11]) is clear.
PAGE 1545
Tiva™ TM4C129ENCPDT Microcontroller Table 23-8. Enhanced Receive Descriptor 0 (RDES0) (continued) Bit 7 Description Timestamp Available or Giant Frame When Advanced Timestamp feature is enabled, this bit indicates that a snapshot of the Timestamp is written in descriptor words 6 (RDES6) and 7 (RDES7). This is valid only when the Last Descriptor bit (RDES0[8]) is set. Otherwise, this bit, when set, indicates the Giant Frame Status.
PAGE 1546
Ethernet Controller Table 23-10. Enhanced Receive Descriptor 1 (RDES1) Bit 31 Description Disable Interrupt on Completion When set, this bit prevents the setting of the Receive Interrupt (RI) bit in the EMACDMARIS register and prevents the receive interrupt from being asserted. 30:29 Reserved 28:16 RBS2: Receive Buffer 2 Size These bits indicate the second data buffer size. The buffer size must be a multiple of 4, even if the value of RDES3 (buffer 2 address pointer) is not aligned to the bus width.
PAGE 1547
Tiva™ TM4C129ENCPDT Microcontroller Table 23-13. Enhanced Received Descriptor 4 (RDES4) (continued) Bit 14 Description Timestamp Dropped When set, this bit indicates that the timestamp was captured for this frame but got dropped in the RX FIFO because of overflow. 13 PTP Version When set, this bit indicates that the received PTP message uses the IEEE 1588 version 2 format. When reset, it uses the version 1 format.
PAGE 1548
Ethernet Controller Table 23-13. Enhanced Received Descriptor 4 (RDES4) (continued) Bit 2:0 Description IP Payload Type These bits indicate the type of payload encapsulated in the IP datagram processed by the Receive Checksum Offload Engine (COE). The COE sets this field to 0x0 if it does not process the IP datagram's payload due to an IP header error or fragmented IP packet.
PAGE 1549
Tiva™ TM4C129ENCPDT Microcontroller 4. If the acquired descriptor is flagged as owned by the DMA (TDES0[31]=1), the DMA decodes the transmit data buffer address from the acquired descriptor. 5. If the acquired descriptor is flagged as owned by DMA (TDES0[31] = 1), the DMA decodes the Transmit Data Buffer address from the acquired descriptor. 6. The DMA fetches the transmit data from system memory and transfers the data to the TX/RX Controller for transmission. 7.
PAGE 1550
Ethernet Controller Figure 23-5.
PAGE 1551
Tiva™ TM4C129ENCPDT Microcontroller for the second frame. If the second frame is valid, the transmit process transfers this frame before writing the first frame's status information. In Operate on Second Frame (OSF) mode, the RUN state TX DMA operates in the following sequence: 1. The DMA operates as described in Steps 1 to 6 (see page 1548). 2. Without closing the previous frame's last descriptor, the DMA fetches the next descriptor. 3.
PAGE 1552
Ethernet Controller Figure 23-6.
PAGE 1553
Tiva™ TM4C129ENCPDT Microcontroller respectively. The First Descriptor bit is located at TDES0[28] and the Last Descriptor is located at TDES0[29]. As transmission starts, the First Descriptor must have TDES0[28] set. When this occurs, frame data transfers from the host memory buffer to the TX FIFO. Concurrently, if the current frame has the Last Segment Descriptor (TDES0[29]) clear, the transmit process attempts to acquire the next descriptor.
PAGE 1554
Ethernet Controller 3. The DMA decodes the receive data buffer address from the acquired descriptors. 4. Incoming frames are processed and placed in the acquired descriptor's data buffers. 5. When the buffer is full or the frame transfer is complete, the RX DMA engine fetches the next descriptor. 6. If the current frame transfer is complete, the DMA proceeds to Step 7.
PAGE 1555
Tiva™ TM4C129ENCPDT Microcontroller Figure 23-7.
PAGE 1556
Ethernet Controller ■ The SR bit of the EMACDMAOPMODE register has been set immediately after being placed in the RUN state. ■ The data buffer or current descriptor is full before the frame ends for the current transfer. ■ The controller has completed frame reception, but the current receive descriptor is not yet closed. ■ The receive process has been suspended because of a host-owned buffer (RDES0[31]=0) and a new frame is received. ■ A receive poll demand has been issued.
PAGE 1557
Tiva™ TM4C129ENCPDT Microcontroller ■ Normal Interrupts: – Transmit Interrupt (TI, bit 0): Indicates that frame transmission is complete. – Transmit Buffer Unavailable (TU, bit 2): Indicates the CPU owns the next descriptor in the transmit list and the DMA cannot acquire it. – Receive Interrupt (RI, bit 6): Indicates the frame reception is complete.
PAGE 1558
Ethernet Controller if the corresponding RI bit is enabled in the EMACDMAIM register. This counter gets disabled before it runs out if a frame is transferred to memory and the RI bit is set because it is enabled for that descriptor. 23.3.2.9 DMA Bus Error If an internal bus error occurs during a DMA transfer, the fatal bus error (FBI) interrupt is set in the EMACDMARIS register and the Access Error status (AE) bit field in the EMACDMARIS register indicates the type of error that caused the bus error.
PAGE 1559
Tiva™ TM4C129ENCPDT Microcontroller Transmit Operation During a transmit, single-packet or double-packets can reside in the buffer. The following describes the details of each: ■ Single-packet transmit: During single packet transmission, the DMA controller fetches data from the CPU memory and forwards it to the TX FIFO and continues to receive data until the end-of-frame is transferred.
PAGE 1560
Ethernet Controller the frames that were flushed and then clears the TX FIFO Flush control (FTF) bit in the EMACDMAOPMODE register. At this point, the TX/RX Controller starts accepting new frames from the DMA. Transmit Status Word At the end of the transfer of the Ethernet frame to the MAC and after the MAC completes the transmission of the frame, the TX/RX delivers a transmit status word (TDES0) to the application.
PAGE 1561
Tiva™ TM4C129ENCPDT Microcontroller Error Handling If the RX FIFO is full before it receives the EOF data from the MAC, an overflow is declared, the entire frame (including the status word) is dropped and the Ethernet MAC Missed Frame and Buffer Overflow Counter (EMACMFBOC) register is incremented. These error actions occur even if the FEF bit is set in the EMACDMAPOPMODE register.
PAGE 1562
Ethernet Controller Table 23-17. RX MAC Flow Control (continued) 23.3.4 TFE bit in EMACFLOWCTL DUPM bit in EMACCFG Description 1 1 The MAC receiver detects or processes the Pause frames and responds to such frames by stopping the MAC transmitter. MAC Operation The MAC module enables the CPU to transmit and receive data over Ethernet in compliance with the IEEE 802.3-2008 standard.
PAGE 1563
Tiva™ TM4C129ENCPDT Microcontroller When a new frame transmission is requested, the MAC transmit module sends out a preamble and SFD, followed by the data in the TX FIFO. The preamble is defined as 7 bytes of 0xAA and the SFD is defined as 1 byte of 0xAB pattern. The collision window is defined as 1 slot time (512-bit times). If a collision occurs any time from the beginning of the frame to the end of the CRC field, the MAC transmit module sends a 32-bit jam pattern of 0x5555.
PAGE 1564
Ethernet Controller ■ Frame data and status buffering for received frames ■ Data path conversion of 8-bit data to 32-bit data ■ Frame filtering ■ Attaching calculated IP checksum input to frame ■ Detecting receiving pause frames and pausing the frame transmission for the delay specified withing the received pause frame ■ Receive IP Checksum Verification ■ Performing destination and source address checking functions on all received frames and reporting the address filtering status to the receive frame contr
PAGE 1565
Tiva™ TM4C129ENCPDT Microcontroller Figure 23-8. Networked Time Synchronization Master Clock Time Slave Clock Time t1 Sync message t2m Data at Slave Clock t2 t2 Follow_Up message containing value of t1 t1, t2 t3m t3 t1, t2, t3 Delay_Req message t4 Delay Resp message containing value of t4 t1, t2, t3, t4 time As shown in Figure 23-8 on page 1565, the PTP uses the following process: 1. The master broadcasts the PTP Sync messages to all its nodes.
PAGE 1566
Ethernet Controller MAC. This timing information is captured and returned to the software for the proper implementation of PTP with high accuracy. 23.3.5.1 System Time Module The System Time module maintains a 64-bit time and is updated using the MOSC clock source as the PTP clock reference. This time is the source for taking snapshots (timestamps) of the Ethernet frames being transmitted or received. Two methods of updating the system time counter are implemented.
PAGE 1567
Tiva™ TM4C129ENCPDT Microcontroller Figure 23-9. System Time Update Using Fine Correction Method EMACTIMADD EMACTIMSTCTRL. ADDREGUP + Accumulator Register Constant Value + Increment the Sub-Seconds Register EMACTIMNANO Increment the Seconds Register EMACTIMSEC Note: The MOSC clock that feeds the PTP reference clock to the System Time Module must be 25 MHz because it is also clocks the integrated PHY module.
PAGE 1568
Ethernet Controller 1. At time MasterSyncTimen the master sends the slave clock a Sync message. The slave receives this message when its local clock is SlaveClockTimen and computes MasterClockTimen as: MasterClockTimen = MasterSyncTimen + MasterToSlaveDelayn 2. The master clock count, MasterClockCountn, for the current Sync cycle is given by: MasterClockCountn = MasterClockTimen - MasterClockTimen-1 This assumes that the MasterToSlaveDelay is the same for Sync cycles n and n-1. 3.
PAGE 1569
Tiva™ TM4C129ENCPDT Microcontroller 23.3.5.4 Timestamp Error Margin According to the IEEE 1588 specifications, a timestamp must be captured at the SFD of the transmitted and received frames at the MAC interface. Because the reference timing source, MOSC, is taken as different from MAC reference clocks, a small error margin is introduced, because of the transfer of information across asynchronous clock domains.
PAGE 1570
Ethernet Controller Figure 23-10. Propagation Delay Calculation in Clocks Supporting Peer-to-Peer Path Correction P2P TC A Delay Requester Time P2P TC B Delay Responder Time Timestamps known by Delay Requester t1 t1 Pdelay_Req tAB t2 t3 tBA t4 Pdelay_Resp Pdelay_Resp_Follow_Up: t2, t3 t1 ,t4 t1, t2, t3, t4 As shown in Figure 23-10 on page 1570, the propagation delay is calculated in the following way: 1. Port-1 issues a Pdelay_Req message and generates a timestamp, t1, for the Pdelay_Req message.
PAGE 1571
Tiva™ TM4C129ENCPDT Microcontroller ■ Sending and receiving of PTP messages. The timestamp snapshot can be controlled through the Ethernet MAC Timestamp Control (EMACTIMSTCTRL) register, offset 0x700. Timestamp snapshots can be for Sync messages. ■ Maintaining the data sets such as timestamp values. For an ordinary clock, snapshots can be taken of either version 1 or version 2 PTP types but not both. Selecting between the two is controlled by the PTPVER2 bit of the EMACTIMSTCTRL register.
PAGE 1572
Ethernet Controller Fixed Pulse-Per-Second Output The Ethernet MAC module supports a pulse-per-second output feature such that the signal, EN0PPS, can indicate one second intervals. The frequency of the EN0PPS output can be changed by setting the PPSCTRL bit field of the Ethernet MAC PPS Control (EMACPPSCTRL) register, offset 0x72C.
PAGE 1573
Tiva™ TM4C129ENCPDT Microcontroller When you enable the advanced timestamp feature, the structure of the descriptor changes. The advanced timestamp feature is supported only through the enhanced descriptors format. The descriptor is 32-bytes long (eight words) and the snapshot of the timestamp is written in descriptor TDES6 and TDES7. Advanced Timestamp Receive Path Functions When the advanced timestamp feature is enabled, the MAC processes the received frames to identify valid PTP frames.
PAGE 1574
Ethernet Controller The MAC provides VLAN tag hash filtering with a 16-bit Hash table. The MAC performs the VLAN hash matching based on the VTHM bit of the EMACVLANTG register. If the VTHM bit is set, the most significant four bits of VLAN tag's CRC-32 are used to index the content of the Ethernet MAC VLAN Hash Table (EMACVLANHASH) register, offset 0x588.
PAGE 1575
Tiva™ TM4C129ENCPDT Microcontroller ■ Insert the content of the MAC Address Registers in the SA field. ■ Replace the content of the SA field with the content of the MAC Address Registers. The software can enable the SA insertion or replacement for all transmitted frames or selective frames: ■ To enable SA insertion or replacement feature for all frames, program the SADDR field of the Ethernet MAC Configuration (EMACCFG) register.
PAGE 1576
Ethernet Controller Table 23-19. CRC Replacement Based on Bit 27 and Bit 24 of TDES0 Bit 27 (DC) Bit 24 (CRCR) 0 X Description Append CRC When DC= 0, the MAC appends the computed CRC irrespective of the CRCR setting. 23.3.8 1 1 Replace CRC 1 0 No operation (user has appended CRC) Checksum Offload Engine Communication protocols such as TCP and UDP implement checksum fields, which help determine the integrity of data transmitted over a network.
PAGE 1577
Tiva™ TM4C129ENCPDT Microcontroller – The Ethernet type is 0x86dd but the IP header Version field is not equal to 0x6. – The frame ends before the IPv6 header (40 bytes) or extension header (as given in the corresponding Header Length field in an extension header) is completely received. If the checksum offload engine detects an IP header error, it still inserts an IPv4 header checksum if the Ethernet Type field indicates an IPv4 payload. 23.3.8.
PAGE 1578
Ethernet Controller 23.3.10 Power Management Module The power management (PMT) module supports the reception of network remote wake-up frames and AMD Magic Packet™ frames. The PMT module does not perform the clock gate function, but generates interrupts for remote wake-up frames and magic packets that the MAC receives.
PAGE 1579
Tiva™ TM4C129ENCPDT Microcontroller ■ Filter n Command Bit 3 specifies the address type of the pattern. When the bit is set, the pattern applies to only multicast frames; when the bit is reset, the pattern applies only to unicast frame. ■ Filter n Command Bit 2 and Bit 1 are reserved. ■ Filter n Command Bit 0 is the enable for Filter n. If bit 0 is not set, filter n is disabled. Filter n Offset The Filter n Offset register defines the offset (within the frame) from which the filter n examines the frames.
PAGE 1580
Ethernet Controller scans the 0xFFFF.FFFF.FFFF pattern in the incoming frame. The 16 repetitions can be anywhere in the frame, but must be preceded by the synchronization stream (0xFFFF.FFFF.FFFF). The device can also accept a multicast frame, as long as the 16 duplications of the MAC address are detected. If the MAC address of a node is 0x0011.2233.4455, then the MAC scans for the following data sequence: Destination Address Source Address ………………..
PAGE 1581
Tiva™ TM4C129ENCPDT Microcontroller 23.3.11 Serial Management Interface The Ethernet MAC has the ability to program the integrated PHY through internal serial MDIO and MDC signals. The MDC signal is a 2.5 MHz clock that is sourced from system clock and then divided down to the required frequency by programming the CR field in the Ethernet MAC MII Address (EMACMIIADDR) register. To access the integrated PHY, the PLA field in the EMACMIIADDR register must be 0x0. 23.3.
PAGE 1582
Ethernet Controller Figure 23-12. Integrated PHY Diagram TRANSMIT BLOCK TX 10BASE-T and 100BASE-TX 25 MHz MOSC Cable Diagnostics DAC EN0TXOP / EN0TXON AutoNegotiation State Machine Clock Generation Auto MDIX EN0RXIP / EN0RXIN RECEIVE BLOCK RX 10BASE-T and 100BASE-TX EN0MDC EN0MDIO 23.4.2 Serial Management Interface PHY Registers ADC Extended PHY Registers LED Drivers EN0LEDn Functional Description The following sections describe the functional characteristics of the integrated PHY. 23.
PAGE 1583
Tiva™ TM4C129ENCPDT Microcontroller Table 23-21. Advertised Mode Configurations 23.4.2.2 ANEN value ANMODE Advertised Mode 1 0x0 10Base-T, Half/Full-Duplex 1 0x1 100Base-TX, Half/Full-Duplex 1 0x2 10Base-T, Half Duplex 100Base-TX, Half Duplex 1 0x3 10Base-T, Half/Full-Duplex 100Base-TX, Half/Full-Duplex Auto-MDIX The PHY automatically determines whether or not it needs to cross over between pairs so that an external crossover cable is not required.
PAGE 1584
Ethernet Controller At reset, LED0 is initialized to display Link OK and LED1 and LED 2 are initialized to the RX/TX activity encoding. The blink rate of the LEDs can be set by programming the BLINKRATE bit field of the Ethernet PHY LED Control - MR24 (EPHYLEDCR) register, address 0x018 23.4.2.5 PHY Address The integrated PHY's address is 0x00.
PAGE 1585
Tiva™ TM4C129ENCPDT Microcontroller The following sections describe how to perform operations on the extended register set using the EPHYREGCTL and EPHYADDAR registers. Write to PHY Registers The following describes the steps to write to a PHY register. 1. Check the MIIB bit in the EMACMIIADDR register to identify if the MII interface is busy. When the MIIB bit is 0, the MII interface is available to write to the PHY registers. 2.
PAGE 1586
Ethernet Controller 5. The EMACMIIDATA register should be written with the address of the extended register to be accessed. This value is written to the EPHYADDAR register. 6. Initiate write by writing the EMACMIIADDR register fields: ■ PLA: Physical Layer Address of the PHY. The integrated PHY's address is 0x0. ■ MII: Address of the PHY register to be written. In this case, it should be the address of the EPHYADDAR register, 0xE. ■ CR: Clock Reference for the MDIO interface. ■ MIIW: Write Initiation.
PAGE 1587
Tiva™ TM4C129ENCPDT Microcontroller ■ MIIB: MII Busy. This bit is set to 1 to indicate that the MII is now busy with a write operation. The EMAC clears this bit when the write has been transmitted. Read from PHY Registers The following describes the steps to read from an extended PHY register. 1. Check the MIIB bit in the EMACMIIADDR register to identify if the MII interface is busy. When the MIIB bit is 0, the MII interface is available to read to the PHY registers. 2.
PAGE 1588
Ethernet Controller Figure 23-13. Interface to Ethernet Jack 3.3V 3.3V 0.1mF 3.3V 0.1mF 49.9Ω 1% Tiva Cortex-M4 Microcontroller 3.3V 49.9Ω 1% 49.9Ω 1% 49.9Ω 1% HX1188FNL EN0TXOP EN0TXON EN0RXIP EN0RXIN SLVU2.8-4 1 16 1 2 15 3 14 2 6 11 3 7 10 8 9 4 RJ45 – NoMag 8 1 TX+ 2 TX- 7 3 RX+ 6 4 TERM1A 5 TERM1B 6 RX- 7 TERM2A 8 TERM2B 5 RBIAS 75Ω 4.87kΩ 1% 75Ω 75Ω CHASIS 10 CHASIS 9 75Ω 0.1mF 0.1mF 1MΩ 1000pF 2000V 4700pF 2000V NOTE: The 0.
PAGE 1589
Tiva™ TM4C129ENCPDT Microcontroller Descriptor List Address (EMACTXDLADDR) register providing the DMA with the starting address of each list. 4. Write to the Ethernet MAC Frame Filter (EMACFRAMEFLTR) register, the Ethernet MAC Hash Table High (EMACHASHTBLH) and the Ethernet MAC Hash Table Low (EMACHASHTBLL) for desired filtering options. 5. Write to the Ethernet MAC Configuration Register (EMACCFG) to configure the operating mode and enable the transmit operation. 6.
PAGE 1590
Ethernet Controller Table 23-22. EMACPC to PHY Register Mapping (continued) EMACPC Register Bit Corresponding PHY Register Corresponding PHY Bit (Bit No.
PAGE 1591
Tiva™ TM4C129ENCPDT Microcontroller 4. Once the Ethernet PHY Peripheral Ready (PREPHY) register reads 0x0000.0001, software can write the EMACPC register with the required value. 5. After software configuration is complete, the application must set the DONE bit in the Ethernet PHY Configuration 1 (EPHYCFG1) register at offset 0x009. Note: 23.6 If a software reset is asserted to the PHY afterwards through the SREPHY register, the custom configuration is lost and the steps described above must be repeated.
PAGE 1592
Ethernet Controller Table 23-23. Ethernet Register Map (continued) Description See page 0xFFFF.FFFF Ethernet MAC Address 1 Low 1628 RW 0x0000.FFFF Ethernet MAC Address 2 High 1629 EMACADDR2L RW 0xFFFF.FFFF Ethernet MAC Address 2 Low 1631 0x058 EMACADDR3H RW 0x0000.FFFF Ethernet MAC Address 3 High 1632 0x05C EMACADDR3L RW 0xFFFF.FFFF Ethernet MAC Address 3 Low 1634 0x0DC EMACWDOGTO RW 0x0000.0000 Ethernet MAC Watchdog Timeout 1635 0x100 EMACMMCCTRL RW 0x0000.
PAGE 1593
Tiva™ TM4C129ENCPDT Microcontroller Table 23-23. Ethernet Register Map (continued) Description See page 0x0000.0000 Ethernet MAC Target Time Seconds 1668 RW 0x0000.0000 Ethernet MAC Target Time Nanoseconds 1669 EMACHWORDSEC RW 0x0000.0000 Ethernet MAC System Time-Higher Word Seconds 1670 0x728 EMACTIMSTAT RO 0x0000.0000 Ethernet MAC Timestamp Status 1671 0x72C EMACPPSCTRL RW 0x0000.0000 Ethernet MAC PPS Control 1672 0x760 EMACPPS0INTVL RW 0x0000.
PAGE 1594
Ethernet Controller Table 23-23.
PAGE 1595
Tiva™ TM4C129ENCPDT Microcontroller Register 1: Ethernet MAC Configuration (EMACCFG), offset 0x000 The EMACCFG register establishes receive and transmit operating modes. Note that the TWOKPEN bit is only applicable when the JFEN bit is 0. Ethernet MAC Configuration (EMACCFG) Base 0x400E.C000 Offset 0x000 Type RW, reset 0x0000.
PAGE 1596
Ethernet Controller Bit/Field Name Type Reset 27 TWOKPEN RW 0x0 Description IEEE 802.3as Support for 2K Packets When set, the MAC considers all frames, up to 2,000 bytes in length, as normal packets. This bit is only valid when the JFEN bit is set to 0. When JFEN is set, configuring TWOKPEN has no effect on Giant Frame status. Value Description 0 If the JFEN bit is clear, the MAC considers all received frames larger than 1,518 bytes (1,522 byes tagged) as Giant Frames.
PAGE 1597
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset Description 21 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 20 JFEN RW 0x0 Jumbo Frame Enable When this bit is set, the MAC allows jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status.
PAGE 1598
Ethernet Controller Bit/Field Name Type Reset 13 DRO RW 0 Description Disable Receive Own When this bit is set, the MAC disables the reception of frames while transmitting in half-duplex mode. When this bit is clear, the MAC receives all packets that are given by the PHY while transmitting. Value Description 0 All packets are received by MAC. 1 Disable reception of frames. Note: 12 LOOPBM RW 0 This bit is not applicable if the MAC is operating in full-duplex mode.
PAGE 1599
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 9 DR RW 0x0 Description Disable Retry When this bit is set, the MAC attempts only one transmission. When a collision occurs on the MII interface, the MAC ignores the current frame transmission and reports a frame abort with excessive collision error in the transmit frame status. When this bit is cleared, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). Note: This bit is only applicable in half-duplex mode.
PAGE 1600
Ethernet Controller Bit/Field Name Type Reset 4 DC RW 0x0 Description Deferral Check When this bit is set, the deferral check function is enabled in the MAC. When the transmit state machine is deferred for more than 24,288 bit times, the MAC issues a Frame Abort status, and sets the excessive deferral error bit (EXDEFF) in the MAC MMC Transmit Interrupt (EMACMMCTXRIS) Register. If the Jumbo frame mode (JFEN) is enabled, the threshold for deferral is 155,680 bits times.
PAGE 1601
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1:0 PRELEN RW 0x0 Description Preamble Length for Transmit Frames These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.
PAGE 1602
Ethernet Controller Register 2: Ethernet MAC Frame Filter (EMACFRAMEFLTR), offset 0x004 The MAC Frame Filter register contains the filter controls for receiving frames. Some of the controls from this register go to the address check block of the MAC, which performs the first level of address filtering. The second level of filtering is performed on the incoming frame, based on other controls such as Pass Bad Frames and Pass Control Frames. Ethernet MAC Frame Filter (EMACFRAMEFLTR) Base 0x400E.
PAGE 1603
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 10 HPF RW 0 Description Hash or Perfect Filter When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits in this register. When this bit is clear and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter.
PAGE 1604
Ethernet Controller Bit/Field Name Type Reset 7:6 PCF RW 0x0 Description Pass Control Frames These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). Value Description 0x00 The MAC filters all control frames from reaching application. 0x1 MAC forwards all control frames except PAUSE control frames to application even if they fail the address filter. 0x2 MAC forwards all control frames to application even if they fail the address Filter.
PAGE 1605
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3 DAIF RW 0 Description Destination Address (DA) Inverse Filtering When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. Value Description 2 HMC RW 0 0 Normal filtering of frames is performed. 1 Inverse filtering mode is enabled for DA.
PAGE 1606
Ethernet Controller Register 3: Ethernet MAC Hash Table High (EMACHASHTBLH), offset 0x008 The 64-bit Hash table is used for group address filtering. For hash filtering, the contents of the Destination Address (DA) in the incoming frame is passed through the CRC logic, and the upper 6 bits of the CRC register are used to index the contents of the Hash table.
PAGE 1607
Tiva™ TM4C129ENCPDT Microcontroller Register 4: Ethernet MAC Hash Table Low (EMACHASHTBLL), offset 0x00C The MAC Hash Table Low (EMACHASHTBLL) register contains the lower 32 bits of the hash table. Ethernet MAC Hash Table Low (EMACHASHTBLL) Base 0x400E.C000 Offset 0x00C Type RW, reset 0x0000.
PAGE 1608
Ethernet Controller Register 5: Ethernet MAC MII Address (EMACMIIADDR), offset 0x010 The Ethernet MAC MII address (EMACMIIADDR) register controls the management cycles to the PHY through the management interface. Ethernet MAC MII Address (EMACMIIADDR) Base 0x400E.C000 Offset 0x010 Type RW, reset 0x0000.
PAGE 1609
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1 MIIW RW 0x0 Description MII Write Value Description 0 MIIB RW 0x0 0 Read operation is active and read data is placed in the MII Data register (EMACMIIDATA). 1 PHY is notified that this is a write operation using the MII Data Register (EMACMIIDATA). MII Busy Indicates whether the MII is busy with a read or write access. This bit should read logic 0 before writing to the EMACMIIADDR register or the EMACMIIDATA register.
PAGE 1610
Ethernet Controller Register 6: Ethernet MAC MII Data Register (EMACMIIDATA), offset 0x014 The Ethernet MAC MII Data (EMACMIIDATA) register holds data that is written to and read from the PHY register located at the address specified by the PLA and MII bit fields of the Ethernet MAC MII Address (EMACMIIADDR) register. Ethernet MAC MII Data Register (EMACMIIDATA) Base 0x400E.C000 Offset 0x014 Type RW, reset 0x0000.
PAGE 1611
Tiva™ TM4C129ENCPDT Microcontroller Register 7: Ethernet MAC Flow Control (EMACFLOWCTL), offset 0x018 The Ethernet MAC Flow Control (EMACFLOWCTL) register controls the generation and reception of the control (pause command) frames by the MAC's Flow control module. A write to a register with the FCBBPA (bit 0) set to 1 triggers the Flow Control block to generate a pause control frame. The fields of the control frame are selected as specified in the 802.
PAGE 1612
Ethernet Controller Bit/Field Name Type Reset 3 UP RW 0x0 Description Unicast Pause Frame Detect Value Description 2 RFE RW 0x0 0 MAC detects only a Pause frame with the unique multicast address specified in the 802.3x standard. 1 The MAC detects the pause frames with the station's unicast address specified in the EMACADDR0H and EMACADDR0L register, in addition to detecting pause frames with the unique multicast address.
PAGE 1613
Tiva™ TM4C129ENCPDT Microcontroller Register 8: Ethernet MAC VLAN Tag (EMACVLANTG), offset 0x01C The Ethernet MAC VLAN Tag (MACVLANTG) register contains the IEEE 802.1Q VLAN Tag to identify the VLAN frames. The MAC compares the 13th and 14th bytes of the receiving frame (Length/Type) with the value 0x8100, and the following two bytes are compared with the VLAN tag. If a match occurs, the MAC sets the received VLAN bit in the receive frame status.
PAGE 1614
Ethernet Controller Bit/Field Name Type Reset 17 VTIM RW 0 Description VLAN Tag Inverse Match Enable Value Description 16 ETV RW 0 0 VLAN perfect matching is enabled. The frames with matched VLAN tag are marked as matched. 1 VLAN tag inverse matching is enabled. The frames that do not have matching VLAN tag are marked as matched.
PAGE 1615
Tiva™ TM4C129ENCPDT Microcontroller Register 9: Ethernet MAC Status (EMACSTATUS), offset 0x024 The Ethernet MAC Status (EMACSTATUS) register gives the status of all main modules of the transmit and receive data-paths and the FIFOs. An all-zero status indicates that the MAC is in idle state (and FIFOs are empty) and no activity is going on in the data-paths. Ethernet MAC Status (EMACSTATUS) Base 0x400E.C000 Offset 0x024 Type RO, reset 0x0000.
PAGE 1616
Ethernet Controller Bit/Field Name Type Reset 21:20 TRC RO 0x0 Description TX/RX Controller's TX FIFO Read Controller Status This field indicates the state of the TX FIFO read controller: Value Description 19 TXPAUSED RO 0 0x0 IDLE state 0x1 READ state (transferring data to MAC transmitter) 0x2 Waiting for TX Status from MAC transmitter 0x3 Writing the received TX Status or flushing the TX FIFO MAC Transmitter PAUSE Value Description 18:17 TFC RO 0x0 0 MAC transmitter is not in P
PAGE 1617
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 9:8 RXF RO 0x0 Description TX/RX Controller RX FIFO Fill-level Status This field gives the status of the fill-level of the RX FIFO. The FIFO threshold is programmed by the TCC field in the Ethernet MAC DMA Operation Mode (EMACDMAOPMODE) register.
PAGE 1618
Ethernet Controller Register 10: Ethernet MAC Remote Wake-Up Frame Filter (EMACRWUFF), offset 0x028 This is the address through which the application writes or reads the remote wake-up frame filter registers. Note that to load values in the Ethernet MAC Wake-up Frame Filter (EMACRWUFF) register, the entire register must be written. The Ethernet MAC Remote Wake-Up Frame Filter (EMACRWUFF) register is a pointer to eight wake-up frame filter registers.
PAGE 1619
Tiva™ TM4C129ENCPDT Microcontroller Register 11: Ethernet MAC PMT Control and Status Register (EMACPMTCTLSTAT), offset 0x02C The Ethernet MAC PMT Control and Status (EMACPMTCTLSTAT) programs and monitors wake-up events. Ethernet MAC PMT Control and Status Register (EMACPMTCTLSTAT) Base 0x400E.C000 Offset 0x02C Type RW, reset 0x0000.
PAGE 1620
Ethernet Controller Bit/Field Name Type Reset 6 WUPRX RO 0x0 Description Wake-Up Frame Received Value Description 0 No effect. 1 The power management event is generated because of the reception of a wake-up frame. This bit is cleared whenever the register is read. 5 MGKPRX RO 0 Magic Packet Received Value Description 0 No effect. 1 The power management event is generated because of the reception of a magic packet. This bit is cleared whenever the register is read.
PAGE 1621
Tiva™ TM4C129ENCPDT Microcontroller Register 12: Ethernet MAC Raw Interrupt Status (EMACRIS), offset 0x038 The Ethernet MAC Raw Interrupt Status (EMACRIS) register identifies the events in the MAC that can generate interrupt. Ethernet MAC Raw Interrupt Status (EMACRIS) Base 0x400E.C000 Offset 0x038 Type RO, reset 0x0000.
PAGE 1622
Ethernet Controller Bit/Field Name Type Reset 6 MMCTX RO 0 Description MMC Transmit Interrupt Status This bit is cleared when all of the bits in the MAC MMC Transmit Interrupt (EMACMMCTXRIS) register are clear. Value Description 5 MMCRX RO 0 0 No interrupts exist in the MAC MMC Transmit Interrupt (EMACMMCTXRIS) register. 1 Indicates an interrupt has been generated in the MAC MMC Transmit Interrupt (EMACMMCTXRIS) register.
PAGE 1623
Tiva™ TM4C129ENCPDT Microcontroller Register 13: Ethernet MAC Interrupt Mask (EMACIM), offset 0x03C The Ethernet MAC Interrupt Mask (EMACIM) Register bits enables the application to mask the interrupt signal caused by the corresponding event in the Ethernet MAC Raw Interrupt Status (EMACRIS) Register. Ethernet MAC Interrupt Mask (EMACIM) Base 0x400E.C000 Offset 0x03C Type RW, reset 0x0000.
PAGE 1624
Ethernet Controller Register 14: Ethernet MAC Address 0 High (EMACADDR0H), offset 0x040 The Ethernet MAC Address 0 High (EMACADDR0H) register holds the upper 16 bits of the first 6-byte MAC address of the station. The first (Destination Address) DA byte that is received on the MII interface corresponds to the least significant byte (Bits [7:0]) of the MAC Address 0 Low Register (EMACADDR0L) register.
PAGE 1625
Tiva™ TM4C129ENCPDT Microcontroller Register 15: Ethernet MAC Address 0 Low Register (EMACADDR0L), offset 0x044 The MAC Address 0 Low Register (EMACADDR0L) register holds the lower 32 bits of the first 6-byte MAC address of the station. Ethernet MAC Address 0 Low Register (EMACADDR0L) Base 0x400E.C000 Offset 0x044 Type RW, reset 0xFFFF.
PAGE 1626
Ethernet Controller Register 16: Ethernet MAC Address 1 High (EMACADDR1H), offset 0x048 The MAC Address 1 High (EMACADDR1H) register holds the upper 16 bits of the second 6-byte MAC address of the station. Ethernet MAC Address 1 High (EMACADDR1H) Base 0x400E.C000 Offset 0x048 Type RW, reset 0x0000.
PAGE 1627
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 23:16 reserved RO 0x0 15:0 ADDRHI RW 0xFFFF Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MAC Address1 [47:32] This field contains the upper 16 bits (47:32) of the second 6-byte MAC address.
PAGE 1628
Ethernet Controller Register 17: Ethernet MAC Address 1 Low (EMACADDR1L), offset 0x04C The MAC Address 1 Low (EMACADDR1L) register holds the lower 32 bits of the second 6-byte MAC address of the station. Ethernet MAC Address 1 Low (EMACADDR1L) Base 0x400E.C000 Offset 0x04C Type RW, reset 0xFFFF.
PAGE 1629
Tiva™ TM4C129ENCPDT Microcontroller Register 18: Ethernet MAC Address 2 High (EMACADDR2H), offset 0x050 The MAC Address 2 High (EMACADDR2H) register holds the upper 16 bits of the third 6-byte MAC address of the station. Ethernet MAC Address 2 High (EMACADDR2H) Base 0x400E.C000 Offset 0x050 Type RW, reset 0x0000.
PAGE 1630
Ethernet Controller Bit/Field Name Type Reset 23:16 reserved RO 0x0 15:0 ADDRHI RW 0xFFFF Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MAC Address2 [47:32] This field contains the upper 16 bits [47:32] of the third 6-byte MAC address.
PAGE 1631
Tiva™ TM4C129ENCPDT Microcontroller Register 19: Ethernet MAC Address 2 Low (EMACADDR2L), offset 0x054 The MAC Address2 Low register holds the lower 32 bits of the third 6-byte MAC address of the station. Ethernet MAC Address 2 Low (EMACADDR2L) Base 0x400E.C000 Offset 0x054 Type RW, reset 0xFFFF.
PAGE 1632
Ethernet Controller Register 20: Ethernet MAC Address 3 High (EMACADDR3H), offset 0x058 The Ethernet MAC Address 3 High (EMACADDR3H) register holds the upper 16 bits of the fourth 6-byte MAC address of the station. Ethernet MAC Address 3 High (EMACADDR3H) Base 0x400E.C000 Offset 0x058 Type RW, reset 0x0000.
PAGE 1633
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 23:16 reserved RO 0x0 15:0 ADDRHI RW 0xFFFF Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MAC Address3 [47:32] This field contains the upper 16 bits [47:32] of the fourth 6-byte MAC address.
PAGE 1634
Ethernet Controller Register 21: Ethernet MAC Address 3 Low (EMACADDR3L), offset 0x05C The Ethernet MAC Address 3 Low (EMACADDR3L) register holds the lower 32 bits of the fourth 6-byte MAC address of the station. Ethernet MAC Address 3 Low (EMACADDR3L) Base 0x400E.C000 Offset 0x05C Type RW, reset 0xFFFF.
PAGE 1635
Tiva™ TM4C129ENCPDT Microcontroller Register 22: Ethernet MAC Watchdog Timeout (EMACWDOGTO), offset 0x0DC This register controls the watchdog counter for received frames. Ethernet MAC Watchdog Timeout (EMACWDOGTO) Base 0x400E.C000 Offset 0x0DC Type RW, reset 0x0000.
PAGE 1636
Ethernet Controller Register 23: Ethernet MAC MMC Control (EMACMMCCTRL), offset 0x100 The MMC Control register establishes the operating mode of the management counters. Note: The CNTRST bit has higher priority than the CNTPRST. Therefore, when the software tries to set both bits in the same write cycle, all counters are cleared and the CNTPRST is not set. Ethernet MAC MMC Control (EMACMMCCTRL) Base 0x400E.C000 Offset 0x100 Type RW, reset 0x0000.
PAGE 1637
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 5 CNTPRSTLVL RW 0 Description Full/Half Preset Level Value Value Description 0 If CNTPRST is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF.F800 (half value - 2 KB) and all frame-counters get preset to 0x7FFF.FFF0 (half value - 16). 1 If CNTPRST is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF.
PAGE 1638
Ethernet Controller Bit/Field Name Type Reset 1 CNTSTPRO RW 0 Description Counters Stop Rollover Value Description 0 CNTRST RW 0x0 0 No effect. 1 After reaching maximum value, the MMC counters do not roll over to zero. Counters Reset Value Description 0 No effect 1 All MMC counters are reset. This bit is cleared automatically after one clock cycle.
PAGE 1639
Tiva™ TM4C129ENCPDT Microcontroller Register 24: Ethernet MAC MMC Receive Raw Interrupt Status (EMACMMCRXRIS), offset 0x104 The MAC MMC Receive Interrupt (EMACMMCRXRIS) register maintains the interrupts that are generated when the following happens: ■ Receive statistic counters reach half of their maximum values (0x8000.0000 for 32-bit counter and 0x8000 for 16-bit counter). ■ Receive statistic counters cross their maximum values (0xFFFF.FFFF for 32-bit counter and 0xFFFF for 16-bit counter).
PAGE 1640
Ethernet Controller Bit/Field Name Type Reset 6 ALGNERR RO 0x0 Description MMC Receive Alignment Error Frame Counter Interrupt Status Value Description 5 CRCERR RO 0x0 0 The Ethernet MAC Receive Frame Count for Alignment Error Frames (EMACRXCNTALGNERR) register has not reached half of the maximum value or the maximum value. 1 The Ethernet MAC Receive Frame Count for Alignment Error Frames (EMACRXCNTALGNERR) register has reached half of the maximum value or the maximum value.
PAGE 1641
Tiva™ TM4C129ENCPDT Microcontroller Register 25: Ethernet MAC MMC Transmit Raw Interrupt Status (EMACMMCTXRIS), offset 0x108 The MAC MMC Transmit Interrupt (EMACMMCTXRIS) register maintains the interrupts generated when transmit statistic counters reach half of their maximum values (0x8000_0000 for 32-bit counter and 0x8000 for 16-bit counter), and the maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter).
PAGE 1642
Ethernet Controller Bit/Field Name Type Reset 15 MCOLLGF RO 0x0 Description MMC Transmit Multiple Collision Good Frame Counter Interrupt Status Value Description 14 SCOLLGF RO 0x0 0 The Ethernet MAC Transmit Frame Count for Frames Transmitted after Multiple Collisions (EMACTXCNTMCOL) register has not reached half of the maximum value or the maximum value.
PAGE 1643
Tiva™ TM4C129ENCPDT Microcontroller Register 26: Ethernet MAC MMC Receive Interrupt Mask (EMACMMCRXIM), offset 0x10C The MAC MMC Receive Interrupt Mask (EMACMMCRXIM) register maintains the masks for the interrupts generated when the receive statistic counters reach half of their maximum value, or maximum value. This register is 32-bits wide. Ethernet MAC MMC Receive Interrupt Mask (EMACMMCRXIM) Base 0x400E.C000 Offset 0x10C Type RW, reset 0x0000.
PAGE 1644
Ethernet Controller Bit/Field Name Type Reset 4:1 reserved RO 0 0 GBF RW 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MMC Receive Good Bad Frame Counter Interrupt Mask Value Description 0 An interrupt is sent to the interrupt controller when the GBF bit in the EMACMMCRXRIS register is set.
PAGE 1645
Tiva™ TM4C129ENCPDT Microcontroller Register 27: Ethernet MAC MMC Transmit Interrupt Mask (EMACMMCTXIM), offset 0x110 The MAC MMC Transmit Interrupt Mask (EMACMMCTXIM) register maintains the masks for the interrupts generated when the transmit statistic counters reach half of their maximum value or maximum value. This register is 32-bits wide. Ethernet MAC MMC Transmit Interrupt Mask (EMACMMCTXIM) Base 0x400E.C000 Offset 0x110 Type RW, reset 0x0000.
PAGE 1646
Ethernet Controller Bit/Field Name Type Reset 13:2 reserved RO 0 1 GBF RW 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MMC Transmit Good Bad Frame Counter Interrupt Mask Value Description 0 reserved RO 0 0 An interrupt is sent to the interrupt controller when the GBF bit in the EMACMMCTXRIS register is set.
PAGE 1647
Tiva™ TM4C129ENCPDT Microcontroller Register 28: Ethernet MAC Transmit Frame Count for Good and Bad Frames (EMACTXCNTGB), offset 0x118 The MAC Transmit Frame Count for Good and Bad Frames (EMACTXCNTGB) register maintains the number of good and bad frames transmitted, exclusive of retried frames. Note: This counter is reset to all zeros by setting the CNTRST bit in the Ethernet MAC MMC Control (EMACMMCCTRL), offset 0x100. Ethernet MAC Transmit Frame Count for Good and Bad Frames (EMACTXCNTGB) Base 0x400E.
PAGE 1648
Ethernet Controller Register 29: Ethernet MAC Transmit Frame Count for Frames Transmitted after Single Collision (EMACTXCNTSCOL), offset 0x14C This register maintains the number of successfully transmitted frames after a single collision in the half-duplex mode. Note: This counter is reset to all zeros by setting the CNTRST bit in the Ethernet MAC MMC Control (EMACMMCCTRL), offset 0x100. Ethernet MAC Transmit Frame Count for Frames Transmitted after Single Collision (EMACTXCNTSCOL) Base 0x400E.
PAGE 1649
Tiva™ TM4C129ENCPDT Microcontroller Register 30: Ethernet MAC Transmit Frame Count for Frames Transmitted after Multiple Collisions (EMACTXCNTMCOL), offset 0x150 This register maintains the number of successfully transmitted frames after multiple collisions in the half-duplex mode. Note: This counter is reset to all zeros by setting the CNTRST bit in the Ethernet MAC MMC Control (EMACMMCCTRL), offset 0x100.
PAGE 1650
Ethernet Controller Register 31: Ethernet MAC Transmit Octet Count Good (EMACTXOCTCNTG), offset 0x164 This register maintains the number of bytes transmitted, exclusive of preamble, only in good frames. Note: This counter is reset to all zeros by setting the CNTRST bit in the Ethernet MAC MMC Control (EMACMMCCTRL), offset 0x100. Ethernet MAC Transmit Octet Count Good (EMACTXOCTCNTG) Base 0x400E.C000 Offset 0x164 Type RO, reset 0x0000.
PAGE 1651
Tiva™ TM4C129ENCPDT Microcontroller Register 32: Ethernet MAC Receive Frame Count for Good and Bad Frames (EMACRXCNTGB), offset 0x180 This register maintains the number of received good and bad frames. Note: This counter is reset to all zeros by setting the CNTRST bit in the Ethernet MAC MMC Control (EMACMMCCTRL), offset 0x100. Ethernet MAC Receive Frame Count for Good and Bad Frames (EMACRXCNTGB) Base 0x400E.C000 Offset 0x180 Type RO, reset 0x0000.
PAGE 1652
Ethernet Controller Register 33: Ethernet MAC Receive Frame Count for CRC Error Frames (EMACRXCNTCRCERR), offset 0x194 This register maintains the number of frames received with CRC error. Note: This counter is reset to all zeros by setting the CNTRST bit in the Ethernet MAC MMC Control (EMACMMCCTRL), offset 0x100. Ethernet MAC Receive Frame Count for CRC Error Frames (EMACRXCNTCRCERR) Base 0x400E.C000 Offset 0x194 Type RO, reset 0x0000.
PAGE 1653
Tiva™ TM4C129ENCPDT Microcontroller Register 34: Ethernet MAC Receive Frame Count for Alignment Error Frames (EMACRXCNTALGNERR), offset 0x198 This register maintains the number of frames received with alignment (dribble) error. Note: This counter is reset to all zeros by setting the CNTRST bit in the Ethernet MAC MMC Control (EMACMMCCTRL), offset 0x100. Ethernet MAC Receive Frame Count for Alignment Error Frames (EMACRXCNTALGNERR) Base 0x400E.C000 Offset 0x198 Type RO, reset 0x0000.
PAGE 1654
Ethernet Controller Register 35: Ethernet MAC Receive Frame Count for Good Unicast Frames (EMACRXCNTGUNI), offset 0x1C4 This register maintains the number of received good unicast frames. Note: This counter is reset to all zeros by setting the CNTRST bit in the Ethernet MAC MMC Control (EMACMMCCTRL), offset 0x100. Ethernet MAC Receive Frame Count for Good Unicast Frames (EMACRXCNTGUNI) Base 0x400E.C000 Offset 0x1C4 Type RO, reset 0x0000.
PAGE 1655
Tiva™ TM4C129ENCPDT Microcontroller Register 36: Ethernet MAC VLAN Tag Inclusion or Replacement (EMACVLNINCREP), offset 0x584 The MAC VLAN Tag Inclusion or Replacement (EMACVLNINCREP) register contains the VLAN tag for insertion or replacement in the transmit frames. Ethernet MAC VLAN Tag Inclusion or Replacement (EMACVLNINCREP) Base 0x400E.C000 Offset 0x584 Type RW, reset 0x0000.
PAGE 1656
Ethernet Controller Bit/Field Name Type Reset 17:16 VLC RW 0x0 Description VLAN Tag Control in Transmit Frames Value Description 0x0 No VLAN tag deletion, insertion, or replacement 0x1 VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. 0x2 VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14.
PAGE 1657
Tiva™ TM4C129ENCPDT Microcontroller Register 37: Ethernet MAC VLAN Hash Table (EMACVLANHASH), offset 0x588 The 16-bit hash table is used for group address filtering based on VLAN tag when the VTHM bit of the EMACVLANTG register is set.
PAGE 1658
Ethernet Controller Register 38: Ethernet MAC Timestamp Control (EMACTIMSTCTRL), offset 0x700 This register controls the operation of the system time generator and the processing of Precision Time Protocol (PTP) packets for time-stamping in the receiver. Ethernet MAC Timestamp Control (EMACTIMSTCTRL) Base 0x400E.C000 Offset 0x700 Type RW, reset 0x0000.
PAGE 1659
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 13 PTPIPV4 RW 0x1 Description Enable Processing of PTP Frames Sent over IPv4-UDP Value Description 12 PTPIPV6 RW 0x0 0 The MAC ignores PTP transported over UDP-IPv4 packets. This bit is set by default. 1 The MAC receiver processes PTP packets encapsulated in UDP over IPv4 packets. Enable Processing of PTP Frames Sent Over IPv6-UDP Value Description 11 PTPETH RW 0x0 0 The MAC ignores PTP transported over UDP-IPv6 packets.
PAGE 1660
Ethernet Controller Bit/Field Name Type Reset Description 7:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 ADDREGUP RW 0x0 Addend Register Update Value Description 4 INTTRIG RW 0x0 0 No effect. 1 When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction.
PAGE 1661
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1 TSFCUPDT RW 0x0 Description Timestamp Fine or Coarse Update Value Description 0 TSEN RW 0x0 0x0 Indicates the system timestamp update should be done using the coarse method. 0x1 Indicates that the system times update should be done using the fine update method. Timestamp Enable The EMACTIMSEC and the EMACTIMNANO registers must be initialized after enabling this mode.
PAGE 1662
Ethernet Controller Register 39: Ethernet MAC Sub-Second Increment (EMACSUBSECINC), offset 0x704 In the Coarse Update mode (enabled by the TSCFUPDT bit in the MAC Timestamp Control (EMACTIMSTCTRL) register), the value in the EMACSUBSECINC register is added to the system time every clock cycle of slave clock reference, MOSC. In the Fine Update mode, the value in this register is added to the system time whenever the Accumulator gets an overflow. Ethernet MAC Sub-Second Increment (EMACSUBSECINC) Base 0x400E.
PAGE 1663
Tiva™ TM4C129ENCPDT Microcontroller Register 40: Ethernet MAC System Time - Seconds (EMACTIMSEC), offset 0x708 The MAC System Time - Seconds (EMACTIMSEC) register, along with the MAC System Time Nanoseconds (EMACTIMNANO) register, indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis, there is some delay from the actual time because of clock domain transfer latencies. Ethernet MAC System Time - Seconds (EMACTIMSEC) Base 0x400E.
PAGE 1664
Ethernet Controller Register 41: Ethernet MAC System Time - Nanoseconds (EMACTIMNANO), offset 0x70C The value in this field has the sub-second representation of time, with an accuracy of 0.46 ns. When DGTLBIN in the EMACTIMSTCTRL register is set, each bit represents 1 ns and the maximum value is 0x3B9A.C9FF, after which it rolls-over to zero. Ethernet MAC System Time - Nanoseconds (EMACTIMNANO) Base 0x400E.C000 Offset 0x70C Type RO, reset 0x0000.
PAGE 1665
Tiva™ TM4C129ENCPDT Microcontroller Register 42: Ethernet MAC System Time - Seconds Update (EMACTIMSECU), offset 0x710 The MAC System Time - Seconds Update (EMACTIMSECU) register, along with the MAC System Time - Nanoseconds Update (EMACTIMNANOU) register, initializes or updates the system time maintained by the MAC. Both of these register must be written before setting the TSINIT or TSUPDT bits in the EMACTIMSTCTRL register. Ethernet MAC System Time - Seconds Update (EMACTIMSECU) Base 0x400E.
PAGE 1666
Ethernet Controller Register 43: Ethernet MAC System Time - Nanoseconds Update (EMACTIMNANOU), offset 0x714 This register along with the EMACTIMSECU register initializes or updates the system time maintained by the MAC. Both of these register must be written before setting the TSINIT or TSUPDT bits in the EMACTIMSTCTRL register. Ethernet MAC System Time - Nanoseconds Update (EMACTIMNANOU) Base 0x400E.C000 Offset 0x714 Type RW, reset 0x0000.
PAGE 1667
Tiva™ TM4C129ENCPDT Microcontroller Register 44: Ethernet MAC Timestamp Addend (EMACTIMADD), offset 0x718 This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit is set in the EMACTIMSTCTRL register). This register content is added to a 32-bit accumulator every slave clock cycle (MOSC source) and the system time is updated whenever the accumulator overflows. Ethernet MAC Timestamp Addend (EMACTIMADD) Base 0x400E.C000 Offset 0x718 Type RW, reset 0x0000.
PAGE 1668
Ethernet Controller Register 45: Ethernet MAC Target Time Seconds (EMACTARGSEC), offset 0x71C The MAC Target Time Seconds (EMACTARGSEC) register, along with the MAC Target Time Nanoseconds (EMACTARGNANO) register, is used to schedule an interrupt event. Ethernet MAC Target Time Seconds (EMACTARGSEC) Base 0x400E.C000 Offset 0x71C Type RW, reset 0x0000.
PAGE 1669
Tiva™ TM4C129ENCPDT Microcontroller Register 46: Ethernet MAC Target Time Nanoseconds (EMACTARGNANO), offset 0x720 The MAC Target Time Seconds (EMACTARGSEC) register, along with the MAC Target Time Nanoseconds (EMACTARGNANO) register, is used to schedule an interrupt event. Ethernet MAC Target Time Nanoseconds (EMACTARGNANO) Base 0x400E.C000 Offset 0x720 Type RW, reset 0x0000.
PAGE 1670
Ethernet Controller Register 47: Ethernet MAC System Time-Higher Word Seconds (EMACHWORDSEC), offset 0x724 This register is used to support the most significant 16-bits of the timestamp seconds value. Ethernet MAC System Time-Higher Word Seconds (EMACHWORDSEC) Base 0x400E.C000 Offset 0x724 Type RW, reset 0x0000.
PAGE 1671
Tiva™ TM4C129ENCPDT Microcontroller Register 48: Ethernet MAC Timestamp Status (EMACTIMSTAT), offset 0x728 Ethernet MAC Timestamp Status (EMACTIMSTAT) Base 0x400E.C000 Offset 0x728 Type RO, reset 0x0000.
PAGE 1672
Ethernet Controller Register 49: Ethernet MAC PPS Control (EMACPPSCTRL), offset 0x72C This register is used to control the EN0PPS signal output. Note: The PTP reference clock referred to below is MOSC clock in course update mode and in fine correction mode, is the clock tick at which the system time gets updated. Ethernet MAC PPS Control (EMACPPSCTRL) Base 0x400E.C000 Offset 0x72C Type RW, reset 0x0000.
PAGE 1673
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3:0 PPSCTRL RW 0x0 Description EN0PPS Output Frequency Control (PPSCTRL) or Command Control (PPSCMD) This bit field has two different functions depending on how the PPSEN0 bit is set. See the values in Table 23-24 on page 1673. If the PPSEN0 bit is set to 0x0, this field functions as a PPS0 output frequency control (PPSCTRL), which controls the frequency of the output signal, EN0PPS.
PAGE 1674
Ethernet Controller Table 23-24. PPSCTRL Bit Field Values (continued) Value Description When the PPSEN0 bit = 0x1, cancel START. This command cancels the START single pulse and START pulse train commands if the system time has not crossed the programmed start time. 0x4 When thePPSEN0 bit = 0x0, the binary rollover is 16 Hz, and the digital rollover is 8 Hz. When the PPSEN0 bit = 0x1, STOP pulse train at time.
PAGE 1675
Tiva™ TM4C129ENCPDT Microcontroller Register 50: Ethernet MAC PPS0 Interval (EMACPPS0INTVL), offset 0x760 The MAC PPS0 Interval (EMACPPS0INTVL) register contains the number of units of sub-second increment value between the rising edges of EN0PPS signal output. Note: The PTP reference clock referred to below is MOSC clock in course update mode and in fine correction mode, is the clock tick at which the system time gets updated. Ethernet MAC PPS0 Interval (EMACPPS0INTVL) Base 0x400E.
PAGE 1676
Ethernet Controller Register 51: Ethernet MAC PPS0 Width (EMACPPS0WIDTH), offset 0x764 The MAC PPS0 Width (EMACPPS0WIDTH) register contains the number of units of sub-second increment value between the rising and corresponding falling edges of the EN0PPS output signal. Note: The PTP reference clock referred to below is MOSC clock in course update mode and in fine correction mode, is the clock tick at which the system time gets updated. Ethernet MAC PPS0 Width (EMACPPS0WIDTH) Base 0x400E.
PAGE 1677
Tiva™ TM4C129ENCPDT Microcontroller Register 52: Ethernet MAC DMA Bus Mode (EMACDMABUSMOD), offset 0xC00 The Ethernet MAC DMA Bus Mode (EMACDMABUSMODE) register establishes the operation modes for the DMA. Ethernet MAC DMA Bus Mode (EMACDMABUSMOD) Base 0x400E.C000 Offset 0xC00 Type RW, reset 0x0002.
PAGE 1678
Ethernet Controller Bit/Field Name Type Reset 25 AAL RW 0 Description Address Aligned Beats Value Description 0x0 Address aligned transfers are not enabled. 0x1 If the FB bit is set, the internal bus interface generates all bursts aligned to the start address least significant bits. If the FB bit is 0, the first burst is not aligned but subsequent bursts are aligned to the address.
PAGE 1679
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 15:14 PR RW 0x0 Description Priority Ratio These bits control the priority ratio in the weighted round-robin arbitration between the RX DMA and TX DMA. These bits are valid only when the DA bit in this register is clear. The priority ratio is RX:TX or TX:RX depending on whether the TXPR bit in this register is clear or set. Value Description 13:8 PBL RW 0x1 0x0 The Priority Ratio is 1:1. 0x1 The Priority Ratio is 2:1.
PAGE 1680
Ethernet Controller Bit/Field Name Type Reset 1 DA RW 0x0 Description DMA Arbitration Scheme This bit specifies the arbitration scheme between the transmit and receive paths of the DMA channel. Value Description 0 Weighted round-robin with RX:TX or TX:RX. The priority between the paths is according to the priority specified in the PR bit field and priority weights specified in the TXPR bit. 1 Fixed priority. The transmit path has priority over receive path when the TXPR bit is set.
PAGE 1681
Tiva™ TM4C129ENCPDT Microcontroller Register 53: Ethernet MAC Transmit Poll Demand (EMACTXPOLLD), offset 0xC04 The MAC Transmit Poll Demand (EMACTXPOLLD) register enables the TX DMA to check whether or not the DMA owns the current descriptor. The Transmit Poll Demand command is given to wake up the TX DMA if it is in the suspend mode. The TX DMA can go into the SUSPEND mode because of an underflow error in a transmitted frame or the unavailability of descriptors owned by it.
PAGE 1682
Ethernet Controller Register 54: Ethernet MAC Receive Poll Demand (EMACRXPOLLD), offset 0xC08 The Ethernet MAC Receive Poll Demand (EMACRXPOLLD) register enables the RX DMA to check for new descriptors. This command is used to wake up the RX DMA from the SUSPEND state. The RX DMA can go into the SUSPEND state only because of the unavailability of descriptors it owns. Ethernet MAC Receive Poll Demand (EMACRXPOLLD) Base 0x400E.C000 Offset 0xC08 Type WO, reset 0x0000.
PAGE 1683
Tiva™ TM4C129ENCPDT Microcontroller Register 55: Ethernet MAC Receive Descriptor List Address (EMACRXDLADDR), offset 0xC0C The Ethernet MAC Receive Descriptor List Address (EMACRXDLADDR) register points to the start of the Receive Descriptor List. The descriptor lists reside in the host's physical memory space and must be word-aligned. The DMA internally converts it to a 32-bit aligned address by making the two lease significant bits zero.
PAGE 1684
Ethernet Controller Register 56: Ethernet MAC Transmit Descriptor List Address (EMACTXDLADDR), offset 0xC10 The MAC Transmit Descriptor List Address (EMACTXDLADDR) register points to the start of the transmit descriptor list. The descriptor lists reside in the host's physical memory space and must be word-aligned. This register can only be written when the DMA transmit has stopped (ST = 0 in the MAC DMA Operation Mode (EMACDMAOPMODE) register).
PAGE 1685
Tiva™ TM4C129ENCPDT Microcontroller Register 57: Ethernet MAC DMA Interrupt Status (EMACDMARIS), offset 0xC14 The MAC DMA Interrupt Status (EMACDMARIS) register contains all status bits that the DMA reports to the host. The software driver reads this register during an interrupt service routine or polling. Most of the fields in this register cause the host to be interrupted. The bits of this register are not cleared when read.
PAGE 1686
Ethernet Controller Bit/Field Name Type Reset 27 MMC RO 0x0 Description MAC MMC Interrupt This bit reflects an interrupt event in the MMC module. Software must read the corresponding EMACMMCTXRIS/EMACMMCRXRIS register to determine the cause of the interrupt and then clear its source to reset this bit to 0. Value Description 26 reserved RO 0 25:23 AE RO 0x0 0 No MMC interrupt has occurred. 1 An interrupt in the MMC module has occurred.
PAGE 1687
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 19:17 RS RO 0x0 Description Received Process State This field indicates the Receive DMA state. This field does not generate an interrupt.
PAGE 1688
Ethernet Controller Bit/Field Name Type Reset 15 AIS RW1C 0x0 Description Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the EMACDMAIM register: ■ EMACDMARIS register, bit[1]: Transmit Process Stopped ■ EMACDMARIS register, bit[3]: Transmit Jabber Timeout ■ EMACDMARIS register, bit[4]: Receive FIFO Overflow ■ EMACDMARIS register, bit[5]: Transmit Underflow ■ EMACDMARIS register, bit[7]:
PAGE 1689
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 9 RWT RW1C 0x0 Description Receive Watchdog Timeout Value Description 0 No watchdog timeout event has occurred. 1 Indicates a frame with length greater than 2,048 bytes is received (10, 240 when Jumbo Frame mode is enabled). This bit is cleared by writing a 1 to it. 8 RPS RW1C 0x0 Receive Process Stopped Value Description 0 No receive process stopped event has occurred.
PAGE 1690
Ethernet Controller Bit/Field Name Type Reset 4 OVF RW1C 0x0 Description Receive Overflow Value Description 0 No receive overflow event has occurred. 1 The receive buffer had an overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. This bit is cleared by writing a 1 to it. 3 TJT RW1C 0x0 Transmit Jabber Timeout Value Description 0 No transmit jabber timeout event has occurred.
PAGE 1691
Tiva™ TM4C129ENCPDT Microcontroller Register 58: Ethernet MAC DMA Operation Mode (EMACDMAOPMODE), offset 0xC18 The MAC DMA Operation Mode (EMACDMAOPMODE) register establishes the Transmit and Receive operating modes and commands. This register should be the last register to be written as part of the DMA initialization. Ethernet MAC DMA Operation Mode (EMACDMAOPMODE) Base 0x400E.C000 Offset 0xC18 Type RW, reset 0x0000.
PAGE 1692
Ethernet Controller Bit/Field Name Type Reset Description 23:22 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 21 TSF RW 0x0 Transmit Store and Forward Value Description 20 FTF RW 0x0 0 Transmission starts according to TTC bit field. 1 Transmission starts when a full frame resides in the TX/RX Controller Transmit FIFO.
PAGE 1693
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 13 ST RW 0x0 Description Start or Stop Transmission Command When this bit is set, transmission is placed in the running state. The DMA attempts to acquire the descriptor from the Transmit Descriptor List.
PAGE 1694
Ethernet Controller Bit/Field Name Type Reset 6 FUF RW 0x0 Description Forward Undersized Good Frames Value Description 5 DGF RW 0x0 0 The Receive FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold (RTC) bit field (for example, RTC = 0x1). 1 The Receive FIFO forwards undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC.
PAGE 1695
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1 SR RW 0x0 Description Start or Stop Receive When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames.
PAGE 1696
Ethernet Controller Register 59: Ethernet MAC DMA Interrupt Mask Register (EMACDMAIM), offset 0xC1C The Interrupt Enable register enables the interrupts reported by the MAC DMA Interrupt Status Register (EMACDMARIS). Setting a bit to 0x1 enables a corresponding interrupt. After a hardware or software reset, all interrupts are disabled. Ethernet MAC DMA Interrupt Mask Register (EMACDMAIM) Base 0x400E.C000 Offset 0xC1C Type RW, reset 0x0000.
PAGE 1697
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 13 FBE RW 0x0 Description Fatal Bus Error Enable Value Description 0 Fatal Bus Error Enable Interrupt is disabled. 1 Fatal Bus Error Interrupt is enabled. Abnormal Interrupt Summary Enable (AIE, bit 15) must also be set to 0x1. 12:11 reserved RO 0x0 Software should not rely on the value of a reserved bit.
PAGE 1698
Ethernet Controller Bit/Field Name Type Reset 5 UNE RW 0x0 Description Underflow Interrupt Enable Value Description 4 OVE RW 0x0 0 Transmit Underflow Interrupt is disabled. 1 The Transmit Underflow Interrupt is enabled Abnormal Interrupt Summary Enable (AIE, bit 15) must also be set to 0x1. Overflow Interrupt Enable Value Description 3 TJE RW 0x0 0 The Overflow Interrupt is disabled. 1 The Receive Overflow Interrupt is enabled.
PAGE 1699
Tiva™ TM4C129ENCPDT Microcontroller Register 60: Ethernet MAC Missed Frame and Buffer Overflow Counter (EMACMFBOC), offset 0xC20 The DMA maintains two counters to track the number of frames missed during reception. This register reports the current value of the counters. The counter is used for diagnostic purposes. The MISFRMCNT field indicates missed frames because of the host buffer being unavailable.
PAGE 1700
Ethernet Controller Register 61: Ethernet MAC Receive Interrupt Watchdog Timer (EMACRXINTWDT), offset 0xC24 This register, when written with non-zero value, enables the watchdog timer for the Receive Interrupt, RI (Bit 6), of the EMACDMARIS register at EMAC offset 0xC14. Ethernet MAC Receive Interrupt Watchdog Timer (EMACRXINTWDT) Base 0x400E.C000 Offset 0xC24 Type RW, reset 0x0000.
PAGE 1701
Tiva™ TM4C129ENCPDT Microcontroller Register 62: Ethernet MAC Current Host Transmit Descriptor (EMACHOSTXDESC), offset 0xC48 The MAC Current Host Transmit Descriptor (EMACHOSTXDESC) register points to the start address of the current Transmit Descriptor read by the DMA. Ethernet MAC Current Host Transmit Descriptor (EMACHOSTXDESC) Base 0x400E.C000 Offset 0xC48 Type R, reset 0x0000.
PAGE 1702
Ethernet Controller Register 63: Ethernet MAC Current Host Receive Descriptor (EMACHOSRXDESC), offset 0xC4C The MAC Current Host Receive Descriptor (EMACHOSRXDESC) register points to the start address of the current Receive Descriptor read by the DMA. Ethernet MAC Current Host Receive Descriptor (EMACHOSRXDESC) Base 0x400E.C000 Offset 0xC4C Type RO, reset 0x0000.
PAGE 1703
Tiva™ TM4C129ENCPDT Microcontroller Register 64: Ethernet MAC Current Host Transmit Buffer Address (EMACHOSTXBA), offset 0xC50 The MAC Current Host Transmit Buffer Address (EMACHOSTXBA) register points to the current Transmit Buffer Address being read by the DMA. Ethernet MAC Current Host Transmit Buffer Address (EMACHOSTXBA) Base 0x400E.C000 Offset 0xC50 Type R, reset 0x0000.
PAGE 1704
Ethernet Controller Register 65: Ethernet MAC Current Host Receive Buffer Address (EMACHOSRXBA), offset 0xC54 The MAC Current Host Receive Buffer Address (EMACHOSRXBA) register points to the current receive buffer address being read by the DMA. Ethernet MAC Current Host Receive Buffer Address (EMACHOSRXBA) Base 0x400E.C000 Offset 0xC54 Type R, reset 0x0000.
PAGE 1705
Tiva™ TM4C129ENCPDT Microcontroller Register 66: Ethernet MAC Peripheral Property Register (EMACPP), offset 0xFC0 This register defines the Ethernet MAC and PHY type used. Ethernet MAC Peripheral Property Register (EMACPP) Base 0x400E.C000 Offset 0xFC0 Type RO, reset 0x0000.
PAGE 1706
Ethernet Controller Register 67: Ethernet MAC Peripheral Configuration Register (EMACPC), offset 0xFC4 The Ethernet MAC Peripheral Configuration Register (EMACPC) register configures the MAC and PHY reset and interface parameters. Ethernet MAC Peripheral Configuration Register (EMACPC) Base 0x400E.C000 Offset 0xFC4 Type RW, reset 0x0080.
PAGE 1707
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 24 NIBDETDIS RO 0 Description Odd Nibble TXER Detection Disable This bit is sampled on the deassertion of the PHY reset signal and is used as the default for the ODDNDETDIS bit of the Ethernet PHY Configuration 2 (EPHYCFG2) register, PHY offset 0x00A.
PAGE 1708
Ethernet Controller Bit/Field Name Type Reset 10 MDIXEN RW 1 Description MDIX Enable This bit is sampled on the deassertion of the PHY reset signal and is used to determine whether automatic MDI/MDIX crossover is enabled. Value Description 9 FASTRXDV RW 0 0 Disable automatic cross-over. 1 Enable automatic cross-over. Fast RXDV Detection This bit is sampled on the deassertion of the PHY reset signal and is used to select whether fast RXDV detection is enabled in the PHY.
PAGE 1709
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 2:1 ANMODE RW 3 Description Auto Negotiation Mode These bits are sampled on the deassertion of the PHY reset signal and are used to determine the auto-negotiation mode of the PHY.
PAGE 1710
Ethernet Controller Register 68: Ethernet MAC Clock Configuration Register (EMACCC), offset 0xFC8 The following register is used to configure the clocks of the Ethernet Controller. Ethernet MAC Clock Configuration Register (EMACCC) Base 0x400E.C000 Offset 0xFC8 Type RO, reset 0x0000.
PAGE 1711
Tiva™ TM4C129ENCPDT Microcontroller Register 69: Ethernet PHY Raw Interrupt Status (EPHYRIS), offset 0xFD0 The Ethernet PHY Raw Interrupt Status (EPHYRIS) register provides the raw interrupt status of the integrated Ethernet PHY. Ethernet PHY Raw Interrupt Status (EPHYRIS) Base 0x400E.C000 Offset 0xFD0 Type RO, reset 0x0000.
PAGE 1712
Ethernet Controller Register 70: Ethernet PHY Interrupt Mask (EPHYIM), offset 0xFD4 The Ethernet PHY Interrupt Mask (EPHYIM) register provides the raw interrupt status of the integrated Ethernet PHY. Ethernet PHY Interrupt Mask (EPHYIM) Base 0x400E.C000 Offset 0xFD4 Type RW, reset 0x0000.
PAGE 1713
Tiva™ TM4C129ENCPDT Microcontroller Register 71: Ethernet PHY Masked Interrupt Status and Clear (EPHYMISC), offset 0xFD8 The Ethernet Masked Interrupt Status and Clear (EPHYMISC) register displays the masked interrupt status of the integrated Ethernet PHY and can written to clear the EPHYRIS register.. This register is used for clearing the EPHYRIS register bits. Ethernet PHY Masked Interrupt Status and Clear (EPHYMISC) Base 0x400E.C000 Offset 0xFD8 Type RW1C, reset 0x0000.
PAGE 1714
Ethernet Controller Register 72: Ethernet PHY Basic Mode Control - MR0 (EPHYBMCR), address 0x000 This register describes the basic mode controls available to the EPHY. The reset state of the ANEN bit is controlled by the EMACPC register.
PAGE 1715
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 11 PWRDWN RW 0 Description Power Down Setting this bit powers down the PHY. Only minimal register functionality is enabled during the power down condition. Value Description 10 ISOLATE RW 0 0 Normal operation 1 Power-down modes are enabled: General Power Down Mode, Active Sleep Mode and Passive Sleep Mode (see Ethernet PHY Specific Control (EPHYSCR) register, offset 0x011.
PAGE 1716
Ethernet Controller Register 73: Ethernet PHY Basic Mode Status - MR1 (EPHYBMSR), address 0x001 This register reflects the basic mode features that are available in the EPHY.
PAGE 1717
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 6 MFPRESUP RO 1 Description Preamble Suppression Capable Value Description 5 ANC RO 0 0 The device does not perform management transactions with preambles suppressed. 1 The device performs management transactions with preambles suppressed. For this mode, the 32-bits of preamble are needed only once after reset, invalid opcode or invalid turnaround.
PAGE 1718
Ethernet Controller Bit/Field Name Type Reset 0 EXTEN RO 1 Description Extended Capability Enable Value Description 0 Basic register set capabilities only. 1 Extended register capabilities.
PAGE 1719
Tiva™ TM4C129ENCPDT Microcontroller Register 74: Ethernet PHY Identifier Register 1 - MR2 (EPHYID1), address 0x002 The Ethernet PHY Identifier 1 and 2 (EPHYIDn) registers together form a unique identifier. The identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management.
PAGE 1720
Ethernet Controller Register 75: Ethernet PHY Identifier Register 2 - MR3 (EPHYID2), address 0x003 The Ethernet PHY Identifier 1 and 2 (EPHYIDn) registers together form a unique identifier. The identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management.
PAGE 1721
Tiva™ TM4C129ENCPDT Microcontroller Register 76: Ethernet PHY Auto-Negotiation Advertisement - MR4 (EPHYANA), address 0x004 This register contains the advertised abilities of this device as they are transmitted to its link partner during Auto-Negotiation.
PAGE 1722
Ethernet Controller Bit/Field Name Type Reset 10 PAUSE RW 0 Description PAUSE Support for Full Duplex Links The PAUSE bit indicates that the device is capable of providing the symmetric PAUSE functions as defined in Annex 31B. Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution status is reported in the Ethernet PHY Control (EPHYCTL)register.
PAGE 1723
Tiva™ TM4C129ENCPDT Microcontroller Register 77: Ethernet PHY Auto-Negotiation Link Partner Ability - MR5 (EPHYANLPA), address 0x005 This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if next-pages are supported.
PAGE 1724
Ethernet Controller Bit/Field Name Type Reset 9 100BT4 RO 0 Description 100Base-T4 Support Value Description 8 100BTXFD RO 0 0 100Base-T4 is not supported by the Link Partner. 1 100Base-T4 is supported by the Link Partner. 100Base-TX Full Duplex Support Value Description 7 100BTX RO 0 0 100Base-TX Full Duplex is not supported by the Link Partner. 1 100Base-TX Full Duplex is supported by the Link Partner.
PAGE 1725
Tiva™ TM4C129ENCPDT Microcontroller Register 78: Ethernet PHY Auto-Negotiation Expansion - MR6 (EPHYANER), address 0x006 This register contains additional local device and link partner status information.
PAGE 1726
Ethernet Controller Register 79: Ethernet PHY Auto-Negotiation Next Page TX - MR7 (EPHYANNPTR), address 0x007 This register contains the next page information sent by this device to its link partner during Auto-Negotiation.
PAGE 1727
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 10:0 CODE RW 0x1 Description Code This field represents the code field of the next page transmission. If the MP bit is set (bit 13 of this register), then the code is interpreted as a Message Page, as defined in annex 28C of IEEE 802.3u. Otherwise, the code is interpreted as an Unformatted Page, and the interpretation is application specific. The default value of the CODE field represents a Null Page as defined in Annex 28C of IEEE 802.
PAGE 1728
Ethernet Controller Register 80: Ethernet PHY Auto-Negotiation Link Partner Ability Next Page MR8 (EPHYANLNPTR), address 0x008 This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.
PAGE 1729
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 11 TOG RO 0 Description Toggle Toggle is used by the Arbitration function within Auto-Negotiation to synchronize with the Link Partner during Next Page exchange. This bit always takes the opposite value of the Toggle bit in the previously exchanged Link Code Word Value Description 10:0 CODE RO 0x0 0 Value of toggle bit in previously transmitted Link Code Word was 1.
PAGE 1730
Ethernet Controller Register 81: Ethernet PHY Configuration 1 - MR9 (EPHYCFG1), address 0x009 This register configuration for the Ethernet PHY. These configuration values are programmed by the system processor after a POR. The DONE bit in the EPHYCFG1 register is set when configuration is complete. This register is used when the user requires a configuration different from what is provided in the EMACPC register.
PAGE 1731
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 6 FAMDIX RW 0 Description Fast Auto MDI/MDIX If both link partners are configured to work in Force 100Base-TX mode (auto-negotiation is disabled), this mode enables automatic MDI/MDIX resolution in a short time. Value Description 5 RAMDIX RW 0 0 Normal Auto MDI/MDIX mode. 1 Enable Fast Auto MDI/MDIX mode.
PAGE 1732
Ethernet Controller Bit/Field Name Type Reset 3:2 FANSEL RW 0 Description Fast Auto-Negotiation Select Configuration This bit is preconfigured at reset by the EMACPC register. For custom configuration see “Custom Configuration” on page 1590. Adjusting these bits reduces the time it takes to auto-negotiate between two PHYs. In Fast AN mode, both PHYs should be configured to the same configuration.
PAGE 1733
Tiva™ TM4C129ENCPDT Microcontroller Register 82: Ethernet PHY Configuration 2 - MR10 (EPHYCFG2), address 0x00A Fields in this register are used to configure the Ethernet PHY. These configuration values are programmed by the system processor after a POR. The DONE bit in the EPHYCFG1 register is set when configuration is complete. This register is used when the user requires a configuration different from what is provided in the EMACPC register.
PAGE 1734
Ethernet Controller Bit/Field Name Type Reset 3 ISOMIILL RW 0 Description Isolate MII outputs when Enhanced Link is not Achievable Value Description 2 RXERRIDLE RW 1 0 Normal MII outputs operation 1 When no link established in 100B-TX and Full Duplex conditions, MII outputs are tied low. Detection of Receive Symbol Error During IDLE State Value Description 1 ODDNDETDIS RW 0 0 Disable detection of Receive symbol error during IDLE state.
PAGE 1735
Tiva™ TM4C129ENCPDT Microcontroller Register 83: Ethernet PHY Configuration 3 - MR11 (EPHYCFG3), address 0x00B Fields in this register are used to configure the Ethernet PHY. These configuration values are programmed by the system processor after a POR. The DONE bit in the EPHYCFG1 register is set when configuration is complete. This register is used when the user requires a configuration different from what is provided in the EMACPC register.
PAGE 1736
Ethernet Controller Bit/Field Name Type Reset 4:0 FLDWNM RW 0x0 Description Fast Link Down Modes The Fast Link Down function is an OR of the following five options. The application can enable combinations of these conditions. Bit 4: Drop the link due to descrambler sync loss. If this bit is enabled, the link is dropped when the receiver loses synchronization of the transmitter. Bit 3: Drop the link based on RX Error count of the MII interface.
PAGE 1737
Tiva™ TM4C129ENCPDT Microcontroller Register 84: Ethernet PHY Register Control - MR13 (EPHYREGCTL), address 0x00D EPHYREGCTL (0x00D) and EPHYADDAR (0x00E) registers allow read/write access to the extended register set using indirect addressing. The modes for the FUNC field are as follows: ■ EPHYREGCTL[15:14] = 0x0: A write to EPHYADDAR modifies the extended register set address register. This address register must be initialized in order to access any of the registers within the extended register set.
PAGE 1738
Ethernet Controller Bit/Field Name Type Reset 4:0 DEVAD WO 0x0 Description Device Address In general, these bits [4:0] are the device address DEVAD that directs any accesses of EPHYADDAR register (0x00E) to the appropriate MMD. The PHY uses the vendor specific DEVAD [4:0] = 0x1F for accesses. All accesses through registers EPHYREGCR and EPHYADDAR should use this DEVAD. Transactions with other DEVAD are ignored.
PAGE 1739
Tiva™ TM4C129ENCPDT Microcontroller Register 85: Ethernet PHY Address or Data - MR14 (EPHYADDAR), address 0x00E This register is the address/data MMD register. It is used in conjunction with EPHYREGCTL register (PHY offset 0x00D) to provide the access by an indirect read/write mechanism to the extended register set.
PAGE 1740
Ethernet Controller Register 86: Ethernet PHY Status - MR16 (EPHYSTS), address 0x010 This register provides quick access to commonly accessed PHY control status and general information.
PAGE 1741
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 11 FCSL RO 0 Description False Carrier Sense Latch Value Description 0 No False Carrier event has occurred. 1 False Carrier event has occurred since last read of EPHYFCSCR register (0x014). This bit is cleared on a read of the EPHYFCSR register. 10 SD RO 0 Signal Detect This bit displays the active high 100Base-TX unconditional Signal Detect indication from the PMD (Physical Layer Medium Dependent).
PAGE 1742
Ethernet Controller Bit/Field Name Type Reset 5 JD RO 0 Description Jabber Detect This bit will not be cleared upon a read of the EPHYSTS register. Value Description 4 ANS RO 0 0 No Jabber. 1 Jabber condition detected. This bit has meaning only in 10 Mb/s mode. This bit is a duplicate of the Jabber Detect bit in the EPHYBMSR register (PHY offset 0x001). Auto-Negotiation Status Value Description 3 MIILB RO 0 0 Auto-Negotiation not complete. 1 Auto-Negotiation complete.
PAGE 1743
Tiva™ TM4C129ENCPDT Microcontroller Register 87: Ethernet PHY Specific Control- MR17 (EPHYSCR), address 0x011 This register implements the PHY Specific Control register. This register allows access to general functionality inside the PHY to enable operation in reduced power modes and control the interrupt mechanism.
PAGE 1744
Ethernet Controller Bit/Field Name Type Reset 11 SBPYASS RW 0x1 Description Scrambler Bypass Value Description 0 Scrambler bypass disabled. 1 Scrambler bypass enabled. 10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
PAGE 1745
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1 INTEN RW 1 Description Interrupt Enable Value Description 0 Disable event based interrupts 1 Enable event based interrupts Enables interrupt dependent on the event enables in the EPHYMISR register (0x012). 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
PAGE 1746
Ethernet Controller Register 88: Ethernet PHY MII Interrupt Status 1 - MR18 (EPHYMISR1), address 0x012 This register contains events status and enables for the interrupt function. If an event has occurred since the last read of this register, the corresponding status bit is set. If the corresponding enable bit in the register is set, an interrupt is generated if the event occurs. The INTEN bit (Bit 1) in the EPHYSCR register (0x011) must also be set to allow interrupts.
PAGE 1747
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 9 FCHF RO 0 Description False Carrier Counter Half-Full Interrupt Reading this bit clears the interrupt and thus, the status bit. Value Description 8 RXHF RO 0 0 False carrier counter half-full event is not pending. 1 False carrier counter (Register EPHYFCSCR, address 0x014) exceeds half-full and an interrupt is pending. Receive Error Counter Half-Full Interrupt Reading this bit clears the interrupt and thus, the status bit.
PAGE 1748
Ethernet Controller Bit/Field Name Type Reset 1 FCHFEN RW 0 Description False Carrier Counter Register half-full Interrupt Enable Value Description 0 RXHFEN RW 0 0 False Carrier Counter Register half-full interrupt disabled. 1 Enable interrupt on False Carrier Counter Register half-full event Receive Error Counter Register Half-Full Event Interrupt Value Description 0 Receive Error Counter Register half-full interrupt disabled.
PAGE 1749
Tiva™ TM4C129ENCPDT Microcontroller Register 89: Ethernet PHY MII Interrupt Status 2 - MR19 (EPHYMISR2), address 0x013 This register contains additional event status and enables for the interrupt function. If an event has occurred since the last read of this register, the corresponding status bit is set. If the corresponding enable bit in the register is set, an interrupt is generated if the event occurs. The INTEN bit (bit 1) in the EPHYSCR register (PHY offset 0x011) must also be set to allow interrupts.
PAGE 1750
Ethernet Controller Bit/Field Name Type Reset 10 SLEEP RO 0 Description Sleep Mode Event Interrupt Reading this bit clears the interrupt. Value Description 9 POLINT RO 0 0 No sleep mode event pending. 1 Sleep Mode event interrupt is pending. Polarity Changed Interrupt Reading this bit clears the interrupt. Value Description 8 JABBER RO 0 0 No Data polarity event pending. 1 Data polarity changed interrupt pending. Jabber Detect Event Interrupt Reading this bit clears the interrupt.
PAGE 1751
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3 MDICOEN RW 0 Description MDI/MDIX Crossover Status Changed Interrupt Enable Value Description 2 SLEEPEN RW 0 0 MDI/MDIX Crossover Change Status interrupt disabled 1 MDI/MDIX Crossover Change Status interrupt enabled. Sleep Mode Event Interrupt Enable Value Description 1 POLINTEN RW 0 0 Sleep mode interrupt disabled. 1 Sleep Mode event interrupt enabled.
PAGE 1752
Ethernet Controller Register 90: Ethernet PHY False Carrier Sense Counter - MR20 (EPHYFCSCR), address 0x014 This counter provides information required to implement the False Carriers attribute within the MAU managed object class of Clause 30 of the IEEE 802.3u specification.
PAGE 1753
Tiva™ TM4C129ENCPDT Microcontroller Register 91: Ethernet PHY Receive Error Count - MR21 (EPHYRXERCNT), address 0x015 This counter provides information required to implement the Symbol Error During Carrier attribute within the PHY managed object class of Clause 30 of the IEEE 802.3u specification. Ethernet PHY Receive Error Count - MR21 (EPHYRXERCNT) Base n/a Address 0x015 Type RO, reset 0x0000.
PAGE 1754
Ethernet Controller Register 92: Ethernet PHY BIST Control - MR22 (EPHYBISTCR), address 0x016 This register is used for Build-In Self Test (BIST) configuration. The BIST functionality provides Pseudo Random Bit Stream (PRBS) mechanism including packet generation generator and checker. Selection of the exact loopback point in the signal chain is also done in this register.
PAGE 1755
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 10 PRBSCHKSYNC RO 0 Description PRBS Checker Lock Sync Loss Indication Value Description 9 PKTGENSTAT RO 0 0 PRBS checker has not lost synchronization. 1 PRBS checker has lost synchronization on received bit stream. This is an error indication. Packet Generator Status Indication Value Description 8 PWRMODE RO 1 0 Packet Generator is disabled. 1 Packet Generator is active and generate packets.
PAGE 1756
Ethernet Controller Bit/Field Name Type Reset 4:0 LBMODE RW 0 Description Loopback Mode Select The PHY provides several options for Loopback that test and verify various functional blocks within the PHY.
PAGE 1757
Tiva™ TM4C129ENCPDT Microcontroller Register 93: Ethernet PHY LED Control - MR24 (EPHYLEDCR), address 0x018 This register provides the ability to control the blink rate on the LED outputs.
PAGE 1758
Ethernet Controller Register 94: Ethernet PHY Control - MR25 (EPHYCTL), address 0x019 This register provides the ability to control and set general functionality inside the PHY.
PAGE 1759
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 11 MIILNKSTAT RO 0 Description MII Link Status Value Description 0 No active link of 100BT full-duplex has been established using Auto-Negotiation. 1 100BT Full-duplex Link is active and was established using Auto-Negotiation. 10:8 reserved RO 0 Software should not rely on the value of a reserved bit.
PAGE 1760
Ethernet Controller Register 95: Ethernet PHY 10Base-T Status/Control - MR26 (EPHY10BTSC), address 0x01A This register provides the ability to control and read status of the PHY's internal 10Base-T functionality.
PAGE 1761
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 POLSTAT RO 0 Description 10 Mb Polarity Status This bit is a duplication of POLSTAT bit in the EPHYSTS register, offset 0x0010. Both bits are cleared on a read of the Ethernet PHY 10Base-T Status/Control (EPHY10BTSC), but not upon a read of the EPHYSTS register. Value Description 0 Correct Polarity detected. 1 Inverted Polarity detected. 3:1 reserved RO 0 Software should not rely on the value of a reserved bit.
PAGE 1762
Ethernet Controller Register 96: Ethernet PHY BIST Control and Status 1 - MR27 (EPHYBICSR1), address 0x01B This register provides the total number of error bytes that are received by the PRBS checker and defines the Inter-Packet Gap (IPG) for the packet generator.
PAGE 1763
Tiva™ TM4C129ENCPDT Microcontroller Register 97: Ethernet PHY BIST Control and Status 2 - MR28 (EPHYBICSR2), address 0x01C This register allows programming the length of the generated packets in bytes for the BIST mechanism Ethernet PHY BIST Control and Status 2 - MR28 (EPHYBICSR2) Base n/a Address 0x01C Type RW, reset 0x05EE 15 14 13 12 11 10 9 8 7 6 reserved Type Reset RO 0 RO 0 RO 0 5 4 3 2 1 0 RW 0 RW 1 RW 1 RW 1 RW 0 PKTLENGTH RO 0 RO 0 RW 1 RW 0 Bit/Field Name Type Res
PAGE 1764
Ethernet Controller Register 98: Ethernet PHY Cable Diagnostic Control - MR30 (EPHYCDCR), address 0x01E This register provides the ability to start cable diagnostics and monitor its status.
PAGE 1765
Tiva™ TM4C129ENCPDT Microcontroller Register 99: Ethernet PHY Reset Control - MR31 (EPHYRCR), address 0x01F This register allows the system to reset or restart the PHY by register access.
PAGE 1766
Ethernet Controller Register 100: Ethernet PHY LED Configuration - MR37 (EPHYLEDCFG), address 0x025 This register configures the LEDs provided in the PHY. Ethernet PHY LED Configuration - MR37 (EPHYLEDCFG) Base n/a Address 0x025 Type RW, reset 0x0000.
PAGE 1767
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3:0 LED0 RW 0x0 Description LED0 Configuration The following encodings are used to program the specific function desired for the LED.
PAGE 1768
Universal Serial Bus (USB) Controller 24 Universal Serial Bus (USB) Controller Important: The full USB chapter is under NDA. This chapter describes the module features at a high level. For a copy of the full NDA data sheet, follow the instructions in the Non-Disclosure Agreement for the Tiva C Series TM4C129ENCPDT Microcontroller Data Sheet (literature number SPMS418).
PAGE 1769
Tiva™ TM4C129ENCPDT Microcontroller 24.1 Block Diagram Figure 24-1. USB Module Block Diagram Endpoint Control DMA Controller Transmit AHB Master Bus EP0 – 7 Control Receive Combine Endpoints UTM Synchronization Packet Encode/Decode Data Sync Packet Encode HNP/SRP Packet Decode Timers CRC Gen/Check 0 FIFO RAM Controller Rx Rx Buff Buff USB0CLK USB0DIR 1 USB0NXT ULPI USB0STP Interface CPU Interface Interrupt Control Interrupts EP Reg.
PAGE 1770
Universal Serial Bus (USB) Controller Note: Port pins PL6 and PL7 operate as Fast GPIO pads, but have 4-mA drive capability only. GPIO register controls for drive strength, slew rate and open drain have no effect on these pins. The registers which have no effect are as follows: GPIODR2R, GPIODR4R, GPIODR8R, GPIODR12R, GPIOSLR, and GPIOODR. Refer to “General-Purpose Input/Outputs (GPIOs)” on page 750 and “Recommended GPIO Operating Characteristics” on page 1944 for more information. Table 24-1.
PAGE 1771
Tiva™ TM4C129ENCPDT Microcontroller Note: Descriptions for all these registers can be found in the NDA version of the data sheet. Table 24-2.
PAGE 1772
Universal Serial Bus (USB) Controller Table 24-2.
PAGE 1773
Tiva™ TM4C129ENCPDT Microcontroller Table 24-2.
PAGE 1774
Universal Serial Bus (USB) Controller Table 24-2.
PAGE 1775
Tiva™ TM4C129ENCPDT Microcontroller Table 24-2.
PAGE 1776
Universal Serial Bus (USB) Controller Table 24-2.
PAGE 1777
Tiva™ TM4C129ENCPDT Microcontroller 25 Analog Comparators An analog comparator is a peripheral that compares two analog voltages and provides a logical output that signals the comparison result. Note: Not all comparators have the option to drive an output pin. See “Signal Description” on page 1778 for more information. The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board.
PAGE 1778
Analog Comparators 25.1 Block Diagram Figure 25-1.
PAGE 1779
Tiva™ TM4C129ENCPDT Microcontroller Table 25-1. Analog Comparators Signals (128TQFP) (continued) Pin Name 25.3 Pin Number Pin Mux / Pin Assignment Pin Type Buffer Type Description C0- 22 PC7 I Analog Analog comparator 0 negative input. C0o 1 83 PD0 (5) PL2 (5) O TTL C1+ 24 PC5 I Analog Analog comparator 1 positive input. C1- 25 PC4 I Analog Analog comparator 1 negative input. C1o 2 84 PD1 (5) PL3 (5) O TTL C2+ 118 PP0 I Analog Analog comparator 2 positive input.
PAGE 1780
Analog Comparators Important: The ASRCP bits in the ACCTL register must be set before using the analog comparators. 25.3.1 Internal Reference Programming The structure of the internal reference is shown in Figure 25-3 on page 1780. The internal reference is controlled by a single configuration register (ACREFCTL). Figure 25-3.
PAGE 1781
Tiva™ TM4C129ENCPDT Microcontroller Table 25-2. Internal Reference Voltage and ACREFCTL Field Values (continued) ACREFCTL Register EN Bit Value RNG Bit Value RNG=0 Output Reference Voltage Based on VREF Field Value VIREF High Range: 16 voltage threshold values indexed by VREF = 0x0 .. 0xF Ideal starting voltage (VREF=0): VDDA / 4.2 Ideal step size: VDDA/ 29.4 Ideal VIREF threshold values: VIREF (VREF) = VDDA / 4.2 + VREF * (VDDA/ 29.4), for VREF = 0x0 ..
PAGE 1782
Analog Comparators Table 25-4. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and RNG = 1 25.4 VREF Value VIREF Min Ideal VIREF VIREF Max Unit 0x0 0.000 0.000 0.074 V 0x1 0.076 0.149 0.223 V 0x2 0.225 0.298 0.372 V 0x3 0.374 0.448 0.521 V 0x4 0.523 0.597 0.670 V 0x5 0.672 0.746 0.820 V 0x6 0.822 0.895 0.969 V 0x7 0.971 1.044 1.118 V 0x8 1.120 1.193 1.267 V 0x9 1.269 1.343 1.416 V 0xA 1.418 1.492 1.565 V 0xB 1.567 1.
PAGE 1783
Tiva™ TM4C129ENCPDT Microcontroller 25.5 Register Map Table 25-5 on page 1783 lists the comparator registers. The offset listed is a hexadecimal increment to the register's address, relative to the Analog Comparator base address of 0x4003.C000. Note that the analog comparator clock must be enabled before the registers can be programmed (see page 404). There must be a delay of 3 system clocks after the analog comparator module clock is enabled before any analog comparator module registers are accessed.
PAGE 1784
Analog Comparators Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 This register provides a summary of the interrupt status (masked) of the comparators. Analog Comparator Masked Interrupt Status (ACMIS) Base 0x4003.C000 Offset 0x000 Type RW1C, reset 0x0000.
PAGE 1785
Tiva™ TM4C129ENCPDT Microcontroller Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 This register provides a summary of the interrupt status (raw) of the comparators. The bits in this register must be enabled to generate interrupts using the ACINTEN register. Analog Comparator Raw Interrupt Status (ACRIS) Base 0x4003.C000 Offset 0x004 Type RO, reset 0x0000.
PAGE 1786
Analog Comparators Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 This register provides the interrupt enable for the comparators. Analog Comparator Interrupt Enable (ACINTEN) Base 0x4003.C000 Offset 0x008 Type RW, reset 0x0000.
PAGE 1787
Tiva™ TM4C129ENCPDT Microcontroller Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 This register specifies whether the resistor ladder is powered on as well as the range and tap. Analog Comparator Reference Voltage Control (ACREFCTL) Base 0x4003.C000 Offset 0x010 Type RW, reset 0x0000.
PAGE 1788
Analog Comparators Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x060 These registers specify the current output value of the comparator. Analog Comparator Status n (ACSTATn) Base 0x4003.C000 Offset 0x020 Type RO, reset 0x0000.
PAGE 1789
Tiva™ TM4C129ENCPDT Microcontroller Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x024 Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x044 Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x064 These registers configure the comparator's input and output. Analog Comparator Control n (ACCTLn) Base 0x4003.C000 Offset 0x024 Type RW, reset 0x0000.
PAGE 1790
Analog Comparators Bit/Field Name Type Reset 6:5 TSEN RW 0x0 Description Trigger Sense The TSEN field specifies the sense of the comparator output that generates an ADC event. The sense conditioning is as follows: Value Description 4 ISLVAL RW 0 0x0 Level sense, see TSLVAL 0x1 Falling edge 0x2 Rising edge 0x3 Either edge Interrupt Sense Level Value Value Description 3:2 ISEN RW 0x0 0 An interrupt is generated if the comparator output is Low.
PAGE 1791
Tiva™ TM4C129ENCPDT Microcontroller Register 11: Analog Comparator Peripheral Properties (ACMPPP), offset 0xFC0 The ACMPPP register provides information regarding the properties of the analog comparator module. Analog Comparator Peripheral Properties (ACMPPP) Base 0x4003.C000 Offset 0xFC0 Type RO, reset 0x0007.
PAGE 1792
Analog Comparators Bit/Field Name Type Reset 1 CMP1 RO 0x1 Description Comparator 1 Present Value Description 0 CMP0 RO 0x1 0 Comparator 1 is not present. 1 Comparator 1 is present. Comparator 0 Present Value Description 0 Comparator 0 is not present. 1 Comparator 0 is present.
PAGE 1793
Tiva™ TM4C129ENCPDT Microcontroller 26 Pulse Width Modulator (PWM) Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control.
PAGE 1794
Pulse Width Modulator (PWM) ■ Can initiate an ADC sample sequence The control block determines the polarity of the PWM signals and which signals are passed through to the pins. The output of the PWM generation blocks are managed by the output control block before being passed to the device pins.
PAGE 1795
Tiva™ TM4C129ENCPDT Microcontroller Figure 26-1.
PAGE 1796
Pulse Width Modulator (PWM) 26.2 Signal Description The following table lists the external signals of the PWM module and describes the function of each. The PWM controller signals are alternate functions for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for these PWM signals.
PAGE 1797
Tiva™ TM4C129ENCPDT Microcontroller value, and continues counting down. In Count-Up/Down mode, the timer counts from zero up to the load value, back down to zero, back up to the load value, and so on. Generally, Count-Down mode is used for generating left- or right-aligned PWM signals, while the Count-Up/Down mode is used for generating center-aligned PWM signals.
PAGE 1798
Pulse Width Modulator (PWM) Figure 26-3. PWM Count-Down Mode LOAD COMPA COMPB 0 load zero cmpA cmpB dir BDown ADown Figure 26-4. PWM Count-Up/Down Mode LOAD COMPA COMPB 0 load zero cmpA cmpB dir BUp AUp 26.3.4 BDown ADown PWM Signal Generator Each PWM generator takes the load, zero, cmpA, and cmpB pulses (qualified by the dir signal) and generates two internal PWM signals, pwmA and pwmB.
PAGE 1799
Tiva™ TM4C129ENCPDT Microcontroller Figure 26-5. PWM Generation Example In Count-Up/Down Mode LOAD COMPA COMPB 0 pwmA pwmB In this example, the first generator is set to drive High on match A up, drive Low on match A down, and ignore the other four events. The second generator is set to drive High on match B up, drive Low on match B down, and ignore the other four events.
PAGE 1800
Pulse Width Modulator (PWM) within the pwmA or pwmB signal. Note that interrupts and ADC triggers are based on the raw events; delays in the PWM signal edges caused by the dead-band generator are not taken into account. 26.3.7 Synchronization Methods The PWM module provides four PWM generators, each providing two PWM outputs that may be used in a wide variety of applications. Generally speaking, the PWM is used in one of two categories of operation: ■ Unsynchronized.
PAGE 1801
Tiva™ TM4C129ENCPDT Microcontroller ■ Module-Level Register: PWMENABLE (based on the state of the ENUPDn bits in the PWMENUPD register). ■ Generator Register: PWMnGENA, PWMnGENB, PWMnDBCTL, PWMnDBRISE, and PWMnDBFALL (based on the state of various Update mode bits and fields in the PWMnCTL register (GENAUPD; GENBUPD; DBCTLUPD; DBRISEUPD; DBFALLUPD)).
PAGE 1802
Pulse Width Modulator (PWM) 26.3.9 Output Control Block The output control block takes care of the final conditioning of the pwmA' and pwmB' signals before they go to the pins as the MnPWMn signals. Via a single register, the PWM Output Enable (PWNENABLE) register, the set of PWM signals that are actually enabled to the pins can be modified.
PAGE 1803
Tiva™ TM4C129ENCPDT Microcontroller ■ Write the PWM0LOAD register with a value of 0x0000.018F. 8. Set the pulse width of the MnPWM0 pin for a 25% duty cycle. ■ Write the PWM0CMPA register with a value of 0x0000.012B. 9. Set the pulse width of the MnPWM1 pin for a 75% duty cycle. ■ Write the PWM0CMPB register with a value of 0x0000.0063. 10. Start the timers in PWM generator 0. ■ Write the PWM0CTL register with a value of 0x0000.0001. 11. Enable PWM outputs.
PAGE 1804
Pulse Width Modulator (PWM) Table 26-2. PWM Register Map (continued) Description See page 0x0000.0000 PWM0 Interrupt Status and Clear 1842 RW 0x0000.0000 PWM0 Load 1844 PWM0COUNT RO 0x0000.0000 PWM0 Counter 1845 0x058 PWM0CMPA RW 0x0000.0000 PWM0 Compare A 1846 0x05C PWM0CMPB RW 0x0000.0000 PWM0 Compare B 1847 0x060 PWM0GENA RW 0x0000.0000 PWM0 Generator A Control 1848 0x064 PWM0GENB RW 0x0000.0000 PWM0 Generator B Control 1851 0x068 PWM0DBCTL RW 0x0000.
PAGE 1805
Tiva™ TM4C129ENCPDT Microcontroller Table 26-2. PWM Register Map (continued) Description See page 0x0000.0000 PWM2 Interrupt Status and Clear 1842 RW 0x0000.0000 PWM2 Load 1844 PWM2COUNT RO 0x0000.0000 PWM2 Counter 1845 0x0D8 PWM2CMPA RW 0x0000.0000 PWM2 Compare A 1846 0x0DC PWM2CMPB RW 0x0000.0000 PWM2 Compare B 1847 0x0E0 PWM2GENA RW 0x0000.0000 PWM2 Generator A Control 1848 0x0E4 PWM2GENB RW 0x0000.0000 PWM2 Generator B Control 1851 0x0E8 PWM2DBCTL RW 0x0000.
PAGE 1806
Pulse Width Modulator (PWM) Table 26-2. PWM Register Map (continued) Description See page 0x0000.0000 PWM1 Fault Pin Logic Sense 1863 - 0x0000.0000 PWM1 Fault Status 0 1864 - 0x0000.0000 PWM1 Fault Status 1 1866 RW 0x0000.0000 PWM2 Fault Pin Logic Sense 1863 PWM2FLTSTAT0 - 0x0000.0000 PWM2 Fault Status 0 1864 0x908 PWM2FLTSTAT1 - 0x0000.0000 PWM2 Fault Status 1 1866 0x980 PWM3FLTSEN RW 0x0000.0000 PWM3 Fault Pin Logic Sense 1863 0x984 PWM3FLTSTAT0 - 0x0000.
PAGE 1807
Tiva™ TM4C129ENCPDT Microcontroller Register 1: PWM Master Control (PWMCTL), offset 0x000 This register provides master control over the PWM generation blocks. PWM Master Control (PWMCTL) 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 GLOBALSYNC3 GLOBALSYNC2 GLOBALSYNC1 GLOBALSYNC0 PWM0 base: 0x4002.8000 Offset 0x000 Type RW, reset 0x0000.
PAGE 1808
Pulse Width Modulator (PWM) Bit/Field Name Type Reset 1 GLOBALSYNC1 RW 0 Description Update PWM Generator 1 Value Description 0 No effect. 1 Any queued update to a load or comparator register in PWM generator 1 is applied the next time the corresponding counter becomes zero. This bit automatically clears when the updates have completed; it cannot be cleared by software. 0 GLOBALSYNC0 RW 0 Update PWM Generator 0 Value Description 0 No effect.
PAGE 1809
Tiva™ TM4C129ENCPDT Microcontroller Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 This register provides a method to perform synchronization of the counters in the PWM generation blocks. Setting a bit in this register causes the specified counter to reset back to 0; setting multiple bits resets multiple counters simultaneously. The bits auto-clear after the reset has occurred; reading them back as zero indicates that the synchronization has completed.
PAGE 1810
Pulse Width Modulator (PWM) Register 3: PWM Output Enable (PWMENABLE), offset 0x008 This register provides a master control of which generated pwmA' and pwmB' signals are output to the MnPWMn pins. By disabling a PWM output, the generation process can continue (for example, when the time bases are synchronized) without driving PWM signals to the pins. When bits in this register are set, the corresponding pwmA' or pwmB' signal is passed through to the output stage.
PAGE 1811
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 PWM4EN RW 0 Description MnPWM4 Output Enable Value Description 3 PWM3EN RW 0 0 The MnPWM4 signal has a zero value. 1 The generated pwm2A' signal is passed to the MnPWM4 pin. MnPWM3 Output Enable Value Description 2 PWM2EN RW 0 0 The MnPWM3 signal has a zero value. 1 The generated pwm1B' signal is passed to the MnPWM3 pin. MnPWM2 Output Enable Value Description 1 PWM1EN RW 0 0 The MnPWM2 signal has a zero value.
PAGE 1812
Pulse Width Modulator (PWM) Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C This register provides a master control of the polarity of the MnPWMn signals on the device pins. The pwmA' and pwmB' signals generated by the PWM generator are active High; but can be made active Low via this register. Disabled PWM channels are also passed through the output inverter (if so configured) so that inactive signals can be High.
PAGE 1813
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3 PWM3INV RW 0 Description Invert MnPWM3 Signal Value Description 2 PWM2INV RW 0 0 The MnPWM3 signal is not inverted. 1 The MnPWM3 signal is inverted. Invert MnPWM2 Signal Value Description 1 PWM1INV RW 0 0 The MnPWM2 signal is not inverted. 1 The MnPWM2 signal is inverted. Invert MnPWM1 Signal Value Description 0 PWM0INV RW 0 0 The MnPWM1 signal is not inverted. 1 The MnPWM1 signal is inverted.
PAGE 1814
Pulse Width Modulator (PWM) Register 5: PWM Output Fault (PWMFAULT), offset 0x010 This register controls the behavior of the MnPWMn outputs in the presence of fault conditions. Both the fault inputs (MnFAULTn pins and digital comparator outputs) and debug events are considered fault conditions. On a fault condition, each pwmA' or pwmB' signal can be passed through unmodified or driven to the value specified by the corresponding bit in the PWMFAULTVAL register.
PAGE 1815
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 FAULT4 RW 0 Description MnPWM4 Fault Value Description 3 FAULT3 RW 0 0 The generated pwm2A' signal is passed to the MnPWM4 pin. 1 The MnPWM4 output signal is driven to the value specified by the PWM4 bit in the PWMFAULTVAL register. MnPWM3 Fault Value Description 2 FAULT2 RW 0 0 The generated pwm1B' signal is passed to the MnPWM3 pin.
PAGE 1816
Pulse Width Modulator (PWM) Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 This register controls the global interrupt generation capabilities of the PWM module. The events that can cause an interrupt are the fault input and the individual interrupts from the PWM generators. Note: The "n" in the INTFAULTn and INTPWMn bits in this register correspond to the PWM generators, not to the FAULTn signals. PWM Interrupt Enable (PWMINTEN) PWM0 base: 0x4002.8000 Offset 0x014 Type RW, reset 0x0000.
PAGE 1817
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 16 INTFAULT0 RW 0 Description Interrupt Fault 0 Value Description 15:4 reserved RO 0x000 3 INTPWM3 RW 0 0 The fault condition for PWM generator 0 is suppressed and not sent to the interrupt controller. 1 An interrupt is sent to the interrupt controller when the fault condition for PWM generator 0 is asserted. Software should not rely on the value of a reserved bit.
PAGE 1818
Pulse Width Modulator (PWM) Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 This register provides the current set of interrupt sources that are asserted, regardless of whether they are enabled to cause an interrupt to be asserted to the interrupt controller. The fault interrupt is asserted based on the fault condition source that is specified by the PWMnCTL, PWMnFLTSRC0 and PWMnFLTSRC1 registers.
PAGE 1819
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 17 INTFAULT1 RO 0 Description Interrupt Fault PWM 1 Value Description 0 The fault condition for PWM generator 1 has not been asserted. 1 The fault condition for PWM generator 1 is asserted. Note: 16 INTFAULT0 RO 0 If the LATCH bit is set in the PWM1CTL register, the INTFAULT1 bit in this register can be cleared by writing a 1 to the INTFAULT1 bit in the PWMISC register.
PAGE 1820
Pulse Width Modulator (PWM) Bit/Field Name Type Reset 0 INTPWM0 RO 0 Description PWM0 Interrupt Asserted Value Description 0 The PWM generator 0 block interrupt has not been asserted. 1 The PWM generator 0 block interrupt is asserted. The PWM0RIS register shows the source of this interrupt. This bit is cleared by writing a 1 to the corresponding bit in the PWM0ISC register.
PAGE 1821
Tiva™ TM4C129ENCPDT Microcontroller Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C This register provides a summary of the interrupt status of the individual PWM generator blocks. If a fault interrupt is set, the corresponding MnFAULTn input has caused an interrupt. For the fault interrupt, a write of 1 to that bit position clears the latched interrupt status. If an block interrupt bit is set, the corresponding generator block is asserting an interrupt.
PAGE 1822
Pulse Width Modulator (PWM) Bit/Field Name Type Reset 17 INTFAULT1 RW1C 0 Description FAULT1 Interrupt Asserted Value Description 0 The fault condition for PWM generator 1 has not been asserted or is not enabled. 1 An enabled interrupt for the fault condition for PWM generator 1 is asserted or is latched. Writing a 1 to this bit clears it and the INTFAULT1 bit in the PWMRIS register.
PAGE 1823
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 0 INTPWM0 RO 0 Description PWM0 Interrupt Status Value Description 0 The PWM generator 0 block interrupt is not asserted or is not enabled. 1 An enabled interrupt for the PWM generator 0 block is asserted. The PWM0RIS register shows the source of this interrupt. This bit is cleared by writing a 1 to the corresponding bit in the PWM0ISC register.
PAGE 1824
Pulse Width Modulator (PWM) Register 9: PWM Status (PWMSTATUS), offset 0x020 This register provides the unlatched status of the PWM generator fault condition. PWM Status (PWMSTATUS) PWM0 base: 0x4002.8000 Offset 0x020 Type RO, reset 0x0000.
PAGE 1825
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 0 FAULT0 RO 0 Description Generator 0 Fault Status Value Description 0 The fault condition for PWM generator 0 is not asserted. 1 The fault condition for PWM generator 0 is asserted. If the FLTSRC bit in the PWM0CTL register is clear, the input is the source of the fault condition, and is therefore asserted.
PAGE 1826
Pulse Width Modulator (PWM) Register 10: PWM Fault Condition Value (PWMFAULTVAL), offset 0x024 This register specifies the output value driven on the MnPWMn signals during a fault condition if enabled by the corresponding bit in the PWMFAULT register. Note that if the corresponding bit in the PWMINVERT register is set, the output value is driven to the logical NOT of the bit value in this register. PWM Fault Condition Value (PWMFAULTVAL) PWM0 base: 0x4002.8000 Offset 0x024 Type RW, reset 0x0000.
PAGE 1827
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 PWM4 RW 0 Description MnPWM4 Fault Value Value Description 3 PWM3 RW 0 0 The MnPWM4 output signal is driven Low during fault conditions if the FAULT4 bit in the PWMFAULT register is set. 1 The MnPWM4 output signal is driven High during fault conditions if the FAULT4 bit in the PWMFAULT register is set.
PAGE 1828
Pulse Width Modulator (PWM) Register 11: PWM Enable Update (PWMENUPD), offset 0x028 This register specifies when updates to the PWMnEN bit in the PWMENABLE register are performed. The PWMnEN bit enables the pwmA' or pwmB' output to be passed to the microcontroller's pin. Updates can be immediate or locally or globally synchronized to the next synchronous update. PWM Enable Update (PWMENUPD) PWM0 base: 0x4002.8000 Offset 0x028 Type RW, reset 0x0000.
PAGE 1829
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 13:12 ENUPD6 RW 0 Description MnPWM6 Enable Update Mode Value Description 0x0 Immediate Writes to the PWM6EN bit in the PWMENABLE register are used by the PWM generator immediately. 0x1 Reserved 0x2 Locally Synchronized Writes to the PWM6EN bit in the PWMENABLE register are used by the PWM generator the next time the counter is 0.
PAGE 1830
Pulse Width Modulator (PWM) Bit/Field Name Type Reset 7:6 ENUPD3 RW 0 Description MnPWM3 Enable Update Mode Value Description 0x0 Immediate Writes to the PWM3EN bit in the PWMENABLE register are used by the PWM generator immediately. 0x1 Reserved 0x2 Locally Synchronized Writes to the PWM3EN bit in the PWMENABLE register are used by the PWM generator the next time the counter is 0.
PAGE 1831
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 1:0 ENUPD0 RW 0 Description MnPWM0 Enable Update Mode Value Description 0x0 Immediate Writes to the PWM0EN bit in the PWMENABLE register are used by the PWM generator immediately. 0x1 Reserved 0x2 Locally Synchronized Writes to the PWM0EN bit in the PWMENABLE register are used by the PWM generator the next time the counter is 0.
PAGE 1832
Pulse Width Modulator (PWM) Register 12: PWM0 Control (PWM0CTL), offset 0x040 Register 13: PWM1 Control (PWM1CTL), offset 0x080 Register 14: PWM2 Control (PWM2CTL), offset 0x0C0 Register 15: PWM3 Control (PWM3CTL), offset 0x100 These registers configure the PWM signal generation blocks (PWM0CTL controls the PWM generator 0 block, and so on). The Register Update mode, Debug mode, Counting mode, and Block Enable mode are all controlled via these registers.
PAGE 1833
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 17 MINFLTPER RW 0 Description Minimum Fault Period This bit specifies that the PWM generator enables a one-shot counter to provide a minimum fault condition period. The timer begins counting on the rising edge of the fault condition to extend the condition for a minimum duration of the count value. The timer ignores the state of the fault condition while counting. The minimum fault delay is in effect only when the MINFLTPER bit is set.
PAGE 1834
Pulse Width Modulator (PWM) Bit/Field Name Type Reset 13:12 DBRISEUPD RW 0x0 Description PWMnDBRISE Update Mode Value Description 0x0 Immediate The PWMnDBRISE register value is immediately updated on a write. 0x1 Reserved 0x2 Locally Synchronized Updates to the register are reflected to the generator the next time the counter is 0.
PAGE 1835
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 7:6 GENAUPD RW 0x0 Description PWMnGENA Update Mode Value Description 0x0 Immediate The PWMnGENA register value is immediately updated on a write. 0x1 Reserved 0x2 Locally Synchronized Updates to the register are reflected to the generator the next time the counter is 0.
PAGE 1836
Pulse Width Modulator (PWM) Bit/Field Name Type Reset 2 DEBUG RW 0 Description Debug Mode Value Description 1 MODE RW 0 0 The counter stops running when it next reaches 0 and continues running again when no longer in Debug mode. 1 The counter always runs when in Debug mode. Counter Mode Value Description 0 ENABLE RW 0 0 The counter counts down from the load value to 0 and then wraps back to the load value (Count-Down mode).
PAGE 1837
Tiva™ TM4C129ENCPDT Microcontroller Register 16: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 Register 17: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 Register 18: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 Register 19: PWM3 Interrupt and Trigger Enable (PWM3INTEN), offset 0x104 These registers control the interrupt and ADC trigger generation capabilities of the PWM generators (PWM0INTEN controls the PWM generator 0 block, and so on).
PAGE 1838
Pulse Width Modulator (PWM) Bit/Field Name Type Reset 12 TRCMPBU RW 0 Description Trigger for Counter=PWMnCMPB Up Value Description 11 TRCMPAD RW 0 0 No ADC trigger is output. 1 An ADC trigger pulse is output when the counter matches the value in the PWMnCMPB register value while counting up. Trigger for Counter=PWMnCMPA Down Value Description 10 TRCMPAU RW 0 0 No ADC trigger is output.
PAGE 1839
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 4 INTCMPBU RW 0 Description Interrupt for Counter=PWMnCMPB Up Value Description 3 INTCMPAD RW 0 0 No interrupt. 1 A raw interrupt occurs when the counter matches the value in the PWMnCMPB register value while counting up. Interrupt for Counter=PWMnCMPA Down Value Description 2 INTCMPAU RW 0 0 No interrupt. 1 A raw interrupt occurs when the counter matches the value in the PWMnCMPA register value while counting down.
PAGE 1840
Pulse Width Modulator (PWM) Register 20: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 Register 21: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 Register 22: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 Register 23: PWM3 Raw Interrupt Status (PWM3RIS), offset 0x108 These registers provide the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller (PWM0RIS controls the PWM generator 0 block, and so on).
PAGE 1841
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3 INTCMPAD RO 0 Description Comparator A Down Interrupt Status Value Description 0 An interrupt has not occurred. 1 The counter has matched the value in the PWMnCMPA register while counting down. This bit is cleared by writing a 1 to the INTCMPAD bit in the PWMnISC register. 2 INTCMPAU RO 0 Comparator A Up Interrupt Status Value Description 0 An interrupt has not occurred.
PAGE 1842
Pulse Width Modulator (PWM) Register 24: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C Register 25: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C Register 26: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC Register 27: PWM3 Interrupt Status and Clear (PWM3ISC), offset 0x10C These registers provide the current set of interrupt sources that are asserted to the interrupt controller (PWM0ISC controls the PWM generator 0 block, and so on).
PAGE 1843
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3 INTCMPAD RW1C 0 Description Comparator A Down Interrupt Value Description 0 No interrupt has occurred or the interrupt is masked. 1 The INTCMPAD bits in the PWMnRIS and PWMnINTEN registers are set, providing an interrupt to the interrupt controller. This bit is cleared by writing a 1. Clearing this bit also clears the INTCMPAD bit in the PWMnRIS register.
PAGE 1844
Pulse Width Modulator (PWM) Register 28: PWM0 Load (PWM0LOAD), offset 0x050 Register 29: PWM1 Load (PWM1LOAD), offset 0x090 Register 30: PWM2 Load (PWM2LOAD), offset 0x0D0 Register 31: PWM3 Load (PWM3LOAD), offset 0x110 These registers contain the load value for the PWM counter (PWM0LOAD controls the PWM generator 0 block, and so on).
PAGE 1845
Tiva™ TM4C129ENCPDT Microcontroller Register 32: PWM0 Counter (PWM0COUNT), offset 0x054 Register 33: PWM1 Counter (PWM1COUNT), offset 0x094 Register 34: PWM2 Counter (PWM2COUNT), offset 0x0D4 Register 35: PWM3 Counter (PWM3COUNT), offset 0x114 These registers contain the current value of the PWM counter (PWM0COUNT is the value of the PWM generator 0 block, and so on).
PAGE 1846
Pulse Width Modulator (PWM) Register 36: PWM0 Compare A (PWM0CMPA), offset 0x058 Register 37: PWM1 Compare A (PWM1CMPA), offset 0x098 Register 38: PWM2 Compare A (PWM2CMPA), offset 0x0D8 Register 39: PWM3 Compare A (PWM3CMPA), offset 0x118 These registers contain a value to be compared against the counter (PWM0CMPA controls the PWM generator 0 block, and so on).
PAGE 1847
Tiva™ TM4C129ENCPDT Microcontroller Register 40: PWM0 Compare B (PWM0CMPB), offset 0x05C Register 41: PWM1 Compare B (PWM1CMPB), offset 0x09C Register 42: PWM2 Compare B (PWM2CMPB), offset 0x0DC Register 43: PWM3 Compare B (PWM3CMPB), offset 0x11C These registers contain a value to be compared against the counter (PWM0CMPB controls the PWM generator 0 block, and so on).
PAGE 1848
Pulse Width Modulator (PWM) Register 44: PWM0 Generator A Control (PWM0GENA), offset 0x060 Register 45: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 Register 46: PWM2 Generator A Control (PWM2GENA), offset 0x0E0 Register 47: PWM3 Generator A Control (PWM3GENA), offset 0x120 These registers control the generation of the pwmA signal based on the load and zero output pulses from the counter, as well as the compare A and compare B pulses from the comparators (PWM0GENA controls the PWM generator 0 block, a
PAGE 1849
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 11:10 ACTCMPBD RW 0x0 Description Action for Comparator B Down This field specifies the action to be taken when the counter matches comparator B while counting down. Value Description 9:8 ACTCMPBU RW 0x0 0x0 Do nothing. 0x1 Invert pwmA. 0x2 Drive pwmA Low. 0x3 Drive pwmA High. Action for Comparator B Up This field specifies the action to be taken when the counter matches comparator B while counting up.
PAGE 1850
Pulse Width Modulator (PWM) Bit/Field Name Type Reset 3:2 ACTLOAD RW 0x0 Description Action for Counter=LOAD This field specifies the action to be taken when the counter matches the value in the PWMnLOAD register. Value Description 1:0 ACTZERO RW 0x0 0x0 Do nothing. 0x1 Invert pwmA. 0x2 Drive pwmA Low. 0x3 Drive pwmA High. Action for Counter=0 This field specifies the action to be taken when the counter is zero. Value Description 0x0 Do nothing. 0x1 Invert pwmA.
PAGE 1851
Tiva™ TM4C129ENCPDT Microcontroller Register 48: PWM0 Generator B Control (PWM0GENB), offset 0x064 Register 49: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 Register 50: PWM2 Generator B Control (PWM2GENB), offset 0x0E4 Register 51: PWM3 Generator B Control (PWM3GENB), offset 0x124 These registers control the generation of the pwmB signal based on the load and zero output pulses from the counter, as well as the compare A and compare B pulses from the comparators (PWM0GENB controls the PWM generator 0
PAGE 1852
Pulse Width Modulator (PWM) Bit/Field Name Type Reset 11:10 ACTCMPBD RW 0x0 Description Action for Comparator B Down This field specifies the action to be taken when the counter matches comparator B while counting down. Value Description 9:8 ACTCMPBU RW 0x0 0x0 Do nothing. 0x1 Invert pwmB. 0x2 Drive pwmB Low. 0x3 Drive pwmB High. Action for Comparator B Up This field specifies the action to be taken when the counter matches comparator B while counting up.
PAGE 1853
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3:2 ACTLOAD RW 0x0 Description Action for Counter=LOAD This field specifies the action to be taken when the counter matches the load value. Value Description 1:0 ACTZERO RW 0x0 0x0 Do nothing. 0x1 Invert pwmB. 0x2 Drive pwmB Low. 0x3 Drive pwmB High. Action for Counter=0 This field specifies the action to be taken when the counter is 0. Value Description 0x0 Do nothing. 0x1 Invert pwmB. 0x2 Drive pwmB Low.
PAGE 1854
Pulse Width Modulator (PWM) Register 52: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 Register 53: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 Register 54: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 Register 55: PWM3 Dead-Band Control (PWM3DBCTL), offset 0x128 The PWMnDBCTL register controls the dead-band generator, which produces the MnPWMn signals based on the pwmA and pwmB signals.
PAGE 1855
Tiva™ TM4C129ENCPDT Microcontroller Register 56: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C Register 57: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC Register 58: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC Register 59: PWM3 Dead-Band Rising-Edge Delay (PWM3DBRISE), offset 0x12C The PWMnDBRISE register contains the number of clock cycles to delay the rising edge of the pwmA signal when generating the pwmA' signal.
PAGE 1856
Pulse Width Modulator (PWM) Register 60: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 Register 61: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 Register 62: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 Register 63: PWM3 Dead-Band Falling-Edge-Delay (PWM3DBFALL), offset 0x130 The PWMnDBFALL register contains the number of clock cycles to delay the rising edge of the pwmB' signal from the falling edge of the pwmA signal.
PAGE 1857
Tiva™ TM4C129ENCPDT Microcontroller Register 64: PWM0 Fault Source 0 (PWM0FLTSRC0), offset 0x074 Register 65: PWM1 Fault Source 0 (PWM1FLTSRC0), offset 0x0B4 Register 66: PWM2 Fault Source 0 (PWM2FLTSRC0), offset 0x0F4 Register 67: PWM3 Fault Source 0 (PWM3FLTSRC0), offset 0x134 This register specifies which fault pin inputs are used to generate a fault condition. Each bit in the following register indicates whether the corresponding fault pin is included in the fault condition.
PAGE 1858
Pulse Width Modulator (PWM) Bit/Field Name Type Reset 2 FAULT2 RW 0 Description Fault2 Input Value Description 0 The Fault2 signal is suppressed and cannot generate a fault condition. 1 The Fault2 signal value is ORed with all other fault condition generation inputs (Faultn signals and digital comparators). Note: 1 FAULT1 RW 0 The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation.
PAGE 1859
Tiva™ TM4C129ENCPDT Microcontroller Register 68: PWM0 Fault Source 1 (PWM0FLTSRC1), offset 0x078 Register 69: PWM1 Fault Source 1 (PWM1FLTSRC1), offset 0x0B8 Register 70: PWM2 Fault Source 1 (PWM2FLTSRC1), offset 0x0F8 Register 71: PWM3 Fault Source 1 (PWM3FLTSRC1), offset 0x138 This register specifies which digital comparator triggers from the ADC are used to generate a fault condition.
PAGE 1860
Pulse Width Modulator (PWM) Bit/Field Name Type Reset 6 DCMP6 RW 0 Description Digital Comparator 6 Value Description 0 The trigger from digital comparator 6 is suppressed and cannot generate a fault condition. 1 The trigger from digital comparator 6 is ORed with all other fault condition generation inputs (Faultn signals and digital comparators). Note: 5 DCMP5 RW 0 The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation.
PAGE 1861
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 2 DCMP2 RW 0 Description Digital Comparator 2 Value Description 0 The trigger from digital comparator 2 is suppressed and cannot generate a fault condition. 1 The trigger from digital comparator 2 is ORed with all other fault condition generation inputs (Faultn signals and digital comparators). Note: 1 DCMP1 RW 0 The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation.
PAGE 1862
Pulse Width Modulator (PWM) Register 72: PWM0 Minimum Fault Period (PWM0MINFLTPER), offset 0x07C Register 73: PWM1 Minimum Fault Period (PWM1MINFLTPER), offset 0x0BC Register 74: PWM2 Minimum Fault Period (PWM2MINFLTPER), offset 0x0FC Register 75: PWM3 Minimum Fault Period (PWM3MINFLTPER), offset 0x13C If the MINFLTPER bit in the PWMnCTL register is set, this register specifies the 16-bit time-extension value to be used in extending the fault condition.
PAGE 1863
Tiva™ TM4C129ENCPDT Microcontroller Register 76: PWM0 Fault Pin Logic Sense (PWM0FLTSEN), offset 0x800 Register 77: PWM1 Fault Pin Logic Sense (PWM1FLTSEN), offset 0x880 Register 78: PWM2 Fault Pin Logic Sense (PWM2FLTSEN), offset 0x900 Register 79: PWM3 Fault Pin Logic Sense (PWM3FLTSEN), offset 0x980 This register defines the PWM fault pin logic sense. PWMn Fault Pin Logic Sense (PWMnFLTSEN) PWM0 base: 0x4002.8000 Offset 0x800 Type RW, reset 0x0000.
PAGE 1864
Pulse Width Modulator (PWM) Register 80: PWM0 Fault Status 0 (PWM0FLTSTAT0), offset 0x804 Register 81: PWM1 Fault Status 0 (PWM1FLTSTAT0), offset 0x884 Register 82: PWM2 Fault Status 0 (PWM2FLTSTAT0), offset 0x904 Register 83: PWM3 Fault Status 0 (PWM3FLTSTAT0), offset 0x984 Along with the PWMnFLTSTAT1 register, this register provides status regarding the fault condition inputs.
PAGE 1865
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset Description 2 FAULT2 - 0 Fault Input 2 If the PWMnCTL register LATCH bit is clear, this bit is RO and represents the current state of the MnFAULT2 input signal after the logic sense adjustment. If the PWMnCTL register LATCH bit is set, this bit is RW1C and represents a sticky version of the MnFAULT2 input signal after the logic sense adjustment.
PAGE 1866
Pulse Width Modulator (PWM) Register 84: PWM0 Fault Status 1 (PWM0FLTSTAT1), offset 0x808 Register 85: PWM1 Fault Status 1 (PWM1FLTSTAT1), offset 0x888 Register 86: PWM2 Fault Status 1 (PWM2FLTSTAT1), offset 0x908 Register 87: PWM3 Fault Status 1 (PWM3FLTSTAT1), offset 0x988 Along with the PWMnFLTSTAT0 register, this register provides status regarding the fault condition inputs.
PAGE 1867
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 6 DCMP6 - 0 Description Digital Comparator 6 Trigger If the PWMnCTL register LATCH bit is clear, this bit represents the current state of the Digital Comparator 6 trigger input. If the PWMnCTL register LATCH bit is set, this bit represents a sticky version of the trigger. 5 DCMP5 - 0 ■ If DCMP6 is set, the trigger transitioned to the active state previously.
PAGE 1868
Pulse Width Modulator (PWM) Bit/Field Name Type Reset 2 DCMP2 - 0 Description Digital Comparator 2 Trigger If the PWMnCTL register LATCH bit is clear, this bit represents the current state of the Digital Comparator 2 trigger input. If the PWMnCTL register LATCH bit is set, this bit represents a sticky version of the trigger. 1 DCMP1 - 0 ■ If DCMP2 is set, the trigger transitioned to the active state previously.
PAGE 1869
Tiva™ TM4C129ENCPDT Microcontroller Register 88: PWM Peripheral Properties (PWMPP), offset 0xFC0 The PWMPP register provides information regarding the properties of the PWM module. PWM Peripheral Properties (PWMPP) PWM0 base: 0x4002.8000 Offset 0xFC0 Type RO, reset 0x0000.
PAGE 1870
Pulse Width Modulator (PWM) Bit/Field Name Type Reset Description 3:0 GCNT RO 0x4 Generators Value Description 0x0 No generators. 0x1 1 generator 0x2 2 generators 0x3 3 generators 0x4 4 generators 0x5 - 0xF reserved The number of PWM outputs is 2 times the number of PWM generators.
PAGE 1871
Tiva™ TM4C129ENCPDT Microcontroller Register 89: PWM Clock Configuration (PWMCC), offset 0xFC8 The PWMCC register controls the clock source for the PWM module. PWM Clock Configuration (PWMCC) PWM0 base: 0x4002.8000 Offset 0xFC8 Type RW, reset 0x0000.
PAGE 1872
Quadrature Encoder Interface (QEI) 27 Quadrature Encoder Interface (QEI) A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals, you can track the position, direction of rotation, and speed. In addition, a third channel, or index signal, can be used to reset the position counter.
PAGE 1873
Tiva™ TM4C129ENCPDT Microcontroller Figure 27-1. QEI Block Diagram QEILOAD Velocity Timer Control & Status QEITIME QEICTL QEISTAT Velocity Accumulator Velocity Predivider PhA PhB QEICOUNT QEISPEED clk Quadrature Encoder dir QEIMAXPOS Position Integrator QEIPOS IDX QEIINTEN Interrupt Control Interrupt QEIRIS QEIISC Figure 27-2 on page 1874 shows the logic that is provided to allow the PhAn and PhBn signals to be inverted and/or swapped.
PAGE 1874
Quadrature Encoder Interface (QEI) Figure 27-2. QEI Input Signal Logic PhAn QEICTL.INVA 1 0 QEICTL.INVB QEICTL.SWAP PhA PhBn 1 PhB clk Quadrature Encoder dir 0 QEICTL.SWAP 27.2 Signal Description The following table lists the external signals of the QEI module and describes the function of each. The QEI signals are alternate functions for some GPIO signals and default to be GPIO signals at reset.
PAGE 1875
Tiva™ TM4C129ENCPDT Microcontroller of forward and backward and to correct for miswiring of the system. Alternatively, the phase signals can be interpreted as a clock and direction signal as output by some encoders. The QEI module input signals have a digital noise filter on them that can be enabled to prevent spurious operation. The noise filter requires that the inputs be stable for a specified number of consecutive clock cycles before updating the edge detector.
PAGE 1876
Quadrature Encoder Interface (QEI) Figure 27-3. Quadrature Encoder and Velocity Predivider Operation PhA PhB clk clkdiv dir pos -1 -1 -1 -1 -1 -1 -1 -1 -1 rel +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 The period of the timer is configurable by specifying the load value for the timer in the QEI Timer Load (QEILOAD) register.
PAGE 1877
Tiva™ TM4C129ENCPDT Microcontroller could use a load value of 82, resulting in 32,800 as the divisor, which is 0.09% above 214. In this case a shift by 15 would be an adequate approximation of the divide in most cases. If absolute accuracy were required, the microcontroller's divide instruction could be used. The QEI module can produce a controller interrupt on several events: phase error, direction change, reception of the index pulse, and expiration of the velocity timer.
PAGE 1878
Quadrature Encoder Interface (QEI) Note that the QEI module clock must be enabled before the registers can be programmed (see page 406). There must be a delay of 3 system clocks after the QEI module clock is enabled before any QEI module registers are accessed. Table 27-2. QEI Register Map Type Reset Description See page QEICTL RW 0x0000.0000 QEI Control 1879 0x004 QEISTAT RO 0x0000.0000 QEI Status 1882 0x008 QEIPOS RW 0x0000.0000 QEI Position 1883 0x00C QEIMAXPOS RW 0x0000.
PAGE 1879
Tiva™ TM4C129ENCPDT Microcontroller Register 1: QEI Control (QEICTL), offset 0x000 This register contains the configuration of the QEI module. Separate enables are provided for the quadrature encoder and the velocity capture blocks; the quadrature encoder must be enabled in order to capture the velocity, but the velocity does not need to be captured in applications that do not need it.
PAGE 1880
Quadrature Encoder Interface (QEI) Bit/Field Name Type Reset 11 INVI RW 0 Description Invert Index Pulse Value Description 10 INVB RW 0 0 No effect. 1 Inverts the IDX input. Invert PhB Value Description 9 INVA RW 0 0 No effect. 1 Inverts the PhBn input. Invert PhA Value Description 8:6 VELDIV RW 0x0 0 No effect. 1 Inverts the PhAn input. Predivide Velocity This field defines the predivider of the input quadrature pulses before being applied to the QEICOUNT accumulator.
PAGE 1881
Tiva™ TM4C129ENCPDT Microcontroller Bit/Field Name Type Reset 3 CAPMODE RW 0 Description Capture Mode Note: When SIGMODE=1, the CAPMODE setting is not applicable and is reserved. Value Description 2 SIGMODE RW 0 0 Only the PhA edges are counted. 1 The PhA and PhB edges are counted, providing twice the positional resolution but half the range. Signal Mode Value Description 1 SWAP RW 0 0 The internal PhA and PhB signals operate as quadrature phase signals.
PAGE 1882
Quadrature Encoder Interface (QEI) Register 2: QEI Status (QEISTAT), offset 0x004 This register provides status about the operation of the QEI module. QEI Status (QEISTAT) QEI0 base: 0x4002.C000 Offset 0x004 Type RO, reset 0x0000.
PAGE 1883
Tiva™ TM4C129ENCPDT Microcontroller Register 3: QEI Position (QEIPOS), offset 0x008 This register contains the current value of the position integrator. The value is updated by the status of the QEI phase inputs and can be set to a specific value by writing to it. QEI Position (QEIPOS) QEI0 base: 0x4002.C000 Offset 0x008 Type RW, reset 0x0000.
PAGE 1884
Quadrature Encoder Interface (QEI) Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C This register contains the maximum value of the position integrator. When moving forward, the position register resets to zero when it increments past this value. When moving in reverse, the position register resets to this value when it decrements from zero. QEI Maximum Position (QEIMAXPOS) QEI0 base: 0x4002.C000 Offset 0x00C Type RW, reset 0x0000.
PAGE 1885
Tiva™ TM4C129ENCPDT Microcontroller Register 5: QEI Timer Load (QEILOAD), offset 0x010 This register contains the load value for the velocity timer. Because this value is loaded into the timer on the clock cycle after the timer is zero, this value should be one less than the number of clocks in the desired period. So, for example, to have 2000 decimal clocks per timer period, this register should contain 1999 decimal. QEI Timer Load (QEILOAD) QEI0 base: 0x4002.C000 Offset 0x010 Type RW, reset 0x0000.
PAGE 1886
Quadrature Encoder Interface (QEI) Register 6: QEI Timer (QEITIME), offset 0x014 This register contains the current value of the velocity timer. This counter does not increment when the VELEN bit in the QEICTL register is clear. QEI Timer (QEITIME) QEI0 base: 0x4002.C000 Offset 0x014 Type RO, reset 0x0000.
PAGE 1887
Tiva™ TM4C129ENCPDT Microcontroller Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 This register contains the running count of velocity pulses for the current time period. Because this count is a running total, the time period to which it applies cannot be known with precision (that is, a read of this register does not necessarily correspond to the time returned by the QEITIME register because there is a small window of time between the two reads, during which either value may have changed).
PAGE 1888
Quadrature Encoder Interface (QEI) Register 8: QEI Velocity (QEISPEED), offset 0x01C This register contains the most recently measured velocity of the quadrature encoder. This value corresponds to the number of velocity pulses counted in the previous velocity timer period. This register does not update when the VELEN bit in the QEICTL register is clear. QEI Velocity (QEISPEED) QEI0 base: 0x4002.C000 Offset 0x01C Type RO, reset 0x0000.
PAGE 1889
Tiva™ TM4C129ENCPDT Microcontroller Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 This register contains enables for each of the QEI module interrupts. An interrupt is asserted to the interrupt controller if the corresponding bit in this register is set. QEI Interrupt Enable (QEIINTEN) QEI0 base: 0x4002.C000 Offset 0x020 Type RW, reset 0x0000.
PAGE 1890
Quadrature Encoder Interface (QEI) Bit/Field Name Type Reset 0 INTINDEX RW 0 Description Index Pulse Detected Interrupt Enable Value Description 0 The INTINDEX interrupt is suppressed and not sent to the interrupt controller. 1 An interrupt is sent to the interrupt controller when the INTINDEX bit in the QEIRIS register is set.
PAGE 1891
Tiva™ TM4C129ENCPDT Microcontroller Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 This register provides the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller (configured through the QEIINTEN register). If a bit is set, the latched event has occurred; if a bit is clear, the event in question has not occurred. QEI Raw Interrupt Status (QEIRIS) QEI0 base: 0x4002.C000 Offset 0x024 Type RO, reset 0x0000.
PAGE 1892
Quadrature Encoder Interface (QEI) Bit/Field Name Type Reset 0 INTINDEX RO 0 Description Index Pulse Asserted Value Description 0 An interrupt has not occurred. 1 The index pulse has occurred. This bit is cleared by writing a 1 to the INTINDEX bit in the QEIISC register.
PAGE 1893
Tiva™ TM4C129ENCPDT Microcontroller Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 This register provides the current set of interrupt sources that are asserted to the controller. If a bit is set, the latched event has occurred and is enabled to generate an interrupt; if a bit is clear the event in question has not occurred or is not enabled to generate an interrupt. This register is RW1C; writing a 1 to a bit position clears the bit and the corresponding interrupt reason.
PAGE 1894
Quadrature Encoder Interface (QEI) Bit/Field Name Type Reset 0 INTINDEX RW1C 0 Description Index Pulse Interrupt Value Description 0 No interrupt has occurred or the interrupt is masked. 1 The INTINDEX bits in the QEIRIS register and the QEIINTEN registers are set, providing an interrupt to the interrupt controller. This bit is cleared by writing a 1. Clearing this bit also clears the INTINDEX bit in the QEIRIS register.
PAGE 1895
Tiva™ TM4C129ENCPDT Microcontroller 28 Pin Diagram The TM4C129ENCPDT microcontroller pin diagram is shown below. Each GPIO signal is identified by its GPIO port unless it defaults to an alternate function on reset. In this case, the GPIO port name is followed by the default alternate function. To see a complete list of possible functions for each pin, see Table 29-5 on page 1932. Figure 28-1.
PAGE 1896
Signal Tables 29 Signal Tables The following tables list the signals available for each pin. Signals are configured as GPIOs on reset, except for those noted below. Use the GPIOAMSEL register (see page 794) to select analog mode. For a GPIO pin to be used for an alternate digital function, the corresponding bit in the GPIOAFSEL register (see page 778) must be set.
PAGE 1897
Tiva™ TM4C129ENCPDT Microcontroller Note: 29.1 All digital inputs are Schmitt triggered. Signals by Pin Number Table 29-2. Signals by Pin Number Pin Number 1 2 3 4 5 6 7 8 Pin Name Pin Type PD0 I/O Buffer Type Description TTL AIN15 I Analog GPIO port D bit 0. Analog-to-digital converter input 15. C0o O TTL Analog comparator 0 output. I2C7SCL I/O OD I2C module 7 clock. Note that this signal has an active pull-up. The corresponding port pin should not be configured as open drain.
PAGE 1898
Signal Tables Table 29-2. Signals by Pin Number (continued) Pin Number Pin Name Pin Type Buffer Type Description VREFA+ - Analog A reference voltage used to specify the voltage at which the ADC converts to a maximum value. This pin is used in conjunction with GNDA. The voltage that is applied to VREFA+ is the voltage with which an AINn signal is converted to 4095. The VREFA+ voltage is limited to the range specified in Table 30-44 on page 1985.
PAGE 1899
Tiva™ TM4C129ENCPDT Microcontroller Table 29-2. Signals by Pin Number (continued) Pin Number Pin Name Pin Type PC7 I/O TTL C0- I Analog EPI0S4 I/O TTL EPI module 0 signal 4. U5Tx O TTL UART module 5 transmit. PC6 I/O TTL GPIO port C bit 6. 22 27 28 29 30 31 32 Analog comparator 0 negative input. C0+ I Analog I/O TTL EPI module 0 signal 5. U5Rx I TTL UART module 5 receive. PC5 I/O TTL GPIO port C bit 5. C1+ I Analog EPI0S6 I/O TTL EPI module 0 signal 6.
PAGE 1900
Signal Tables Table 29-2. Signals by Pin Number (continued) Pin Number 33 34 35 36 37 38 39 Pin Name Pin Type Buffer Type Description PA0 I/O TTL GPIO port A bit 0. CAN0Rx I TTL CAN module 0 receive. I2C9SCL I/O OD I2C module 9 clock. Note that this signal has an active pull-up. The corresponding port pin should not be configured as open drain. T0CCP0 I/O TTL 16/32-Bit Timer 0 Capture/Compare/PWM 0. U0Rx I TTL UART module 0 receive. PA1 I/O TTL GPIO port A bit 1.
PAGE 1901
Tiva™ TM4C129ENCPDT Microcontroller Table 29-2. Signals by Pin Number (continued) Pin Number 40 41 Pin Name Pin Type Buffer Type Description PA6 I/O TTL GPIO port A bit 6. EPI0S8 I/O TTL EPI module 0 signal 8. I2C6SCL I/O OD I2C module 6 clock. Note that this signal has an active pull-up. The corresponding port pin should not be configured as open drain. SSI0XDAT2 I/O TTL SSI Module 0 Bi-directional Data Pin 2. T3CCP0 I/O TTL 16/32-Bit Timer 3 Capture/Compare/PWM 0.
PAGE 1902
Signal Tables Table 29-2. Signals by Pin Number (continued) Pin Number Pin Name Pin Type Buffer Type Description PF4 I/O TTL GPIO port F bit 4. EN0LED1 O TTL Ethernet 0 LED 1. M0FAULT0 I TTL Motion Control Module 0 PWM Fault 0. SSI3XDAT2 I/O TTL SSI Module 3 Bi-directional Data Pin 2. TRD3 O TTL Trace data 3. 47 VDD - Power Positive supply for I/O and some logic. 48 GND - Power Ground reference for logic and I/O pins. PG0 I/O TTL GPIO port G bit 0.
PAGE 1903
Tiva™ TM4C129ENCPDT Microcontroller Table 29-2. Signals by Pin Number (continued) Pin Number Pin Name Pin Type Buffer Type Description PK5 I/O TTL GPIO port K bit 5. EN0LED2 O TTL Ethernet 0 LED 2. EPI0S31 I/O TTL EPI module 0 signal 31. I2C3SDA I/O OD I2C module 3 data. M0PWM7 O TTL Motion Control Module 0 PWM 7. This signal is controlled by Module 0 PWM Generator 3. PK4 I/O TTL GPIO port K bit 4. EN0LED0 O TTL Ethernet 0 LED 0. EPI0S32 I/O TTL EPI module 0 signal 32.
PAGE 1904
Signal Tables Table 29-2. Signals by Pin Number (continued) Pin Number Pin Name Pin Type PM3 I/O TTL GPIO port M bit 3. 75 EPI0S12 I/O TTL EPI module 0 signal 12. T3CCP1 I/O TTL 16/32-Bit Timer 3 Capture/Compare/PWM 1. PM2 I/O TTL GPIO port M bit 2. EPI0S13 I/O TTL EPI module 0 signal 13. T3CCP0 I/O TTL 16/32-Bit Timer 3 Capture/Compare/PWM 0. PM1 I/O TTL GPIO port M bit 1. EPI0S14 I/O TTL EPI module 0 signal 14. T2CCP1 I/O TTL 16/32-Bit Timer 2 Capture/Compare/PWM 1.
PAGE 1905
Tiva™ TM4C129ENCPDT Microcontroller Table 29-2. Signals by Pin Number (continued) Pin Number Pin Name Pin Type Buffer Type Description PL5 I/O TTL GPIO port L bit 5. EPI0S33 I/O TTL EPI module 0 signal 33. T0CCP1 I/O TTL 16/32-Bit Timer 0 Capture/Compare/PWM 1. USB0D5 I/O TTL USB data 5. VDDC - Power Positive supply for most of the logic function, including the processor core and most peripherals. The voltage on this pin is 1.2 V and is supplied by the on-chip LDO.
PAGE 1906
Signal Tables Table 29-2. Signals by Pin Number (continued) Pin Number 96 97 Pin Name Pin Type PB1 I/O TTL GPIO port B bit 1. CAN1Tx O TTL CAN module 1 transmit. I2C5SDA I/O OD I2C module 5 data. T4CCP1 I/O TTL 16/32-Bit Timer 4 Capture/Compare/PWM 1. U1Tx O TTL UART module 1 transmit. USB0VBUS I/O Analog PC3 I/O TTL GPIO port C bit 3. SWO O TTL JTAG TDO and SWO. TDO O TTL JTAG TDO and SWO. PC2 I/O TTL GPIO port C bit 2. TDI I TTL JTAG TDI.
PAGE 1907
Tiva™ TM4C129ENCPDT Microcontroller Table 29-2. Signals by Pin Number (continued) Pin Number Pin Name Pin Type Buffer Type Description PP5 I/O TTL GPIO port P bit 5. I2C2SCL I/O OD I2C module 2 clock. Note that this signal has an active pull-up. The corresponding port pin should not be configured as open drain. U3CTS I TTL UART module 3 Clear To Send modem flow control input signal. USB0D6 I/O TTL USB data 6. 106 PN0 I/O TTL GPIO port N bit 0.
PAGE 1908
Signal Tables Table 29-2. Signals by Pin Number (continued) Pin Number Pin Name Pin Type PP0 I/O TTL C2+ I Analog SSI3XDAT2 I/O TTL SSI Module 3 Bi-directional Data Pin 2. U6Rx I TTL UART module 6 receive. PP1 I/O TTL GPIO port P bit 1. 118 121 122 123 124 125 126 GPIO port P bit 0. Analog comparator 2 positive input. C2- I Analog SSI3XDAT3 I/O TTL SSI Module 3 Bi-directional Data Pin 3. U6Tx O TTL UART module 6 transmit. GPIO port B bit 5.
PAGE 1909
Tiva™ TM4C129ENCPDT Microcontroller Table 29-2. Signals by Pin Number (continued) Pin Number 127 128 29.2 Pin Name Pin Type Buffer Type Description PD6 I/O TTL AIN5 I Analog GPIO port D bit 6. SSI2XDAT3 I/O TTL SSI Module 2 Bi-directional Data Pin 3. T4CCP0 I/O TTL 16/32-Bit Timer 4 Capture/Compare/PWM 0. U2RTS O TTL UART module 2 Request to Send modem flow control output line.
PAGE 1910
Signal Tables Table 29-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment Pin Type Buffer Type Description C0- 22 PC7 I Analog Analog comparator 0 negative input. C0o 1 83 PD0 (5) PL2 (5) O TTL C1+ 24 PC5 I Analog Analog comparator 1 positive input. C1- 25 PC4 I Analog Analog comparator 1 negative input. C1o 2 84 PD1 (5) PL3 (5) O TTL C2+ 118 PP0 I Analog Analog comparator 2 positive input. Analog comparator 2 negative input.
PAGE 1911
Tiva™ TM4C129ENCPDT Microcontroller Table 29-3. Signals by Signal Name (continued) Pin Name EPI0S11 Pin Number Pin Mux / Pin Assignment 49 PG0 (15) Pin Type I/O Buffer Type Description TTL EPI module 0 signal 11. EPI0S12 75 PM3 (15) I/O TTL EPI module 0 signal 12. EPI0S13 76 PM2 (15) I/O TTL EPI module 0 signal 13. EPI0S14 77 PM1 (15) I/O TTL EPI module 0 signal 14. EPI0S15 78 PM0 (15) I/O TTL EPI module 0 signal 15. EPI0S16 81 PL0 (15) I/O TTL EPI module 0 signal 16.
PAGE 1912
Signal Tables Table 29-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment Pin Type Buffer Type Description I2C1SCL 49 PG0 (2) I/O OD I2C module 1 clock. Note that this signal has an active pull-up. The corresponding port pin should not be configured as open drain. I2C1SDA 50 PG1 (2) I/O OD I2C module 1 data. I2C2SCL 82 106 112 PL1 (2) PP5 (2) PN5 (3) I/O OD I2C module 2 clock. Note that this signal has an active pull-up.
PAGE 1913
Tiva™ TM4C129ENCPDT Microcontroller Table 29-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment Pin Type Buffer Type Description M0PWM1 43 PF1 (6) O TTL Motion Control Module 0 PWM 1. This signal is controlled by Module 0 PWM Generator 0. M0PWM2 44 PF2 (6) O TTL Motion Control Module 0 PWM 2. This signal is controlled by Module 0 PWM Generator 1. M0PWM3 45 PF3 (6) O TTL Motion Control Module 0 PWM 3. This signal is controlled by Module 0 PWM Generator 1.
PAGE 1914
Signal Tables Table 29-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment Pin Type Buffer Type Description 3 - I/O TTL GPIO port D bit 2. PD3 4 - I/O TTL GPIO port D bit 3. PD4 125 - I/O TTL GPIO port D bit 4. PD5 126 - I/O TTL GPIO port D bit 5. PD6 127 - I/O TTL GPIO port D bit 6. PD7 128 - I/O TTL GPIO port D bit 7. PD2 PE0 15 - I/O TTL GPIO port E bit 0. PE1 14 - I/O TTL GPIO port E bit 1.
PAGE 1915
Tiva™ TM4C129ENCPDT Microcontroller Table 29-3. Signals by Signal Name (continued) Pin Name PL6 Pin Number Pin Mux / Pin Assignment 94 - Pin Type I/O Buffer Type Description TTL GPIO port L bit 6. PL7 93 - I/O TTL GPIO port L bit 7. PM0 78 - I/O TTL GPIO port M bit 0. PM1 77 - I/O TTL GPIO port M bit 1. PM2 76 - I/O TTL GPIO port M bit 2. PM3 75 - I/O TTL GPIO port M bit 3. PM4 74 - I/O TTL GPIO port M bit 4. PM5 73 - I/O TTL GPIO port M bit 5.
PAGE 1916
Signal Tables Table 29-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment Pin Type Buffer Type Description SSI1Fss 121 PB4 (15) I/O TTL SSI module 1 frame signal. SSI1XDAT0 123 PE4 (15) I/O TTL SSI Module 1 Bi-directional Data Pin 0 (SSI1TX in Legacy SSI Mode). SSI1XDAT1 124 PE5 (15) I/O TTL SSI Module 1 Bi-directional Data Pin 1 (SSI1RX in Legacy SSI Mode). SSI1XDAT2 125 PD4 (15) I/O TTL SSI Module 1 Bi-directional Data Pin 2.
PAGE 1917
Tiva™ TM4C129ENCPDT Microcontroller Table 29-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment Pin Type Buffer Type Description T3CCP0 40 76 125 PA6 (3) PM2 (3) PD4 (3) I/O TTL 16/32-Bit Timer 3 Capture/Compare/PWM 0. T3CCP1 41 75 126 PA7 (3) PM3 (3) PD5 (3) I/O TTL 16/32-Bit Timer 3 Capture/Compare/PWM 1. T4CCP0 74 95 127 PM4 (3) PB0 (3) PD6 (3) I/O TTL 16/32-Bit Timer 4 Capture/Compare/PWM 0.
PAGE 1918
Signal Tables Table 29-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment Pin Type Buffer Type Description U1CTS 104 108 PP3 (1) PN1 (1) I TTL UART module 1 Clear To Send modem flow control input signal. U1DCD 13 109 PE2 (1) PN2 (1) I TTL UART module 1 Data Carrier Detect modem status input signal. U1DSR 14 110 PE1 (1) PN3 (1) I TTL UART module 1 Data Set Ready modem output control line.
PAGE 1919
Tiva™ TM4C129ENCPDT Microcontroller Table 29-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment Pin Type Buffer Type Description USB0D1 82 PL1 (14) I/O TTL USB data 1. USB0D2 83 PL2 (14) I/O TTL USB data 2. USB0D3 84 PL3 (14) I/O TTL USB data 3. USB0D4 85 PL4 (14) I/O TTL USB data 4. USB0D5 86 PL5 (14) I/O TTL USB data 5. USB0D6 106 PP5 (14) I/O TTL USB data 6. USB0D7 105 PP4 (14) I/O TTL USB data 7.
PAGE 1920
Signal Tables Table 29-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment Pin Type Buffer Type Description VDDA 8 fixed - Power The positive supply for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be supplied with a voltage that meets the specification in , regardless of system implementation.
PAGE 1921
Tiva™ TM4C129ENCPDT Microcontroller 29.3 Signals by Function, Except for GPIO Table 29-4. Signals by Function, Except for GPIO Function ADC Analog Comparators Controller Area Network Pin Name Pin Number Pin Type Buffer Type Description AIN0 12 I Analog Analog-to-digital converter input 0. AIN1 13 I Analog Analog-to-digital converter input 1. AIN2 14 I Analog Analog-to-digital converter input 2. AIN3 15 I Analog Analog-to-digital converter input 3.
PAGE 1922
Signal Tables Table 29-4. Signals by Function, Except for GPIO (continued) Function Core Ethernet Pin Name Pin Number Pin Type Buffer Type Description TRCLK 45 O TTL Trace clock. TRD0 44 O TTL Trace data 0. TRD1 43 O TTL Trace data 1. TRD2 42 O TTL Trace data 2. TRD3 46 O TTL Trace data 3. EN0LED0 42 63 O TTL Ethernet 0 LED 0. EN0LED1 46 61 O TTL Ethernet 0 LED 1. EN0LED2 43 62 O TTL Ethernet 0 LED 2.
PAGE 1923
Tiva™ TM4C129ENCPDT Microcontroller Table 29-4. Signals by Function, Except for GPIO (continued) Function External Peripheral Interface Pin Name Pin Number Pin Type Buffer Type Description EPI0S0 18 29 I/O TTL EPI module 0 signal 0. EPI0S1 19 30 I/O TTL EPI module 0 signal 1. EPI0S2 20 31 I/O TTL EPI module 0 signal 2. EPI0S3 21 32 I/O TTL EPI module 0 signal 3. EPI0S4 22 I/O TTL EPI module 0 signal 4. EPI0S5 23 I/O TTL EPI module 0 signal 5.
PAGE 1924
Signal Tables Table 29-4. Signals by Function, Except for GPIO (continued) Function General-Purpose Timers Pin Name Pin Number Pin Type Buffer Type Description T0CCP0 1 33 85 I/O TTL 16/32-Bit Timer 0 Capture/Compare/PWM 0. T0CCP1 2 34 86 I/O TTL 16/32-Bit Timer 0 Capture/Compare/PWM 1. T1CCP0 3 35 94 I/O TTL 16/32-Bit Timer 1 Capture/Compare/PWM 0. T1CCP1 4 36 93 I/O TTL 16/32-Bit Timer 1 Capture/Compare/PWM 1. T2CCP0 37 78 I/O TTL 16/32-Bit Timer 2 Capture/Compare/PWM 0.
PAGE 1925
Tiva™ TM4C129ENCPDT Microcontroller Table 29-4. Signals by Function, Except for GPIO (continued) Function Hibernate Pin Name Pin Number Pin Type Buffer Type Description HIB 65 O TTL An output that indicates the processor is in Hibernate mode. RTCCLK 24 60 104 O TTL Buffered version of the Hibernation module's 32.768-kHz clock. This signal is not output when the part is in Hibernate mode and before being configured after power-on reset. TMPR0 71 I/O TTL Tamper signal 0.
PAGE 1926
Signal Tables Table 29-4. Signals by Function, Except for GPIO (continued) Function I2C Pin Name Pin Number Pin Type Buffer Type Description I2C0SCL 91 I/O OD I2C I2C0SDA 92 I/O OD I2C module 0 data. I2C1SCL 49 I/O OD I2C module 1 clock. Note that this signal has an active pull-up. The corresponding port pin should not be configured as open drain. I2C1SDA 50 I/O OD I2C module 1 data. I2C2SCL 82 106 112 I/O OD I2C module 2 clock. Note that this signal has an active pull-up.
PAGE 1927
Tiva™ TM4C129ENCPDT Microcontroller Table 29-4. Signals by Function, Except for GPIO (continued) Function JTAG/SWD/SWO Pin Name Pin Number Pin Type Buffer Type Description SWCLK 100 I TTL JTAG/SWD CLK. SWDIO 99 I/O TTL JTAG TMS and SWDIO. SWO 97 O TTL JTAG TDO and SWO. TCK 100 I TTL JTAG/SWD CLK. TDI 98 I TTL JTAG TDI. TDO 97 O TTL JTAG TDO and SWO. TMS 99 I TTL JTAG TMS and SWDIO. M0FAULT0 46 I TTL Motion Control Module 0 PWM Fault 0.
PAGE 1928
Signal Tables Table 29-4. Signals by Function, Except for GPIO (continued) Function Pin Name Pin Number Pin Type Buffer Type GND 17 48 55 58 80 114 - Power Ground reference for logic and I/O pins. GNDA 10 - Power The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions.
PAGE 1929
Tiva™ TM4C129ENCPDT Microcontroller Table 29-4. Signals by Function, Except for GPIO (continued) Function Pin Name Pin Number Pin Type Buffer Type SSI0Clk 35 I/O TTL SSI module 0 clock SSI0Fss 36 I/O TTL SSI module 0 frame signal SSI0XDAT0 37 I/O TTL SSI Module 0 Bi-directional Data Pin 0 (SSI0TX in Legacy SSI Mode). SSI0XDAT1 38 I/O TTL SSI Module 0 Bi-directional Data Pin 1 (SSI0RX in Legacy SSI Mode). SSI0XDAT2 40 I/O TTL SSI Module 0 Bi-directional Data Pin 2.
PAGE 1930
Signal Tables Table 29-4. Signals by Function, Except for GPIO (continued) Function Pin Name Pin Number Pin Type Buffer Type Description U0CTS 30 74 121 I TTL UART module 0 Clear To Send modem flow control input signal. U0DCD 31 73 104 I TTL UART module 0 Data Carrier Detect modem status input signal. U0DSR 32 72 105 I TTL UART module 0 Data Set Ready modem output control line. U0DTR 103 O TTL UART module 0 Data Terminal Ready modem status input signal.
PAGE 1931
Tiva™ TM4C129ENCPDT Microcontroller Table 29-4. Signals by Function, Except for GPIO (continued) Function Pin Name Pin Number Pin Type Buffer Type Description UART module 4 Clear To Send modem flow control input signal. USB U4RTS 20 O TTL UART module 4 Request to Send modem flow control output line. U4Rx 18 35 I TTL UART module 4 receive. U4Tx 19 36 O TTL UART module 4 transmit. U5Rx 23 I TTL UART module 5 receive. U5Tx 22 O TTL UART module 5 transmit.
PAGE 1932
Signal Tables 29.4 GPIO Pins and Alternate Functions Table 29-5.
PAGE 1933
Tiva™ TM4C129ENCPDT Microcontroller Table 29-5.
PAGE 1934
Signal Tables Table 29-5.
PAGE 1935
Tiva™ TM4C129ENCPDT Microcontroller 29.5 Possible Pin Assignments for Alternate Functions Table 29-6.
PAGE 1936
Signal Tables Table 29-6.
PAGE 1937
Tiva™ TM4C129ENCPDT Microcontroller Table 29-6.
PAGE 1938
Signal Tables Table 29-6.
PAGE 1939
Tiva™ TM4C129ENCPDT Microcontroller Table 29-6.
PAGE 1940
Signal Tables Table 29-6.
PAGE 1941
Tiva™ TM4C129ENCPDT Microcontroller Table 29-7.
PAGE 1942
Electrical Characteristics 30 Electrical Characteristics 30.1 Maximum Ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Device reliability may be adversely affected by exposure to absolute-maximum ratings for extended periods. Note: The device is not guaranteed to operate properly at the maximum ratings. Table 30-1.
PAGE 1943
Tiva™ TM4C129ENCPDT Microcontroller 30.2 Operating Characteristics Table 30-3. Temperature Characteristics Characteristic Symbol Value Unit Ambient operating temperature range TA -40 to 85 (industrial temperature part) °C -40 to 105 (extended temperature part) Junction operating temperature range TJ -40 to 105 (industrial temperature part) °C -40 to 125 (extended temperature part) ab Table 30-4.
PAGE 1944
Electrical Characteristics 30.3 Recommended Operating Conditions The following sections describe the recommended DC operating conditions and GPIO operating characteristics for the device. 30.3.1 DC Operating Conditions Table 30-6. Recommended DC Operating Conditions Parameter Parameter Name Min Nom Max Unit VDD VDD supply voltage 2.97 3.3 3.63 V a VDDA VDDA supply voltage 2.97 3.3 3.63 V VDDC VDDC supply voltage, Run mode 1.14 1.2 1.32 V VDDC supply voltage, Deep-Sleep mode 0.
PAGE 1945
Tiva™ TM4C129ENCPDT Microcontroller Table 30-7. Recommended FAST GPIO Pad Operating Conditions (continued) Parameter Parameter Name Min Nom Max Unit 2-mA Drive 2.0 - - mA 4-mA Drive 4.0 - - mA 8-mA Drive 8.0 - - mA 10-mA Drive 10.0 - - mA 12.0 - - mA 2-mA Drive 2.0 - - mA 4-mA Drive 4.0 - - mA 8-mA Drive 8.0 - - mA 10-mA Drive 10.0 - - mA 12-mA Drive 12.0 - - mA 12-mA Drive overdriven to 18-mA 18.
PAGE 1946
Electrical Characteristics Table 30-9. GPIO Current Restrictions (continued) Parameter Parameter Name Min Nom Max Unit - - 80 mA b IMAXT Cumulative maximum GPIO current per side, top a. Based on design simulations, not tested in production. b. Sum of sink and source current for GPIOs as shown in Table 30-10 on page 1946. Table 30-10.
PAGE 1947
Tiva™ TM4C129ENCPDT Microcontroller 30.4 Load Conditions Table 30-11 on page 1947 contains the load conditions used for timing measurements. Figure 30-1. Load Conditions pin CL GND Table 30-11.
PAGE 1948
Electrical Characteristics 30.5 JTAG and Boundary Scan Table 30-12. JTAG Characteristics Parameter Parameter Parameter Name No.
PAGE 1949
Tiva™ TM4C129ENCPDT Microcontroller Figure 30-2. JTAG Test Clock Input Timing J2 J3 J4 TCK J6 J5 Figure 30-3.
PAGE 1950
Electrical Characteristics 30.6 Power and Brown-Out Table 30-13. Power and Brown-Out Levels Parameter No. Parameter Parameter Name Min Nom Max Unit P1 TVDDA_RISE Analog Supply voltage (VDDA) rise time - - ∞ µs P2 TVDD_RISE P3 a TVDDC_RISE I/O Supply voltage (VDD) rise time - - ∞ µs Core Supply Voltage (VDDC) rise time 10 - 150 µs Power-On Reset Threshold (Rising Edge) 1.98 2.35 2.72 V Power-On Reset Threshold (Falling Edge) 1.84 2.20 2.
PAGE 1951
Tiva™ TM4C129ENCPDT Microcontroller ■ BOR bit in the Reset Cause (RESC) register, System Control offset 0x05C. This bit is set only if either of the BOR events have been configured to initiate a reset. See page 274. In addition, the following bits control both BOR events: ■ BORIM bit in the Interrupt Mask Control (IMC) register, System Control offset 0x054. ■ VDDA_UBOR0 and VDD_UBOR0 bits in the Power-Temperature Cause (PWRTC) register.
PAGE 1952
Electrical Characteristics in operational ranges. The BOR monitor is used to generate a reset to the device or assert an interrupt if the VDD supply drops below its operational range. Note: VDDA BOR and VDD BOR events are a combined BOR to the system logic, such that if either BOR event occurs, the following bits are affected: ■ BORRIS bit in the Raw Interrupt Status (RIS) register, System Control offset 0x050. See page 268.
PAGE 1953
Tiva™ TM4C129ENCPDT Microcontroller Figure 30-6. POK Assertion vs VDDC POK VDDC P3 1.2V P9RISE P9FALL 1 0 30.6.4 Response 30.6.4.1 VDD Glitch Response Figure 30-7 on page 1953 shows the response of the BOR and the POR circuit to glitches on the VDD supply. Figure 30-7. POR-BOR VDD Glitch Response 30.6.4.2 VDD Droop Response Figure 30-8 on page 1954 shows the response of the BOR and the POR monitors to a drop on the VDD supply.
PAGE 1954
Electrical Characteristics Figure 30-8.
PAGE 1955
Tiva™ TM4C129ENCPDT Microcontroller 30.7 Reset a Table 30-14. Reset Characteristics Parameter No. Parameter R1 TDPORDLY R2 TIRTOUT R3 TBOR0DLY 0.44 - R4 TRSTMIN Minimum RST pulse width - 0.25 /100 R5 TIRHWDLY RST to Internal Reset assertion delay - R6 b TIRSWR Internal reset timeout after software-initiated system reset - R7 TIRWDR Internal reset timeout after Watchdog reset - 2.44 - µs R8 b TIRMFR Internal reset timeout after MOSC failure reset - 2.
PAGE 1956
Electrical Characteristics Figure 30-10. Brown-Out Reset Timing BOR R3 R2 Reset (Internal) Figure 30-11. External Reset Timing (RST) R4 RST (Package Pin) R5 R2 Reset (Internal) Figure 30-12. Software Reset Timing Software Reset R6 Reset (Internal) Figure 30-13.
PAGE 1957
Tiva™ TM4C129ENCPDT Microcontroller Figure 30-14.
PAGE 1958
Electrical Characteristics 30.8 On-Chip Low Drop-Out (LDO) Regulator Table 30-15. LDO Regulator Characteristics Parameter Parameter Name Min Nom Max Unit CLDO External filter capacitor size for internal power a supply 2.5 - 4.0 µF ESR Filter capacitor equivalent series resistance 0 - 100 mΩ ESL Filter capacitor equivalent series inductance VLDO LDO output voltage, Run mode IINRUSH Inrush current - - 0.5 nH 1.13 1.2 1.27 V 50 - 250 mA a.
PAGE 1959
Tiva™ TM4C129ENCPDT Microcontroller 30.9 Clocks The following sections provide specifications on the various clock sources and mode. 30.9.1 PLL Specifications The following tables provide specifications for using the PLL. Note: If the integrated Ethernet PHY is used in this device, then FREF_XTAL and FREF_EXT are required to be 25 MHz. Table 30-16.
PAGE 1960
Electrical Characteristics When the PLL is active, the system clock frequency (SysClk) is calculated using the following equation: SysClk = fVCO/ (PSYSDIV + 1) The PLL system divisor factor (PSYSDIV) determines the value of the system clock. Table 5-6 on page 244 shows how the system divisor encodings affect the system clock frequency when the fVCO = 480 MHz. Table 30-17.
PAGE 1961
Tiva™ TM4C129ENCPDT Microcontroller Table 30-18. Actual PLL Frequency (continued) Crystal Frequency (MHz) MINT (Decimal Value) MINT (Hexadecimal Value) N Reference Frequency b (MHz) PLL Frequency (MHz) 10 48 0x30 0x0 10 480 12 40 0x28 0x0 12 480 16 30 0x1E 0x0 16 480 18 80 0x50 0x2 6 480 20 24 0x18 0x0 20 480 24 20 0x14 0x0 24 480 25 96 0x60 0x4 5 480 a. For all examples listed, Q=0 b.
PAGE 1962
Electrical Characteristics Table 30-22. Hibernation External Oscillator (XOSC) Input Characteristics (continued) Parameter CPCB CSHUNT Parameter Name b PCB stray shunt capacitance DL TSTART f VIH f VIL f VHYS Nom Max Unit - 0.5 - pF - - 4 pF c - - 50 kΩ c Crystal effective series resistance, OSCDRV = 1 - - 75 kΩ Oscillator output drive level - - 0.25 µW - 600 1500 ms CMOS input high level, when using an external oscillator with Supply > 3.3 V 2.
PAGE 1963
Tiva™ TM4C129ENCPDT Microcontroller Table 30-23. Main Oscillator Input Characteristics (continued) Parameter CPCB CSHUNT Parameter Name Min Nom Max Unit - 0.
PAGE 1964
Electrical Characteristics on a network analyzer. The parameters labeled ESR, DL and CL are maximum numbers usually available in the data sheet for a crystal. The table also includes three columns of Recommended Component Values. These values apply to system board components. C1 and C2 are the values in pico Farads of the load capacitors that should be put on each leg of the crystal pins to ensure oscillation at the correct frequency.
PAGE 1965
Tiva™ TM4C129ENCPDT Microcontroller Table 30-24. Crystal Parameters (continued) Abracon AABMM- 4-SMD ABMM 7.2 x 5.2 30/30 ppm 1.16 4.16 42.30 80 500 10 14 14 WC Dl (μW) Rs (kΩ) C2 (pF) Recommended Component Values C1 (pF) CL (pf) Max Dl (µW) Max Values ESR (Ω) L1 (mH) C1 (fF) Typical Values C0 (pF) 12 Crystal Spec (Tolerance / Stability) 5 x 3.2 PKG Size Freq (MHz) FQ5032B-12 (mm x mm) FOX Holder MFG MFG Part# Crystal Parameters 0 370 a 143 a 16 10/20 ppm 3.00 11.
PAGE 1966
Electrical Characteristics 30.9.6 System Clock Specification with ADC Operation Table 30-25. System Clock Characteristics with ADC Operation Parameter Fsysadc 30.9.7 Parameter Name Min Nom Max Unit - 16 - MHz System clock frequency when the ADC module is operating (when PLL is bypassed). System Clock Specification with USB Operation Table 30-26.
PAGE 1967
Tiva™ TM4C129ENCPDT Microcontroller 30.10 Sleep Modes The following tables can be used to calculate the maximum wake time from Sleep or Deep Sleep depending on the specific application. Depending on the application configuration, each of the parameters, except for TFLASH, add sequential latency to the wake time. Flash restoration happens in parallel to the other wake processes and its wake time is normally absorbed by the other latencies.
PAGE 1968
Electrical Characteristics Table 30-28. Wake from Deep Sleep Characteristics (continued) Parameter No Parameter Parameter Name D14 TSRAMSTBYDS Time to restore SRAM to active state from standby state Min Nom - - Max Unit 15 µs a. Deep Sleep Clock can vary. See page 288 for the Deep Sleep Clock options.
PAGE 1969
Tiva™ TM4C129ENCPDT Microcontroller 30.11 Hibernation Module The Hibernation module requires special system implementation considerations because it is intended to power down all other sections of its host device, refer to “Hibernation Module” on page 539. Table 30-29. Hibernation Module Battery Characteristics Parameter VBAT b VBATRMP Parameter Name Min Nominal Max Battery supply voltage 1.8 3.0 3.6 V 0 - 0.7 V/µs Low battery detect voltage, VBATSEL=0x0 1.8 1.9 2.
PAGE 1970
Electrical Characteristics Figure 30-15.
PAGE 1971
Tiva™ TM4C129ENCPDT Microcontroller 30.12 Flash Memory Table 30-32.
PAGE 1972
Electrical Characteristics 30.13 EEPROM a Table 30-33.
PAGE 1973
Tiva™ TM4C129ENCPDT Microcontroller 30.14 Input/Output Pin Characteristics Note: All GPIO signals are 3.3-V tolerant, except for PB1 (USB0VBUS) which is 5-V tolerant. See “Signal Description” on page 751 for more information on GPIO configuration. Two types of pads are provided on the device: ■ Fast GPIO pads: These pads provide variable, programmable drive strength and optimized voltage output levels.
PAGE 1974
Electrical Characteristics Table 30-34. Fast GPIO Module Characteristics (continued) Parameter Parameter Name Nom Max Unit i Min Fast GPIO fall time, 2-mA drive 10.3 16.5 ns i 5.15 8.29 ns 2.58 4.16 ns Fast GPIO fall time, 4-mA drive i TGPIOF Fast GPIO fall time, 8-mA drive Fast GPIO fall time, 8-mA drive with slew rate control i - 3.54 5.55 ns Fast GPIO fall time, 10-mA drive i 2.07 3.34 ns i 1.73 2.78 ns Fast GPIO fall time, 12-mA drive a.
PAGE 1975
Tiva™ TM4C129ENCPDT Microcontroller 30.14.1 Types of I/O Pins and ESD Protection Caution – All device I/Os pins, except for PB1, are NOT 5V tolerant; voltages in excess of the limits shown in Table 30-6 on page 1944 can permanently damage the device. PB1 is used for the USB's USB0VBUS signal, which requires a 5-V input. 30.14.1.1 Hibernate WAKE pin The Hibernate WAKE pin uses ESD protection, similar to the one shown in Figure 30-16 on page 1975.
PAGE 1976
Electrical Characteristics Figure 30-17. ESD Protection for Non-Power Pins (Except WAKE Signal) Table 30-37. Non-Power I/O Pad Voltage/Current Characteristics Parameter d VIO Parameter Name IO pad voltage limits if voltage protected Min Nom Max Unit -0.3 VDD VDD+0.3 V e - - 400 nA e - - 60 µA - - 2 mA - - -0.
PAGE 1977
Tiva™ TM4C129ENCPDT Microcontroller 30.15 External Peripheral Interface (EPI) Table 30-38. EPI Interface Load Conditions Signals Load Value (CL) EPI0S[35:0] SDRAM interface EPI0S[35:0] General-Purpose interface 30 pF EPI0S[35:0] Host-Bus interface EPI0S[35:0] PSRAM interface 40 pF When the EPI module is in SDRAM mode, EPI CLK must be configured to 12 mA. The EPI data bus can be configured to 8 mA. Table 30-39 on page 1977 shows the rise and fall times in SDRAM mode.
PAGE 1978
Electrical Characteristics Figure 30-18. SDRAM Initialization and Load Mode Register Timing CLK (EPI0S31) E1 CKE (EPI0S30) E2 E3 NOP Command (EPI0S[29:28,19:18]) NOP NOP NOP AREF PRE NOP NOP PRE LOAD AREF NOP AREF Active DQMH, DQML (EPI0S[17:16]) AD11, AD[9:0] (EPI0S[11,9:0] Code Row All Banks AD10 (EPI0S[10]) Code Row Single Bank BAD[1:0] (EPI0S[14:13]) Bank AD [15,12] (EPI0S [15,12]) E9 E10 E11 E12 Notes: 1. If CS is high at clock high time, all applied commands are NOP.
PAGE 1979
Tiva™ TM4C129ENCPDT Microcontroller Figure 30-20. SDRAM Write Timing CLK (EPI0S31) CKE (EPI0S30) E4 E5 E6 CSn (EPI0S29) WEn (EPI0S28) RASn (EPI0S19) CASn (EPI0S18) DQMH, DQML (EPI0S [17:16]) AD [15:0] (EPI0S [15:0]) Row Column-1 Activate NOP Data 0 Data 1 ... Data n Burst Term Write AD [15:0] driven out AD [15:0] driven out Table 30-41.
PAGE 1980
Electrical Characteristics Figure 30-21. Host-Bus 8/16 Asynchronous Mode Read Timing E21 ALE (EPI0S30) CSn (EPI0S30) E18 E22 WRn (EPI0S29) E19 E23 E20 RDn/OEn (EPI0S28) BSEL0n/ BSEL1na Address E15 E14 Data a Data BSEL0n and BSEL1n are available in Host-Bus 16 mode only. Figure 30-22.
PAGE 1981
Tiva™ TM4C129ENCPDT Microcontroller Figure 30-23. Host-Bus 8/16 Mode Asynchronous Muxed Read Timing E21 ALE (EPI0S30) E18 CSn (EPI0S30) E22 WRn (EPI0S29) E19 E18 E23 E20 RDn/OEn (EPI0S28) E24 BSEL0n/ BSEL1na a E15 E14 Muxed Address/Data Address Data BSEL0n and BSEL1n are available in Host-Bus 16 mode only. Figure 30-24.
PAGE 1982
Electrical Characteristics Figure 30-25. General-Purpose Mode Read and Write Timing E26 E25 E27 Clock (EPI0S31) E30 Frame (EPI0S30) RD (EPI0S29) WR (EPI0S28) Address E30 E28 Data Data E31 Data E29 Read Note: Write This figure illustrates accesses where the FRM50 bit is clear, the FRMCNT field is 0x0 and the WR2CYC bit is clear. Table 30-43.
PAGE 1983
Tiva™ TM4C129ENCPDT Microcontroller Figure 30-26.
PAGE 1984
Electrical Characteristics Figure 30-27.
PAGE 1985
Tiva™ TM4C129ENCPDT Microcontroller 30.16 Analog-to-Digital Converter (ADC) ab Table 30-44. ADC Electrical Characteristics for ADC at 1 Msps Parameter Parameter Name Min Nom Max Unit POWER SUPPLY REQUIREMENTS VDDA ADC supply voltage 2.97 3.3 3.63 V GNDA ADC ground voltage - 0 - V - 1.0 // 0.
PAGE 1986
Electrical Characteristics Table 30-44. ADC Electrical Characteristics for ADC at 1 Msps (continued) Parameter ET Parameter Name p Total unadjusted error, over full input range Min Nom Max Unit - ±2.5 ±4.0 LSB LSB SYSTEM PERFORMANCE when using internal reference N Resolution 12 bits INL Integral nonlinearity error, over full input range - ±1.5 ±3.0 DNL Differential nonlinearity error, over full input range - ±0.8 +2.0/-1.0 LSB EO Offset error - ±5.0 ±15.
PAGE 1987
Tiva™ TM4C129ENCPDT Microcontroller g. With signal common mode as (VREF+ + GNDA). h. This parameter is defined as the average of the differential inputs. i. As shown in Figure 30-29 on page 1990, RADC is the total equivalent resistance in the input line all the way up to the sampling node at the input of the ADC. j. See “System Clock Specification with ADC Operation” on page 1966 for full ADC clock frequency specification. k. ADC conversion time (Tc) includes the ADC sample time (Ts). l.
PAGE 1988
Electrical Characteristics Table 30-45. ADC Electrical Characteristics for ADC at 2 Msps (continued) Parameter Parameter Name Min Nom Max Unit 0 - VDDA V Differential, full-scale analog input voltage, eg internal reference -VDDA - VVDDA V Single-ended, full-scale analog input voltage, df external reference VREFA- - VREFA+ V - (VREFA+ VREFA-) - VREFA+ - VREFA- V - - [(VREFA+ + VREFA-) / 2] ± 0.025 V - - 2.0 µA - - 2.
PAGE 1989
Tiva™ TM4C129ENCPDT Microcontroller Table 30-45. ADC Electrical Characteristics for ADC at 2 Msps (continued) Parameter Min Nom Max Unit Signal-to-noise-ratio, Single-ended input, VADCIN: -20dB FS, 1KHz 58 65 - dB SDRS Signal-to-distortion ratio, Single-ended input, uv VADCIN: -3dB FS, 1KHz 68 72 - dB SNDRS Signal-to-Noise+Distortion ratio, Single-ended ywx input, VADCIN: -3dB FS, 1KHz 58 63 - dB SNRS Parameter Name y a. Values are at VREF+= 3.
PAGE 1990
Electrical Characteristics Figure 30-28. ADC External Reference Filtering Tiva™ Microcontroller IVREF VREF+ VREF+ CREF GNDA VREF GNDA Figure 30-29.
PAGE 1991
Tiva™ TM4C129ENCPDT Microcontroller 30.17 Synchronous Serial Interface (SSI) Table 30-46. SSI Characteristics Parameter No. Parameter Parameter Name S1 TCLK_PER S2 TCLK_HIGH S3 TCLK_LOW S4 TCLKR SSIClk rise time S5 TCLKF c S6 TTXDMOV S7 a SSIClk cycle time, as master Min Nom Max Unit 16.67 - - ns b SSIClk cycle time, as slave 100 - - ns SSIClk high time, as master 8.33 - - ns SSIClk high time, as slave 50 - - ns SSIClk low time, as master 8.
PAGE 1992
Electrical Characteristics Figure 30-30. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement S1 S2 S4 S5 SSIClk S3 SSIFss SSITx SSIRx MSB LSB 4 to 16 bits Figure 30-31.
PAGE 1993
Tiva™ TM4C129ENCPDT Microcontroller Figure 30-32. Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 S1 S5 S2 S4 SSIClk (SPO=1) S3 S3 SSIClk (SPO=0) S10 SSITx S11 MSB (to master) LSB S12 S13 SSIRx MSB ( from master) LSB SSIFss a Table 30-47. Bi- and Quad-SSI Characteristics Parameter No. Parameter Parameter Name b Min Nom Max Unit S15 TCLK_PER SSIClk cycle time, as master 16.67 - - ns S16 TCLK_HIGH SSIClk high time, as master 8.
PAGE 1994
Electrical Characteristics 30.18 Inter-Integrated Circuit (I2C) Interface Table 30-48. I2C Characteristics Parameter No. Parameter Parameter Name Min Nom Max Unit a TSCH Start condition hold time 36 - - system clocks a TLP Clock Low period 36 - - system clocks b I3 TSRT I2CSCL/I2CSDA rise time (VIL =0.5 V to V IH =2.
PAGE 1995
Tiva™ TM4C129ENCPDT Microcontroller 30.19 Ethernet Controller 30.19.1 DC Characteristics The parameters listed in Table 30-49 on page 1995, with the exception of RBIAS, apply to transmit pins of the Ethernet PHY, which are generally the EN0TXOP and EN0TX0N signals during standard operation but can also be the EN0RXIN EN0RXIP signals if Auto-MDIX is enabled. Table 30-49. Ethernet PHY DC Characteristics 30.19.
PAGE 1996
Electrical Characteristics a Table 30-51. MOSC Single-Ended 25-MHz Oscillator Specification (continued) Parameter No. Parameter - TJ - DC Parameter Name Min Nom Max Unit - 50 - ps - - 1 ns 40 - 60 % Jitter (cycle-to-cycle) Jitter (over 10 ms) Duty cycle Figure 30-35. Single-Ended MOSC Characteristics for Ethernet N4 N5 N5 OSC0 30.19.3 AC Characteristics Table 30-52. Ethernet Controller Enable and Software Reset Timing Parameter No.
PAGE 1997
Tiva™ TM4C129ENCPDT Microcontroller Table 30-53. 100Base-TX Transmit Timing (tR/F and Jitter) (continued) Parameter No. Parameter N39 TRF_JTTR Parameter Name Min Nom Max Unit - - 1.4 ns 100 Mb/s PMD Output Pair Transmit Jitter a. Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude. b. Normal mismatch is the difference between the maximum and minimum of all rise and fall times c. Choice of Ethernet transformer magnetics can affect this parameter. Figure 30-37.
PAGE 1998
Electrical Characteristics Table 30-55. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameter No. Parameter Parameter Name Min Nom Max Unit N72 TCLKP Clock pulse to clock pulse period - 125 - µs N73 TCLKDP Clock Pulse to Data Pulse Period - 62 - µs N74 TPUL Clock, Data Pulse Width - 110 - ns N75 TBRSTP FLP Burst to FLP Burst Period - 16 - ms N76 TBRSTW Burst Width - 2 - ms Figure 30-39.
PAGE 1999
Tiva™ TM4C129ENCPDT Microcontroller 30.20 Universal Serial Bus (USB) Controller The Tiva™ C Series USB controller electrical specifications are compliant with the Universal Serial Bus Specification Rev. 2.0 (full-speed and low-speed support) and the On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0. Some components of the USB system are integrated within the TM4C129ENCPDT microcontroller and specific to the Tiva™ C Series microcontroller design.
PAGE 2000
Electrical Characteristics Figure 30-41.
PAGE 2001
Tiva™ TM4C129ENCPDT Microcontroller 30.21 Analog Comparator ab Table 30-58. Analog Comparator Characteristics Parameter Parameter Name c VINP,VINN VCM VOS IINP,IINN CMRR Min Nom Max Unit Input voltage range GNDA - VDDA V Input common mode voltage range GNDA - VDDA V d Input offset voltage - ±10 ±50 mV Input leakage current over full voltage range - - 2.0 µA Common mode rejection ratio - 50 - dB e TRT Response time - - 1.
PAGE 2002
Electrical Characteristics Table 30-60. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and RNG = 0 (continued) VREF Value VIREF Min Ideal VIREF VIREF Max Unit 0xD 2.190 2.245 2.300 V 0xE 2.302 2.357 2.412 V 0xF 2.414 2.469 2.525 V Table 30-61. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and RNG = 1 VREF Value VIREF Min Ideal VIREF VIREF Max Unit 0x0 0.000 0.000 0.074 V 0x1 0.076 0.149 0.223 V 0x2 0.225 0.298 0.
PAGE 2003
Tiva™ TM4C129ENCPDT Microcontroller 30.22 Pulse-Width Modulator (PWM) Table 30-62. PWM Timing Characteristics Parameter TFLTW Parameter Name Minimum Fault Pulse Width a TFLTMAX MnFAULTn Assertion to PWM Inactive TFLTMIN MnFAULTn De-Assertion to PWM Active b Min Nom Max Unit 2 - - PWM clock periods - - 24 + (1 PWM clock) ns 5 - - ns a.
PAGE 2004
Electrical Characteristics 30.23 Current Consumption Table 30-64 on page 2008 shows the amount of current consumption that specific peripherals contribute to the Run mode current consumption numbers shown in Table 30-63 on page 2004. If these peripherals are not powered, then the peripheral current consumption values can be subtracted from the Run mode numbers displayed in Table 30-63 on page 2004. ab Table 30-63. Current Consumption System Clock Parameter Nom Max 85°C 105°C c Unit 96.4 105.3 107.
PAGE 2005
Tiva™ TM4C129ENCPDT Microcontroller Table 30-63. Current Consumption (continued) System Clock Parameter Parameter Name Conditions Clock Source 60 MHz MOSC with PLL 16 MHz 1 MHz -40°C 25°C 85°C 105°C c 85°C 105°C Unit 48.2 49.8 50.9 67.6 78.6 mA PIOSC 11.7 17.9 19.2 20.2 36.6 47.2 mA PIOSC 5.05 9.75 11.0 11.9 28.6 39.4 mA 120 MHz MOSC with PLL 35.4 43.3 44.7 45.8 59.8 69.0 mA 60 MHz MOSC with PLL 23.4 29.4 30.7 31.7 45.5 54.
PAGE 2006
Electrical Characteristics Table 30-63. Current Consumption (continued) System Clock Parameter Parameter Name Conditions Peripherals = All ON including MAC but not PHY Nom Frequency Clock Source 16 MHz PIOSC 1 MHz -40°C 25°C Max c 85°C 105°C c 85°C 105°C Unit d 9.75 10.4 11.8 12.9 28.9 39.6 mA PIOSC d 3.82 3.82 5.25 6.38 22.5 33.4 mA 120 MHz MOSC with PLL 58.1 59.9 61.4 62.5 79.1 89.7 mA 60 MHz MOSC with PLL 34.2 35.1 36.7 37.6 53.6 64.
PAGE 2007
Tiva™ TM4C129ENCPDT Microcontroller Table 30-63. Current Consumption (continued) System Clock Parameter Parameter Name Conditions Frequency Clock Source Nom -40°C 25°C Max c 85°C 105°C c 85°C 105°C Unit VDD = 3.3 V 16 MHz PIOSC 2.45 2.48 2.50 2.48 2.84 2.90 mA VDDA = 3.3 V 30 kHz LFIOSC 2.45 2.48 2.50 2.48 2.85 2.90 mA Peripherals = All ON LDO = 1.2 V VDD = 3.3 V 16 MHz PIOSC 0.226 0.227 0.265 0.249 0.558 0.635 mA VDDA = 3.3 V 30 kHz LFIOSC 0.228 0.227 0.272 0.247 0.
PAGE 2008
Electrical Characteristics d. Note that if the MOSC is the source of the Run-mode system clock and is powered down in Sleep mode, wake time is increased by TMOSC_SETTLE. e. To achieve the lowest possible Deep-Sleep current, one or more wait states must be configured in the MEMTIM0 register. If there are no wait states applied in Run mode, then lowest possible Deep-Sleep current is not achieved. f. See the section called “LDO Power Control” on page 251 for information on lowering the LDO voltage to 0.9 V.
PAGE 2009
Tiva™ TM4C129ENCPDT Microcontroller A Package Information A.1 Orderable Devices The figure below defines the full set of orderable part numbers for the TM4C129x Series. See the Package Option Addendum for the complete list of valid orderable part numbers for the TM4C129ENCPDT microcontroller. Figure A-1.
PAGE 2010
Package Information $$ TM4C129X NCZADI3 YMLLLLS G1 This identifying number contains the following information: ■ Lines 1 and 5: Internal tracking numbers ■ Lines 2 and 3: Part number For example, TM4C129X on the second line followed by NCZADI3 on the third line indicates orderable part number TM4C129XNCZADI3. Note that the first letter in the part number indicates the product status.
PAGE 2011
Tiva™ TM4C129ENCPDT Microcontroller A.4 Packaging Diagram Figure A-2. TM4C129ENCPDT 128-Pin TQFP Package Diagram MECHANICAL DATA MPQF013 – NOVEMBER 1995 PDT (S-PQFP-G128) PLASTIC QUAD FLATPACK 0,23 0,13 0,40 96 0,05 M 65 97 64 128 33 1 0,13 NOM 32 12,40 TYP Gage Plane 14,05 SQ 13,95 16,10 SQ 15,90 0,25 0,05 MIN 0°– 5° 0,75 0,45 1,05 0,95 Seating Plane 0,08 1,20 MAX 4087726/A 11/95 NOTES: A. All linear dimensions are in millimeters. B.
PAGE 2012
PACKAGE OPTION ADDENDUM www.ti.
PAGE 2013
PACKAGE OPTION ADDENDUM www.ti.com 3-Dec-2014 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 2014
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
PAGE 2015
TM4C Series TM4C129E Crypto Connected LaunchPad Evaluation Kit EK-TM4C129EXL User's Guide Literature Number: SPMU372A September 2015 – Revised October 2016
PAGE 2016
Contents 1 Board Overview ................................................................................................................... 5 1.1 1.2 1.3 1.4 1.5 1.6 2 2.2 2.3 3.2 3.3 Secure IoT Demo........................................................................................................... 3.1.1 Software Description .............................................................................................. 3.1.2 Source Code Download and Build Instructions ........................
PAGE 2017
www.ti.com Revision History ..........................................................................................................................
PAGE 2018
www.ti.com List of Figures 1-1. TM4C Series Crypto Connected LaunchPad Evaluation Board ....................................................... 5 2-1. TM4C Crypto Connected LaunchPad Evaluation Board Block Diagram ............................................. 9 2-2. Default Jumper Locations ................................................................................................. 20 A-1. Crypto Connected LaunchPad Dimensions and Component Locations ............................................
PAGE 2019
Chapter 1 SPMU372A – September 2015 – Revised October 2016 Board Overview The TM4C Series TM4C129E Crypto Connected LaunchPad™ Evaluation Board (EK-TM4C129EXL) is a low-cost evaluation platform for ARM® Cortex®-M4F-based microcontrollers. The Crypto Connected LaunchPad design highlights the TM4C129ENCPDT microcontroller with its on-chip crypto acceleration hardware, 10/100 Ethernet MAC and PHY, USB 2.
PAGE 2020
Kit Contents 1.1 www.ti.com Kit Contents The Crypto Connected LaunchPad Evaluation Kit contains the following items: • TM4C Series TM4C129E Evaluation Board (EK-TM4C129EXL) • Retractable Ethernet cable • USB Micro-B plug to USB-A plug cable • 90° 49x2 breadboard header • Meet the TM4C Series TM4C129E Crypto LaunchPad Evaluation Kit (SPMZ862) 1.2 Using the Crypto Connected LaunchPad The recommended steps for using the Crypto Connected LaunchPad Evaluation Kit are: 1.
PAGE 2021
BoosterPacks www.ti.com • • • • 1.4 Jumper for selecting power source: – ICDI USB – USB Device – BoosterPack Preloaded secure access of Internet-of-Things product to Exosite application I/O brought to board edge for breadboard expansion Two independent BoosterPack XL standard connectors featuring stackable headers to maximize expansion through BoosterPack ecosystem – For a complete list of BoosterPacks, see the TI MCU LaunchPad web page: http://www.ti.
PAGE 2022
Specifications 8 Board Overview www.ti.
PAGE 2023
Chapter 2 SPMU372A – September 2015 – Revised October 2016 Hardware Description The Crypto Connected LaunchPad includes a TM4C129ENCPDT microcontroller with an integrated 10/100 Ethernet MAC and PHY and crypto acceleration blocks. This advanced ARM Cortex M4F MCU has a wide range of peripherals that are made available to users via the on-board accessories and the BoosterPack connectors. This chapter explains how those peripherals operate and interface to the microcontroller.
PAGE 2024
Functional Description www.ti.com 2.1.2 Ethernet Connectivity The Crypto Connected LaunchPad is designed to connect directly to an Ethernet network using RJ45 style connectors. The microcontroller contains a fully integrated Ethernet MAC and PHY. This integration creates a simple, elegant and cost-saving Ethernet circuit design. Example code is available for both the uIP and LwIP TCP/IP protocol stacks. The embedded Ethernet on this device can be programmed to act as an HTTP server, client or both.
PAGE 2025
Functional Description www.ti.com 2.1.6 User Switches and LED's Two user switches are provided for input and control of the TM4C129ENCPDT software. The switches are connected to GPIO pins PJ0 and PJ1. A reset switch and a wake switch are also provided. The reset switch initiates a system reset of the microcontroller whenever it is pressed and released. Pressing the reset switch also asserts the reset signal to the BoosterPack and Breadboard headers.
PAGE 2026
Functional Description www.ti.com 2.1.7 BoosterPacks and Headers 2.1.7.1 BoosterPack 1 The Crypto Connected LaunchPad features two fully independent BoosterPack XL connectors. BoosterPack 1, located around the ICDI portion of the board, is fully compliant with the BoosterPack standard with the single exception of GPIO pin PA6 (X8-16), which does not provide analog capability. PA6 is located near the bottom of the inner left BoosterPack XL header.
PAGE 2027
Functional Description www.ti.com Table 2-1.
PAGE 2028
Functional Description 2.1.7.2 www.ti.com BoosterPack 2 The second BoosterPack XL interface is located near the middle of the board. This interface is fully compliant with the BoosterPack standard and adds features not covered by the BoosterPack standard that enable operation with additional BoosterPacks. An additional analog signal is provided on the outer left header (X6-9). This signal can be used to monitor the touch panel on the popular Kentec EB-LM4F120-L35 BoosterPack.
PAGE 2029
Functional Description www.ti.com Table 2-2.
PAGE 2030
Functional Description 2.1.7.3 www.ti.com Breadboard Connection The breadboard adapter section of the board is a set of 98 holes on a 0.1 inch grid. Properly combined with a pair of right angle headers, the entire Crypto Connected LaunchPad can be plugged directly into a standard 300 mil (0.3 inch) wide solder-less breadboard. The right angle headers and breadboard are not provided with this kit.
PAGE 2031
Functional Description www.ti.com Table 2-3.
PAGE 2032
Functional Description www.ti.com Table 2-4.
PAGE 2033
Functional Description www.ti.com Table 2-4.
PAGE 2034
Power Management 2.1.7.4 www.ti.com Other Headers and Jumpers JP1 is provided to select the power input source for the Crypto Connected LaunchPad. The top position is for BoosterPack power; this position also disconnects both USB voltages from the board’s primary 5-V input. In the top position, the TPS2052B does not limit current so additional care should be exercised. The middle position draws power from the USB connector on the left side of the board near the Ethernet jack.
PAGE 2035
Power Management www.ti.com 2.2.2 Low Power Modes The Crypto Connected LaunchPad demonstrates several low power microcontroller modes. In run mode, the microcontroller can be clocked from several sources such as the internal precision oscillator or an external crystal oscillator. Either of these sources can then optionally drive an internal PLL to increase the effective frequency of the system up to 120 MHz. In this way, the run mode clock speed can be used to manage run mode current consumption.
PAGE 2036
Debug Interface www.ti.com 2.3.2 External Debugger The connector U6 is provided for the attachment of an external debug adapter such as the IAR J-Link or Keil ULINK. This connector follows the ARM standard 10-pin JTAG pinout. This interface can use either JTAG or SWD if supported by the external debug adapter. 2.3.3 Virtual COM Port When plugged into a USB host, the ICDI enumerates as both a debugger and a virtual COM port.
PAGE 2037
Chapter 3 SPMU372A – September 2015 – Revised October 2016 Software Development This chapter provides general information on software development as well as instructions for flash memory programming. 3.1 Secure IoT Demo 3.1.1 Software Description The out-of-box “Secure IoT” application demonstrates the use of Transport Layer Security/Secure Sockets Layer (TLS/SSL) protocol to connect an IoT product to a cloud server securely. This application runs on TI-RTOS and uses WolfSSL library for TLS/SSL support.
PAGE 2038
TivaWare for C Series Software www.ti.com 3.2.2 Source Code The complete source code including the source code installation instructions are provided at http://www.ti.com/tool/sw-tm4c. The source code and binary files are installed in the TivaWare software tree. 3.2.
PAGE 2039
Chapter 4 SPMU372A – September 2015 – Revised October 2016 References 4.1 References In • • • • • • • • • • addition to this document the following references are available for download at www.ti.com. TivaWare for C Series (http://www.ti.com/tool/sw-tm4c) TivaWare Peripheral Driver Library Users' Guide (SPMU298) Quick Start Guide: Crypto Connected LaunchPad Evaluation Kit (EK-TM4C129EXL) (SPMZ862) LM Flash Programmer Tool (http://www.ti.
PAGE 2040
Appendix A SPMU372A – September 2015 – Revised October 2016 PCB Layout and Bill of Materials A.1 Component Locations Figure A-1 is a dimensioned drawing of the Crypto Connected LaunchPad that shows the location of selected features of the board, as well as the component locations. Figure A-1.
PAGE 2041
Bill of Materials www.ti.com A.2 Bill of Materials Table A-1 is the Crypto Connected LaunchPad bill of materials list. Table A-1. Crypto Connected LaunchPad Bill of Materials Item Ref Qty Description Mfg Part Number Kemet C1210C102MGRACTU 1 C1 1 Capacitor, 1000 pF, 2kV, 20%, X7R, 1210 2 C3, C4, C5, C10, C11, C12, C13, C16, C17, C18, C19, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C40, C41, C42, C43, C46 26 Capacitor, 0.
PAGE 2042
Bill of Materials www.ti.com Table A-1. Crypto Connected LaunchPad Bill of Materials (continued) Item Ref Qty Description Mfg Part Number Rohm MCR01MRTF1004 22 R42 1 Resistor, 1M Ω, 1/10W, 5%, 0402 23 R47 1 RES 1M Ω 5% 1206 TF Panasonic ERJ-8GEYJ105V Panasonic ERJ-3GEYJ202V 24 R49, R50 2 Resistor, 2.
PAGE 2043
Bill of Materials www.ti.com Table A-1. Crypto Connected LaunchPad Bill of Materials (continued) Item Ref Qty Description Mfg Part Number PCB Do Not Populate List (Shown for information only) 43 C2 1 Capacitor, 0.1 µF 16 V, 10%, 0402 X7R Taiyo Yuden EMK105B7104KV-F 44 H1, H4, H6 3 Screw, #4 x 0.625" Pan head, sheet metal, Phillips/slotted (for fan) McMaster 90077A112 45 R12, R13, R14 3 Resistor, 5.6k Ω, 1/10W, 5%, 0402 Panasonic ERJ-2GEJ562X 46 R48 1 Resistor 0402 1% 52.
PAGE 2044
Appendix B SPMU372A – September 2015 – Revised October 2016 Schematic This section contains the complete schematics for the TM4C Series TM4C129E Crypto Connected LaunchPad.
PAGE 2045
Revision History www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (September 2015) to A Revision ............................................................................................... Page • GLOBAL: Updated/Changed all instances of "UART4" to "UART2"................................................................
PAGE 2046
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.