Datasheet

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SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
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38
Requirements for Bit Clock and System Clock
In the DSD mode, the bit clock (DBCK) is required on pin 3 of the DSD1796. The frequency of the bit clock can be N times
the sampling frequency. Generally, N is 64 in DSD applications.
The interface timing between the bit clock and DSDL and DSDR is required to meet the same setup-and hold-time
specifications as shown in Figure 40.
SCK is not necessary after the mode change to the DSD mode is complete.
t = 1/(64 × 44.1 kHz)
D1
DSDL
DSDR
D0 D2 D3 D4
DBCK
Figure 39. Normal Data Output Form From DSD Decoder
DSDL
DSDR
t
(BCH)
DBCK
t
(BCL)
t
(BCY)
1.4 V
1.4 V
t
(DS)
t
(DH)
PARAMETER MIN MAX UNITS
t
(BCY)
DBCK pulse cycle time 85
(1)
ns
t
(BCH)
DBCK high-level time 30 ns
t
(BCL)
DBCK low-level time 30 ns
t
(DS)
DSDL, DSDR setup time 10 ns
t
(DH)
DSDL, DSDR hold time 10 ns
(1)
2.8224 MHz × 4. (2.8224 MHz = 64 × 44.1 kHz. This value is specified as a sampling rate of DSD.)
Figure 40. Timing for DSD Audio Interface