Datasheet

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SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
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35
Audio Format
The DSD1796 in the external digital filter interface mode supports right-justified audio formats including 16-bit, 20-bit, and
24-bit audio data, as shown in Figure 36. The audio format is selected by the FMT[2:0] bits of control register 18.
MSB LSB
16
BCK
1/4 f
S
or 1/8 f
S
WDCK
Audio Data Word = 16-Bit
Audio Data Word = 20-Bit
Audio Data Word = 24-Bit
1 2 3 4 5 6 7 8 9 10 11 12 13 14 151615
MSB LSB
161 2 3 4 5 6 7 8 9 10 11 12 13 14 152019 2017 18 19
MSB LSB
161 2 3 4 5 6 7 8 9 10 11 12 13 14 152423 2017 18 19 2421 22 23
DATA,
DATAL, DATAR
DATA,
DATAL, DATAR
DATA,
DATAL, DATAR
Figure 36. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application
System Clock (SCK) and Interface Timing
The DSD1796 in an application using an external digital filter requires the synchronization of WDCK and the system clock.
The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK, DATA, DATAL, and DATAR
is shown in Figure 37.
t
(BCH)
1.4 V
BCK
WDCK
t
(BCL)
t
(LB)
t
(BCY)
t
(DS)
t
(DH)
1.4 V
1.4 V
t
(BL)
DATA
DATAL
DATAR
PARAMETER MIN MAX UNITS
t
(BCY)
BCK pulse cycle time 20 ns
t
(BCL)
BCK pulse duration, LOW 7 ns
t
(BCH)
BCK pulse duration, HIGH 7 ns
t
(BL)
BCK rising edge to WDCK falling edge 5 ns
t
(LB)
WDCK falling edge to BCK rising edge 5 ns
t
(DS)
DATA, DATAL, DATAR setup time 5 ns
t
(DH)
DATA, DATAL, DATAR hold time 5 ns
Figure 37. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application