Datasheet
SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
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21
MODE CONTROL REGISTERS
User-Programmable Mode Controls
The DSD1796 includes a number of user-programmable functions which are accessed via mode control registers. The
registers are programmed using the serial control interface, which is previously desribed in the SERIAL CONTROL
INTERFACE section of this data sheet. Table 2 lists the available mode control functions, along with their default reset
conditions and associated register index.
Table 2. User-Programmable Function Controls
FUNCTION
DEFAULT REGISTER BIT PCM DSD
DF
BYPASS
Digital attenuation control
0 dB to –120 dB and mute, 0.5 dB step
0 dB Register 16
Register 17
ATL[7:0] (for L-ch)
ATR[7:0] (for R-ch)
yes
Attenuation load control—Disabled, enabled Attenuation disabled Register 18 ATLD yes
Input audio data format selection
16-, 20-, 24-bit standard (right-justified) format
24-bit MSB-first left-justified format
16-/24-bit I
2
S format
24-bit I
2
S format Register 18 FMT[2:0] yes yes
Sampling rate selection for de-emphasis
Disabled,44.1 kHz, 48 kHz, 32 kHz
De-emphasis disabled Register 18 DMF[1:0] yes yes
(1)
De-emphasis control—Disabled, enabled De-emphasis disabled Register 18 DME yes
Soft mute control—Mute disabled, enabled Mute disabled Register 18 MUTE yes
Output phase reversal—Normal, reverse Normal Register 19 REV yes yes yes
Attenuation speed selection
×1 f
S
, ×(1/2)f
S
, ×(1/4)f
S
, ×(1/8)f
S
×1 f
S
Register 19 ATS[1:0] yes
DAC operation control—Enabled, disabled DAC operation enabled Register 19 OPE yes yes yes
Zero flag pin operation control
DSD data input, zero flag output
DSD data input Register 19 ZOE yes yes
Stereo DF bypass mode select
Monaural, stereo
Monaural Register 19 DFMS yes
Digital filter rolloff selection
Sharp rolloff, slow rolloff
Sharp rolloff Register 19 FLT yes
Infinite zero mute control
Disabled, enabled
Disabled Register 19 INZD yes yes
System reset control
Reset operation , normal operation
Normal operation Register 20 SRST yes yes yes
DSD interface mode control
DSD enabled, disabled
Disabled Register 20 DSD yes yes
Digital-filter bypass control
DF enabled, DF bypass
DF enabled Register 20 DFTH yes yes
Monaural mode selection
Stereo, monaural
Stereo Register 20 MONO yes yes yes
Channel selection for monaural mode data
L-channel, R-channel
L-channel Register 20 CHSL yes yes yes
Delta-sigma oversampling rate selection
×64 f
S
, ×128 f
S
, ×32 f
S
×64 f
S
Register 20 OS[1:0] yes yes
(2)
yes
PCM zero output enable Enabled Register 21 PCMZ yes yes
DSD zero output enable Disabled Register 21 DZ[1:0] yes
FUNCTION AVAILABLE ONLY FOR READ
Zero detection flag
Not zero, zero detected
Not zero = 0
Zero detected = 1
Register 22 ZFGL (for L-ch)
ZFGR (for R-ch)
yes yes yes
Device ID (at TDMCA) – Register 23 ID[4:0] yes
(1)
When in DSD mode, DMF[1:0] is defined as DSD filter (analog FIR) performance selection.
(2)
When in DSD mode, OS[1:0] is defined as DSD filter (analog FIR) operation rate selection.