Datasheet

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SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006
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15
Power-On and External Reset Functions
The DSD1796 includes a power-on reset function. Figure 24 shows the operation of this function. With V
DD
> 2 V, the
power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time V
DD
> 2 V. After
the initialization period, the DSD1796 is set to its default reset state, as described in the MODE CONTROL REGISTERS
section of this data sheet.
The DSD1796 also includes an external reset capability using the RST input (pin 14). This allows an external controller
or master reset circuit to force the DSD1796 to initialize to its default reset state.
Figure 25 shows the external reset operation and timing. The
RST
pin is set to logic 0 for a minimum of 20 ns. The
RST
pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock periods. The
external reset is especially useful in applications where there is a delay between the DSD1796 power up and system clock
activation.
Reset Reset Removal
1024 System Clocks
V
DD
2.4 V (Max)
2 V (Typ)
1.6 V (Min)
Internal Reset
System Clock
Figure 24. Power-On Reset Timing
Reset Reset Removal
1024 System Clocks
Internal Reset
System Clock
RST (Pin 14)
t
(RST)
1.4 V
PARAMETERS MIN MAX UNITS
t
(RST)
Reset pulse duration, LOW 20 ns
Figure 25. External Reset Timing