Datasheet


SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006
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6
Terminal Functions
TERMINAL
I/O
DESCRIPTIONS
NAME PIN
I/O
DESCRIPTIONS
ADR0 10 I I
2
C address 0
(1)
ADR1 11 I I
2
C address 1
(1)
AGND1 19 – Analog ground (internal bias)
AGND2 24 – Analog ground (internal bias)
AGND3L 27 – Analog ground (L-channel DACFF)
AGND3R 16 – Analog ground (R-channel DACFF)
DBCK 3 I Bit clock input for DSD modes
(1)
DGND 8 – Digital ground
DSDL 1 I/O L-channel audio data input when in DSD and external DF modes
PCM-mode zero flag for L-channel when in zero-flag output mode
(2)
DSDR 2 I/O R-channel audio data input when in DSD and external DF modes
(2)
PCM-mode zero flag for R-channel when in zero-flag output mode
I
OUT
L+ 25 O L-channel analog current output +
I
OUT
L– 26 O L-channel analog current output –
I
OUT
R+ 17 O R-channel analog current output +
I
OUT
R– 18 O R-channel analog current output –
I
REF
20 – Output current reference bias pin
PBCK 6 I Bit clock input. Connected to GND in DSD mode
(1)
PDATA 5 I Serial audio data input for PCM-format operation
(1)
PLRCK 4 I Left and right clock (f
S
) input for PCM-format operation. WDCK clock input for external DF mode.
Connected to GND for DSD mode
(1)
RST 14 I Reset
(1)
SCL 12 I I
2
C clock
(1)
SCK 7 I System clock input
(1)
SDA 13 I/O I
2
C data
(3)
V
CC
1 23 – Analog power supply, 5 V
V
CC
2L 28 – Analog power supply (L-channel DACFF), 5 V
V
CC
2R 15 – Analog power supply (R-channel DACFF), 5 V
V
COM
L 22 – L-channel internal bias decoupling pin
V
COM
R 21 – R-channel internal bias decoupling pin
V
DD
9 – Digital power supply, 3.3 V
(1)
Schmitt-trigger input, 5-V tolerant
(2)
Schmitt-trigger input and output. 5-V tolerant input, and CMOS output
(3)
Schmitt-trigger 5-V tolerant input and open-drain/3-state output