Datasheet

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SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006
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42
DSD MODE CONFIGURATION AND FUNCTION CONTROLS
Configuration for the DSD Interface Mode
DSD = 1 (Register 20, B5)
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Register 16 R/W 0 0 1 0 0 0 0 – – – – – – – –
Register 17 R/W 0 0 1 0 0 0 1 – – – – – – – –
Register 18 R/W 0 0 1 0 0 1 0 – – – – DMF1 DMF0 – –
Register 19 R/W 0 0 1 0 0 1 1 REV – – OPE – – – –
Register 20 R/W 0 0 1 0 1 0 0 – SRST 1 – MONO CHSL OS1 OS0
Register 21 R 0 0 1 0 1 0 1 – – – – – DZ1 DZ0 –
Register 22 R 0 0 1 0 1 1 0 – – – – – – ZFGR ZFGL
NOTE: – indicates that function is disabled. No operation even if data bit is set
DMF[1:0]: Analog FIR Performance Selection
Default value: 00
DMF[1:0] Analog-FIR Performance Select
00 FIR-1 (default)
01 FIR-2
10 FIR-3
11 FIR-4
Plots for the four analog FIR filter responses are shown in the TYPICAL PERFORMANCE CURVES section of this
data sheet.
OS[1:0]: Analog-FIR Operation-Speed Selection
Default value: 00
OS[1:0] Operation Speed Select
00 f
DBCK
(default)
01 f
DBCK
/2
10 Reserved
11 f
DBCK
/4
The OS bit in the DSD mode is used to select the operating rate of the analog FIR. The OS bits must be set before
setting the DSD bit to 1.
Requirements for System Clock
The bit clock (DBCK) for the DSD mode is required at pin 3 of the DSD1794A. The frequency of the bit clock can
be N times the sampling frequency. Generally, N is 64 in DSD applications.
The interface timing between the bit clock and DSDL and DSDR is required to meet the same setup-and hold-time
specifications as shown in Figure 42.