Datasheet


SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006
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35
I
OUT
–
Figure 34
Circuit
I
OUT
+
I
OUT
L– (Pin 26)
I
OUT
L+ (Pin 25)
OUT+
1
2
3
Balanced Out
I
OUT
–
Figure 34
Circuit
I
OUT
+
I
OUT
R– (Pin 18)
I
OUT
R+ (Pin 17)
OUT–
Figure 36. Measurement Circuit for Monaural Mode
APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE
DATA
BCK
SCK
WDCK (Word Clock)
External Filter Device
PDATA
5
6
7
PBCK
SCK
DSDL
1
2
3
4
DSDR
DBCK
PLRCK
DSD1794A
DFMS = 0
BCK
SCK
WDCK (Word Clock)
External Filter Device
PDATA
5
6
7
PBCK
SCK
DSDL
1
2
3
4
DSDR
DBCK
PLRCK
DSD1794A
DFMS = 1
DATA_L
DATA_R
Figure 37. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application