Datasheet

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SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006
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30
R: Read Mode Select
Value is always 1, specifying the readback mode.
ZFGx: Zero-Detection Flag
Where x = L or R, corresponding to the DAC output channel. These bits are available only for readback.
Default value: 00
ZFGx = 0
Not zero
ZFGx = 1 Zero detected
When the DSD1794A detects that audio input data is continuously zero, the ZFGx bit is set to 1 for the corresponding
channel(s).
TYPICAL CONNECTION DIAGRAM
PDATA
24
23
22
21
20
19
18
17
16
15
5
6
7
8
9
10
11
12
13
14
DSD1794A
PBCK
SCK
DGND
V
DD
ADR0
ADR1
SCL
SDA
RST
AGND2
I
OUT
R–
V
CC
1
V
COM
L
V
COM
R
I
REF
I
OUT
R+
AGND3R
AGND1
–
+
DSDL
1
2
3
4
DSDR
DBCK
PLRCK
28
27
26
25
V
CC
2L
AGND3L
I
OUT
L–
I
OUT
L+
DSD
Audio Data
Source
V
OUT
L-Channe
l
5 V
V
CC
2R
0.1 µF
Controller
10 µF
3.3 V
PCM
Audio Data
Source
0.1 µF
10 µF
C
f
R
f
Differential
to
Single
Converter
With
Low-Pass
Filter
+
+
47 µF
47 µF
5 V
10 µF
10 kΩ
–
+
C
f
R
f
–
+
V
OUT
R-Channe
l
C
f
R
f
Differential
to
Single
Converter
With
Low-Pass
Filter
–
+
C
f
R
f
0.1 µF
10 µF
5 V
+
+
+
+
Figure 32. Typical Application Circuit