Datasheet

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SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006
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21
Transmitter
M M M S M S M M M S S M … M M
Data Type St Slave Address W ACK Reg Address ACK Sr Slave Address R ACK Data ACK … NACK Sp
M: Master Device S: Slave Device
St: Start Condition Sr: Repeated Start Condition ACK: Acknowledge
Sp: Stop Condition NACK: Not Acknowledge W: Write R: Read
NOTE: The slave address after the repeat start condition must be the same as the previous slave address.
Figure 31. Read Operation
Noise Suppression
The DSD1794A incorporates noise suppression using the system clock (SCK). However, there must be no more than
two noise spikes in 600 ns. The noise suppression works for SCK frequencies between 8 MHz and 40 MHz in fast
mode. However, it works incorrectly in the following conditions.
Case 1:
1. t
(SCK)
> 120 ns (t
(SCK)
: period of SCK)
2. t
(HI)
+ t
(D-HD)
< t
(SCK)
× 5
3. Spike noise exists on the first half of the SCL HIGH pulse.
4. Spike noise exists on the SDA HIGH pulse just before SDA goes LOW.
SCL
SDA
Noise
When these conditions occur at the same time, the data is recognized as LOW.
Case 2:
1. t(
SCK)
> 120 ns
2. t
(S−HD)
or t
(RS-HD)
< t
(SCK)
× 5
3. Spike noise exists on both SCL and SDA during the hold time.
SCL
SDA
Noise
When these conditions occur at the same time, the DSD1794A fails to detect a start condition.
Case 3:
1. t
(SCK)
< 50 ns
2. t
(SP)
> t
(SCK)
3. Spike noise exists on SCL just after SCL goes LOW.
4. Spike noise exists on SDA just before SCL goes LOW.
SCL
SDA
Noise
When these conditions occur at the same time, the DSD1794A erroneously detects a start or stop condition.