Datasheet
SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006
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19
External Digital Filter Interface and Timing
The DSD1794A supports an external digital filter interface with a 3- or 4-wire synchronous serial port, which allows
the use of an external digital filter. External filters include the Texas Instruments DF1704 and DF1706, the Pacific
Microsonics PMD200, or a programmable digital signal processor.
In the external DF mode, PLRCK (pin 4), PBCK (pin 6) and PDATA (pin 5) are defined as WDCK, the word clock;
BCK, the bit clock; and DATA, the monaural data, respectively. The external digital filter interface is selected by using
the DFTH bit of control register 20, which functions to bypass the internal digital filter of the DSD1794A.
When the DFMS bit of control register 19 is set, the DSD1794A can process stereo data. In this case, DSDL (pin
1) and DSDR (pin 2) are defined as L-channel data and R-channel data input, respectively.
Detailed information for the external digital filter interface mode is provided in the APPLICATION FOR EXTERNAL
DIGITAL FILTER INTERFACE section of this data sheet.
Direct Stream Digital (DSD) Format Interface and Timing
The DSD1794A supports the DSD-format interface operation, which includes out-of-band noise filtering using an
internal analog FIR filter. The DSD-format interface consists of a 3-wire synchronous serial port, which includes
DBCK (pin 3), DSDL (pin 1), and DSDR (pin 2). DBCK is the serial bit clock. DSDL and DSDR are the L-channel and
R-channel DSD data inputs, respectively. They are clocked into the DSD1794A on the rising edge of DBCK. PLRCK
(pin 4) and PBCK (pin 6) are connected to GND in the DSD mode. The DSD-format interface is activated by setting
the DSD bit of control register 20.
Detailed information for the DSD mode is provided in the APPLICATION FOR DSD FORMAT (DSD MODE)
INTERFACE section of this data sheet.
SERIAL CONTROL INTERFACE (I
2
C)
The DSD1794A supports the I
2
C serial bus and the data transmission protocol for standard and fast mode as a slave
device. This protocol is explained in I
2
C specification 2.0.
Slave Address
MSB LSB
1 0 0 1 1 ADR1 ADR0 R/W
The DSD1794A has 7 bits for its own slave address. The first five bits (MSBs) of the slave address are factory preset
to 10011. The next two bits of the address byte are the device select bits which can be user-defined by the ADR1
and ADR0 terminals. A maximum of four DSD1794As can be connected on the same bus at one time. Each
DSD1794A responds when it receives its own slave address.
Packet Protocol
A master device must control packet protocol, which consists of start condition, slave address, read/write bit, data
if write or acknowledge if read, and stop condition. The DSD1794A supports only slave receivers and slave
transmitters.