Datasheet

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SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006
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17
AUDIO DATA INTERFACE
Audio Serial Interface
The audio interface port is a 3-wire serial port. It includes PLRCK (pin 4), PBCK (pin 6), and PDATA (pin 5). PBCK
is the serial audio bit clock, and it is used to clock the serial data present on PDATA into the serial shift register of
the audio interface. Serial data is clocked into the DSD1794A on the rising edge of PBCK. PLRCK is the serial audio
left/right word clock.
The DSD1794A requires the synchronization of PLRCK and the system clock, but does not need a specific phase
relation between PLRCK and the system clock.
If the relationship between PLRCK and the system clock changes more than ±6 PBCK, internal operation is initialized
within 1/f
S
and analog outputs are forced to the bipolar zero level until resynchronization between PLRCK and the
system clock is completed.
PCM Audio Data Formats and Timing
The DSD1794A supports industry-standard audio data formats, including standard right-justified, I
2
S, and
left-justified. The data formats are shown in Figure 28. Data formats are selected using the format bits, FMT[2:0],
in control register 18. The default data format is 24-bit I
2
S. All formats require binary twos-complement, MSB-first
audio data. Figure 27 shows a detailed timing diagram for the serial audio interface.
PDATA
t
(BCH)
50% of V
DD
PBCK
PLRCK
t
(BCL)
t
(LB)
t
(BCY)
t
(DS)
t
(DH)
50% of V
DD
50% of V
DD
t
(BL)
PARAMETERS MIN MAX UNITS
t
(BCY)
PBCK pulse cycle time 70 ns
t
(BCL)
PBCK pulse duration, LOW 30 ns
t
(BCH)
PBCK pulse duration, HIGH 30 ns
t
(BL)
PBCK rising edge to PLRCK edge 10 ns
t
(LB)
PLRCK edge to PBCK rising edge 10 ns
t
(DS)
PDATA Setup time 10 ns
t
(DH)
PDATA hold time 10 ns
— PLRCK clock data 50% ± 2 bit clocks
Figure 27. Timing of Audio Interface